Unit ii arm7 thumb

The Thumb Concept
An Introduction to Thumb
Dr. P. H. Zope
Assistant Professor
SSBT’s COET Bambhori Jalgaon
North Maharashtra University Jalgaon India
phzope@gmail.com
9860631040

On execution, these new 16-bit Thumb opcodes are decompressed by the processor to
their ARM instruction set equivalents, which are then run on an ARM core as normal.
ARM7 TDMI supports Thumb mode.
It contains 36 instruction formats drawn from the standard 32-bit ARM instruction set that
have been re-coded into 16-bit wide op-codes.
Thumb is an extension to the ARM architecture.
ARM instructions are 32 bits wide, and
Thumb instructions are 16 wide.
ARM and Thumb are two different instruction sets supported by ARM cores
Thumb mode allows for code to be smaller, and can potentially be faster if the target has
slow memory.
This brings very high code density, since Thumb instructions are half the width of ARM
instructions.

ARM Encoding characteristics
–fixed width 32 bit ISA
–three address instruction set format
–All instructions are conditional
–16 registers in user space
•Code size as well as power are important for embedded processors.
•ARM provides good performance with low power requirements, at the cost of
code size.
Need for 16 Bit Thumb

Summary of the Thumb Advantage
Excellent code density
The Thumb instruction set gives excellent code density compared to both 32-bit cores
and the 8 and 16-bit processors commonly used in embedded applications. Memory
size and system costs are thereby reduced.
Smallest core die size
Thumb-aware cores have amongst the smallest core die sizes in the industry
(ARM7TDMI is less than 5 mm2 on 0.6m). The ASSP(Application Specific standard
Product) and ASIC designer therefore gets a reduced system die size driven both by a
core that is smaller than common 16/32 bit CISCs and by the reduced requirement for
on-chip programme ROM. Combined with simplified—hence cheaper—testing
compared to CISCs as well as low-power commodity plastic packaging, this brings a
lower- ost produ t tha toda s o o solutio s.
16-bit instructions
Thumb instructions are only 16-bits long, meaning that the system data bus need
only be 16-bits wide. This reduces both power consumption and PCB area, leading to
lower-cost, lower-power systems.

Full 32-bit architecture
Thu i stru tio s e e ute o A‘M s full -bit RISC architecture. The designer is
therefore able to exploit fast 32-bit maths and a simple unsegmented memory mapthat
has a 4 GByte address space; room for the most complex of embedded control
applications.
The standard architecture combined with new tools that can compile for ARM code,
Thumb code, or a mixture of both, guarantees forward compatibility with the existing
32-bit ARM family. This provides the 16-bit system designer with a future migration
route to an already-exisiting family of 32-bit cores.
Code size and performance
Thumb-aware cores such as the ARM7TDMI execute both 32-bit ARM and the new16-bit
Thumb instructions. Designers can mix routines of Thumb and ARM code in thesame
address space. This allows the programmer to trade-off code size andperformance,
routine by routine, as required by the application.
Enhanced ARM software toolkit
The new Thumb instructions are fully supported by an enhanced ARM toolkit which
is Thu -a are . This toolkit i lude a Mi rosoft Wi do s I tegrated De elop e t
Environment, Kanji support and seamless interworking between Thumb and ARM
states.

Protected investment
Investment in existing ARM software is protected, as Thumb-aware cores execute
ARM code. For use in Thumb state, existing source code only needs recompiling.
Building on the ARM advantage
The new family of Thumb-aware cores will build on the standard ARM advantages of
extremely low power consumption, industry-leading MIPS/Watt performance, small
die size for integration/low cost and global multi-vendor sourcing.

Thumb-aware core in a system
The following three configurations demonstrate a Thumb-aware core in a system
This system benefits from the narrow external bus and memory that low-cost
embedded applications demand.
The controller integrates customer-specific on-chip peripherals as well as small
amounts of fast 32-bit ROM or RAM which is used to store speed-critical code.
When the Thumb-aware core switches into ARM state for extra performance
such as in the case of an interrupt, ARM code is executed out of this area of fast
memory. External 16-bit ROM is used for code and constants storage while 8-bit
RAM contains scratchpad data.
Low-cost 16-bit controller and memory system

32-bit* system with low-cost ROM
This configuration shows how a Thumb-aware core can be used with slow, low-cost
32-bit ROM.
The ROM stores a mixture of routines of 32-bit ARM code with one instruction per
32-bit word and routines of Thumb code with two instructions per word. Each
external fetch draws either one 32-bit ARM instruction or two 16-bit Thumb
instructions. ARM instructions flow into the core pipeline in the usual way.
However, in Thumb state, one Thumb instruction goes into the pipeline while the
other is stored on a 16-bit latch, which is effectively a one-instruction prefetch
buffer. At the next fetch, this stored instruction is immediately available to the
core.

Simulations have shown that in this configuration with 200nS ROM, the Thumb
solution will outperform a standard ARM core by between 10 and 20% depending
on code and processor clock frequency. This is because the ARM solution incurs
wait-states whilst fetching each instruction from the ROM, whereas the Thumbaware
solution only has to wait for one instruction in every two.
With high speed ROM that is clocked at the processor frequency, no wait states
are incurred and hence the ARM solution will always outperform the Thumb-aware
core.

This solution represents the final Thumb-aware step before moving to a standard
ARM core for its extra performance in 32-bit systems.
High performance 32-bit system
Using high-speed ROM and an on-chip cache, this system offers the highest
performance of Thumb-aware solutions since 32-bit ARM instructions can be run
straight out of fast memory. Code size and system cost are obviously greater than the
low-cost 16-bit bus and memory systems.

When operating in the 16-bit Thumb state, the application encounters a slightly different
set of registers. Figure 1 compares the programmer's model in that state to the same
model in the 32-bit ARM state.
Figure 1 ARM vs. Thumb
programmer's models
In the ARM state, 17 registers are visible in user mode. One
additional register—a saved copy of Current Program
Status Register (CPSR) that's called SPSR (Saved Program
Status Register)—is for exception mode only.
12 registers accessible in Thumb state are exactly the same
physical 32-bit registers accessible in ARM state. Thus data
can be passed between software running in the ARM state
and software running in the Thumb state via registers R0
through R7.
The biggest register difference involves the SP register.
The Thumb state has unique stack mnemonics (PUSH,
POP) that don't exist in the ARM state. These
instructions assume the existence of a stack pointer, for
which R13 is used. They translate into load and store
instructions in the ARM state.

The CPSR register holds the processor mode (user or exception flag), interrupt mask bits,
condition codes, and Thumb status bit. The Thumb status bit (T) indicates the processor's
current state: 0 for ARM state (default) or 1 for Thumb. Although other bits in the CPSR
may be modified in software, it's dangerous to write to T directly; the results of an
improper state change are unpredictable.

The Instruction Pipeline
• The ARM uses a pipeline in order to increase the speed of the flow of
instructions to the processor.
– Allows several operations to be undertaken simultaneously, rather
than serially.
• Rather than pointing to the instruction being executed, the PC points
to the instruction being fetched.
FETCH
DECODE
EXECUTE
Instruction fetched from memory
Decoding of registers used in instruction
Register(s) read from Register Bank
Shift and ALU operation
Write register(s) back to Register Bank
PC
PC - 4
PC - 8
ARM

Conditional Execution
• Most instruction sets only allow branches to be executed
conditionally.
• However by reusing the condition evaluation hardware, ARM
effectively increases number of instructions.
– All instructions contain a condition field which determines
whether the CPU will execute them.
– Non-executed instructions soak up 1 cycle.
• Still have to complete cycle so as to allow fetching and
decoding of following instructions.
• This removes the need for many branches, which stall the pipeline
(3 cycles to refill).
– Allows very dense in-line code, without branches.
– The Time penalty of not executing several conditional
instructions is frequently less than overhead of the branch
or subroutine call that would otherwise be needed.

Using and updating the
Condition Field
• To execute an instruction conditionally, simply postfix it with the
appropriate condition:
– For example an add instruction takes the form:
– ADD r0,r1,r2 ; r0 = r1 + r2 (ADDAL)
– To execute this only if the zero flag is set:
– ADDEQ r0,r1,r2 ; If zero flag set then…
; ... r0 = r1 + r2
• By default, data processing operations do not affect the condition flags
(apart from the comparisons where this is the only effect). To cause the
condition flags to be updated, the S bit of the instruction needs to be set
postfi i g the i stru tio a d a o ditio ode ith a “ .
– For example to add two numbers and set the condition flags:
– ADDS r0,r1,r2 ; r0 = r1 + r2
; ... and set
flags

* Branch : B{<cond>} label
* Branch with Link : BL{<cond>} sub_routine_label
* The offset for branch instructions is calculated by the assembler:
• By taking the difference between the branch instruction and
the target address minus 8 (to allow for the pipeline).
• This gives a 26 bit offset which is right shifted 2 bits (as the
bottom two bits are always zero as instructions are word –
aligned) and stored into the instruction encoding.
• This gives a range of ± 32 Mbytes.
Branch instructions (1)
2831 24 0
Cond 1 0 1 L Offset
Condition field
Link bit 0 = Branch
1 = Branch with link
232527

Branch instructions (2)
• When executing the instruction, the processor:
– shifts the offset left two bits, sign extends it to 32 bits, and adds it to
PC.
• Execution then continues from the new PC, once the pipeline has been
refilled.
• The "Branch with link" instruction implements a subroutine call by
writing PC-4 into the LR of the current bank.
– i.e. the address of the next instruction following the branch with link
(allowing for the pipeline).
• To return from subroutine, simply need to restore the PC from the LR:
• MOV pc, lr
– Again, pipeline has to refill before execution continues.
• The "Branch" instruction does not affect LR.
• Note: Architecture 4T offers a further ARM branch instruction, BX
– See Thumb Instruction Set Module for details.

Data processing Instructions
• Largest family of ARM instructions, all sharing the same instruction
format.
• Contains:
– Arithmetic operations
– Comparisons (no results - just set condition codes)
– Logical operations
– Data movement between registers
• Remember, this is a load / store architecture
– These instruction only work on registers, NOT memory.
• They each perform a specific operation on one or two operands.
– First operand always a register - Rn
– Second operand sent to the ALU via barrel shifter.
• We will examine the barrel shifter shortly.

Arithmetic Operations
• Operations are:
– ADD operand1 + operand2
– ADC operand1 + operand2 + carry
– SUB operand1 - operand2
– SBC operand1 - operand2 + carry -1
– RSB operand2 - operand1
– RSC operand2 - operand1 + carry - 1
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples
– ADD r0, r1, r2
– SUBGT r3, r3, #1
– RSBLES r4, r5, #5

Comparisons
• The only effect of the comparisons is to
– UPDATE THE CONDITION FLAGS. Thus no need to set S bit.
• Operations are:
– CMP operand1 - operand2, but result not written
– CMN operand1 + operand2, but result not written
– TST operand1 AND operand2, but result not written
– TEQ operand1 EOR operand2, but result not written
• Syntax:
– <Operation>{<cond>} Rn, Operand2
• Examples:
– CMP r0, r1
– TSTEQ r2, #5

Logical Operations
• Operations are:
– AND operand1 AND operand2
– EOR operand1 EOR operand2
– ORR operand1 OR operand2
– BIC operand1 AND NOT operand2 [ie bit clear]
• Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
• Examples:
– AND r0, r1, r2
– BICEQ r2, r3, #7
– EORS r1,r3,r0

Data Movement
• Operations are:
– MOV operand2
– MVN NOT operand2
Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2
• Examples:
– MOV r0, r1
– MOVS r2, #10
– MVNEQ r1,#0

The Barrel Shifter
• The A‘M does t ha e a tual shift i stru tio s.
• Instead it has a barrel shifter which provides a mechanism to carry out
shifts as part of other instructions.
• So what operations does the barrel shifter support?

* Shifts left by the specified amount (multiplies by powers of two) e.g.
LSL #5 = multiply by 32
Barrel Shifter - Left Shift
Logical Shift Left (LSL)
DestinationCF 0

Logical Shift Right
•Shifts right by the
specified amount
(divides by powers of
two) e.g.
LSR #5 = divide by 32
Arithmetic Shift Right
•Shifts right (divides by
powers of two) and
preserves the sign bit,
for 2's complement
operations. e.g.
ASR #5 = divide by 32
Barrel Shifter - Right Shifts
Destination CF
Destination CF
Logical Shift Right
Arithmetic Shift Right
...0
Sign bit shifted in

Barrel Shifter - Rotations
Rotate Right (ROR)
• Similar to an ASR but
the bits wrap around as they
leave the LSB and appear as
the MSB.
e.g. ROR #5
•Note the last bit rotated is
also used as the Carry Out.
Rotate Right Extended (RRX)
• This operatio uses the
CPSR C flag as a 33rd bit.
•Rotates right by 1 bit.
Encoded as ROR #0.
Destination CF
Rotate Right
Destination CF
Rotate Right through
Carry

Using the Barrel Shifter:
The Second Operand
* Immediate value
• 8 bit number
• Can be rotated right
through an even number
of positions.
• Assembler will calculate
rotate for you from
constant.
• Register, optionally with shift
operation applied.
• Shift value can be either be:
– 5 bit unsigned integer
– Specified in bottom byte of
another register.
Operand 1
Result
ALU
Barrel
Shifter
Operand 2

Second Operand :
Shifted Register
• The amount by which the register is to be shifted is contained in
either:
– the immediate 5-bit field in the instruction
• NO OVERHEAD
• Shift is done for free - executes in single cycle.
– the bottom byte of a register (not PC)
• Then takes extra cycle to execute
• A‘M does t ha e e ough read ports to read registers
at once.
• Then same as on other processors where shift is
separate instruction.
• If no shift is specified then a default shift is applied: LSL #0
– i.e. barrel shifter has no effect on value in register.

Second Operand : Using a Shifted Register
• Using a multiplication instruction to multiply by a constant means first
loading the constant into a register and then waiting a number of
internal cycles for the instruction to complete.
• A more optimum solution can often be found by using some
combination of MOVs, ADDs, SUBs and RSBs with shifts.
– Multiplications by a constant equal to a ((power of 2) ± 1) can be
done in one cycle.
• Example: r0 = r1 * 5
Example: r0 = r1 + (r1 * 4)
ADD r0, r1, r1, LSL #2
• Example: r2 = r3 * 105
Example: r2 = r3 * 15 * 7
Example: r2 = r3 * (16 - 1) * (8 - 1)
RSB r2, r3, r3, LSL #4 ; r2 = r3 * 15
RSB r2, r2, r2, LSL #3 ; r2 = r2 * 7

Second Operand : Immediate Value
• There is no single instruction which will load a 32 bit immediate
constant into a register without performing a data load from memory.
– All ARM instructions are 32 bits long
– ARM instructions do not use the instruction stream as data.
• The data processing instruction format has 12 bits available for
operand2
– If used directly this would only give a range of 4096.
• Instead it is used to store 8 bit constants, giving a range of 0 - 255.
• These 8 bits can then be rotated right through an even number of
positions (ie RORs by 0, 2, 4,..30).
– This gives a much larger range of constants that can be directly
loaded, though some constants will still need to be loaded
from memory.

Second Operand : Immediate Value
• This gives us:
– 0 - 255 [0 - 0xff]
– 256,260,264,..,1020 [0x100-0x3fc, step 4, 0x40-0xff ror 30]
– 1024,1040,1056,..,4080 [0x400-0xff0, step 16, 0x40-0xff ror 28]
– 4096,4160, 4224,..,16320 [0x1000-0x3fc0, step 64, 0x40-0xff ror
26]
• These can be loaded using, for example:
– MOV r0, #0x40, 26 ; => MOV r0, #0x1000 (ie 4096)
• To make this easier, the assembler will convert to this form for us if
simply given the required constant:
– MOV r0, #4096 ; => MOV r0, #0x1000 (ie 0x40 ror 26)
• The bitwise complements can also be formed using MVN:
– MOV r0, #0xFFFFFFFF ; assembles to MVN r0, #0
• If the required constant cannot be generated, an error will
be reported.

Loading full 32 bit constants
• Although the MOV/MVN mechansim will load a large range of constants
into a register, sometimes this mechansim will not generate the
required constant.
• Therefore, the assembler also provides a method which will load ANY 32
bit constant:
• LDR rd,=numeric constant
• If the constant can be constructed using either a MOV or MVN then this
will be the instruction actually generated.
• Otherwise, the assembler will produce an LDR instruction with a PC-
relative address to read the constant from a literal pool.
• LDR r0,=0x42 ; generates MOV r0,#0x42
• LDR r0,=0x55555555 ; generate LDR r0,[pc,
offset to lit pool]
• As this mechanism will always generate the best instruction for a given
case, it is the recommended way of loading constants.

Multiplication Instructions
• The Basic ARM provides two multiplication instructions.
• Multiply
– MUL{<cond>}{S} Rd, Rm, Rs ; Rd = Rm * Rs
• Multiply Accumulate - does addition for free
– MLA{<cond>}{S} Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn
• Restrictions on use:
– Rd and Rm cannot be the same register
• Can be avoid by swapping Rm and Rs around. This works
because multiplication is commutative.
– Cannot use PC.
These will be picked up by the assembler if overlooked.
• Operands can be considered signed or unsigned
– Up to user to interpret correctly.

Multiplication Implementation
• The A‘M akes use of Booth s Algorith to perfor i teger
multiplication.
• On non-M ARMs this operates on 2 bits of Rs at a time.
– For each pair of bits this takes 1 cycle (plus 1 cycle to start with).
– Ho e er he there are o ore s left i ‘s, the ultipli atio
will early-terminate.
• Example: Multiply 18 and -1 : Rd = Rm * Rs
• Note: Compiler does not use early termination criteria to
decide on which order to place operands.
0 0 0 0 0 0 1 00 0 0 10 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1 1 1 1 1 1 1 1 1
Rm
Rs
17
cycles
Rs
Rm
4 cycles
18
-1
18
-1

Extended Multiply Instructions
• M variants of ARM cores contain extended multiplication
hardware. This provides three enhancements:
– An 8 bit Booth’s Algorithm is used
• Multiplication is carried out faster (maximum for standard
instructions is now 5 cycles).
– Early termination method improved so that now completes
multiplication when all remaining bit sets contain
• all zeroes (as with non-M ARMs), or
• all ones.
Thus the previous example would early terminate in 2 cycles in
both cases.
– 64 bit results can now be produced from two 32bit operands
• Higher accuracy.
• Pair of registers used to store result.

Multiply-Long and
Multiply-Accumulate Long
• Instructions are
– MULL which gives RdHi,RdLo:=Rm*Rs
– MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
• However the full 64 bit of the result now matter (lower precision
multiply instructions simply throws top 32bits away)
– Need to specify whether operands are signed or unsigned
• Therefore syntax of new instructions are:
– UMULL{<cond>}{S} RdLo,RdHi,Rm,Rs
– UMLAL{<cond>}{S} RdLo,RdHi,Rm,Rs
– SMULL{<cond>}{S} RdLo, RdHi, Rm, Rs
– SMLAL{<cond>}{S} RdLo, RdHi, Rm, Rs
• Not generated by the compiler.
Warning : Unpredictable on non-M ARMs.

Load / Store Instructions
• The ARM is a Load / Store Architecture:
– Does not support memory to memory data processing
operations.
– Must move data values into registers before using them.
• This ight sou d i effi ie t, ut i pra ti e is t:
– Load data values from memory into registers.
– Process data in registers using a number of data processing
instructions which are not slowed down by memory access.
– Store results from registers out to memory.
• The ARM has three sets of instructions which interact with main
memory. These are:
– Single register data transfer (LDR / STR).
– Block data transfer (LDM/STM).
– Single Data Swap (SWP).

Single register data transfer
• The basic load and store instructions are:
– Load and Store Word or Byte
• LDR / STR / LDRB / STRB
• ARM Architecture Version 4 also adds support for halfwords and signed
data.
– Load and Store Halfword
• LDRH / STRH
– Load Signed Byte or Halfword - load value and sign extend it to 32
bits.
• LDRSB / LDRSH
• All of these instructions can be conditionally executed by inserting the
appropriate condition code after STR / LDR.
– e.g. LDREQB
• Syntax:
– <LDR|STR>{<cond>}{<size>} Rd, <address>

Load and Store Word or Byte:
Base Register
• The memory location to be accessed is held in a base register
– STR r0, [r1] ; Store contents of r0 to location pointed to
; by contents of r1.
– LDR r2, [r1] ; Load r2 with contents of memory location
; pointed to by contents of r1.
r1
0x200
Base
Register
Memory
0x50x200
r0
0x5
Source
Register
for STR
r2
0x5
Destinatio
n
Register
for LDR

Offsets from the Base Register
• As well as accessing the actual location contained in the base register,
these instructions can access a location offset from the base register
pointer.
• This offset can be
– An unsigned 12bit immediate value (ie 0 - 4095 bytes).
– A register, optionally shifted by an immediate value
• This can be either added or subtracted from the base register:
– Prefi the offset alue or register ith + default or - .
• This offset can be applied:
– before the transfer is made: Pre-indexed addressing
• optionally auto-incrementing the base register, by postfixing
the i stru tio ith a ! .
– after the transfer is made: Post-indexed addressing
• causing the base register to be auto-incremented.

Pre-indexed Addressing
• Example: STR r0, [r1,#12]
• To store to location 0x1f4 instead use: STR r0, [r1,#-12]
• To auto-increment base pointer to 0x20c use: STR r0, [r1, #12]!
• If r2 contains 3, access 0x20c by multiplying this by 4:
– STR r0, [r1, r2, LSL #2]
r1
0x200
Base
Register
Memory
0x5
0x200
r0
0x5
Source
Register
for STR
Offset
12 0x20c

Post-indexed Addressing
• Example: STR r0, [r1], #12
• To auto-increment the base register to location 0x1f4 instead use:
– STR r0, [r1], #-12
• If r2 contains 3, auto-incremenet base register to 0x20c by multiplying
this by 4:
– STR r0, [r1], r2, LSL #2
r1
0x200
Original
Base
Register
Memory
0x50x200
r0
0x5
Source
Register
for STR
Offset
12 0x20c
r1
0x20c
Updated
Base
Register

Load and Stores
with User Mode Privilege
• When using post-indexed addressing, there is a further form of
Load/Store Word/Byte:
– <LDR|STR>{<cond>}{B}T Rd, <post_indexed_address>
• When used in a privileged mode, this does the load/store with user
mode privilege.
– Normally used by an exception handler that is emulating a memory
access instruction that would normally execute in user mode.

Example Usage of
Addressing Modes
• Imagine an array, the first element of which is pointed to by the
contents of r0.
• If we want to access a particular element,
then we can use pre-indexed addressing:
– r1 is element we want.
– LDR r2, [r0, r1, LSL #2]
• If we want to step through every
element of the array, for instance
to produce sum of elements in the
array, then we can use post-indexed addressing within a loop:
– r1 is address of current element (initially equal to r0).
– LDR r2, [r1], #4
Use a further register to store the address of final element,
so that the loop can be correctly terminated.
0
1
2
3
element
0
4
8
12
Memory
Offset
r0
Pointer to
start of array

Offsets for Halfword and
Signed Halfword / Byte Access
• The Load and Store Halfword and Load Signed Byte or Halfword
instructions can make use of pre- and post-indexed addressing in much
the same way as the basic load and store instructions.
• However the actual offset formats are more constrained:
– The immediate value is limited to 8 bits (rather than 12 bits) giving
an offset of 0-255 bytes.
– The register form cannot have a shift applied to it.

Effect of endianess
• The ARM can be set up to access its data in either little or big
endian format.
• Little endian:
– Least significant byte of a word is stored in bits 0-7 of an
addressed word.
• Big endian:
– Least significant byte of a word is stored in bits 24-31 of an
addressed word.
• This has no real relevance unless data is stored as words and then
accessed in smaller sized quantities (halfwords or bytes).
– Which byte / halfword is accessed will depend on the
endianess of the system involved.

Endianess Example
Big-endianLittle-
endian
r1 = 0x100
r0 = 0x11223344
31 24 23 16 15 8 7
0
11 22 33
44
31 24 23 16 15 8 7
0
11 22 33
44
31 24 23 16 15 8 7
0
44 33 22
11
31 24 23 16 15 8 7
0
00 00 00
44
31 24 23 16 15 8 7
0
00 00 00
11
r2 = 0x44 r2 = 0x11
STR r0, [r1]
LDRB r2, [r1]
r1 = 0x100Memory

Block Data Transfer (1)
Cond 1 0 0 P U S W L Rn Register list
Condition field Base register
Load/Store bit
0 = Store to memory
1 = Load from memory
Write- back bit
0 = no write-back
1 = write address into base
PSR and force user bit
0 = don’t load PSR or force user mode
1 = load PSR or force user mode
Up/Down bit
0 = Down; subtract offset from base
1 = Up ; add offset to base
Pre/Post indexing bit
0 = Post; add offset after transfer,
1 = Pre ; add offset before transfer
2831 22 16 023 21 1527 20 1924
Each bit corresponds to a
particular register. For example:
• Bit 0 set causes r0 to be transferred.
• Bit 0 unset causes r0 not to be transferred.
At least one register must be
transferred as the list cannot be
empty.
• The Load and Store Multiple instructions (LDM / STM) allow betweeen 1
and 16 registers to be transferred to or from memory.
• The transferred registers can be either:
– Any subset of the current bank of registers (default).
– Any subset of the user mode bank of registers when in a priviledged
ode postfi i stru tio ith a ^ .

Block Data Transfer (2)
• Base register used to determine where memory access should occur.
– 4 different addressing modes allow increment and decrement
inclusive or exclusive of the base register location.
– Base register can be optionally updated following the transfer (by
appe di g it ith a ! .
– Lowest register number is always transferred to/from lowest
memory location accessed.
• These instructions are very efficient for
– Saving and restoring context
• For this useful to view memory as a stack.
– Moving large blocks of data around memory
• For this useful to directly represent functionality of the
instructions.

Stacks
• A sta k is a area of e or hi h gro s as e data is pushed o to
the top of it, a d shri ks as data is popped off the top.
• Two pointers define the current limits of the stack.
– A base pointer
• used to poi t to the otto of the sta k the first lo atio .
– A stack pointer
• used to poi t the urre t top of the sta k.
SP
BASE
PUSH
{1,2,3}
1
2
3
BASE
SP
POP
1
2
Result of
pop = 3
BASE
SP

Stack Operation
• Traditio all , a sta k gro s do i e or , ith the last pushed
value at the lowest address. The ARM also supports ascending stacks,
where the stack structure grows up through memory.
• The value of the stack pointer can either:
– Point to the last occupied address (Full stack)
• and so needs pre-decrementing (ie before the push)
– Point to the next occupied address (Empty stack)
• and so needs post-decrementing (ie after the push)
• The stack type to be used is given by the postfix to the instruction:
– STMFD / LDMFD : Full Descending stack
– STMFA / LDMFA : Full Ascending stack.
– STMED / LDMED : Empty Descending stack
– STMEA / LDMEA : Empty Ascending stack
• Note: ARM Compiler will always use a Full descending stack.

Stack Examples
STMFD sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0S
P
Old SP
STMED sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0
S
P
Old SP
r5
r4
r3
r1
r0
STMFA sp!,
{r0,r1,r3-r5}
S
P
Old SP 0x400
0x418
0x3e8
STMEA sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0
S
P
Old SP

Stacks and Subroutines
• One use of stacks is to create temporary register workspace for
subroutines. Any registers that are needed can be pushed onto the stack
at the start of the subroutine and popped off again at the end so as to
restore them before return to the caller :
STMFD sp!,{r0-r12, lr} ; stack all
registers
........ ; and the return address
........
LDMFD sp!,{r0-r12, pc} ; load all the
registers
; and return automatically
• See the chapter on the ARM Procedure Call Standard in the SDT
Reference Manual for further details of register usage within
subroutines.
• If the pop i stru tio also had the “ it set usi g ^ the the tra sfer
of the PC when in a priviledged mode would also cause the SPSR to be
copied into the CPSR (see exception handling module).

Direct functionality of
Block Data Transfer
• When LDM / STM are not being used to implement stacks, it is clearer to
specify exactly what functionality of the instruction is:
– i.e. specify whether to increment / decrement the base pointer,
before or after the memory access.
• In order to do this, LDM / STM support a further syntax in addition to
the stack one:
– STMIA / LDMIA : Increment After
– STMIB / LDMIB : Increment Before
– STMDA / LDMDA : Decrement After
– STMDB / LDMDB : Decrement Before

Example: Block Copy
– Copy a block of memory, which is an exact multiple of 12 words long
from the location pointed to by r12 to the location pointed to by r13.
r14 points to the end of block to be copied.
; r12 points to the start of the source data
; r14 points to the end of the source data
; r13 points to the start of the destination data
loop LDMIA r12!, {r0-r11} ; load 48 bytes
STMIA r13!, {r0-r11} ; and store them
CMP r12, r14 ; check for the end
BNE loop ; and loop until done
– This loop transfers 48 bytes in 31 cycles
– Over 50 Mbytes/sec at 33 MHz
r13
r14
r12
Increasing
Memory

* Atomic operation of a memory read followed by a memory write
which moves byte or word quantities between registers and memory.
* Syntax:
• SWP{<cond>}{B} Rd, Rm, [Rn]
* Thus to implement an actual swap of contents make Rd = Rm.
* The compiler cannot produce this instruction.
Swap and Swap Byte Instructions
Rm Rd
Rn
32
1
temp
Memory

Software Interrupt (SWI)
• In effect, a SWI is a user-defined instruction.
• It causes an exception trap to the SWI hardware vector (thus causing a
change to supervisor mode, plus the associated state saving), thus
causing the SWI exception handler to be called.
• The handler can then examine the comment field of the instruction to
decide what operation has been requested.
• By making use of the SWI mechansim, an operating system can
implement a set of privileged operations which applications running in
user mode can request.
• See Exception Handling Module for further details.
2831 2427 0
Cond 1 1 1
1
Comment field (ignored by Processor)
Condition Field
23

The ARM instruction set contains the following sections:
•Instruction set encoding
•The condition field
•Branch instructions
•Data-processing instructions
•Multiply instructions
•Parallel addition and subtraction instructions
•Extend instructions
•Miscellaneous arithmetic instructions
•Other miscellaneous instructions
•Status register access instructions
•Load and store instructions
•Load and Store Multiple instructions
•Semaphore instructions
•Exception-generating instructions
•Coprocessor instructions
•Extending the instruction set
ARM 7 instruction set Classification

ARM Instruction Set Format
Instruction type
Data processing / PSR Transfer
Multiply
Long Multiply (v3M / v4 only)
Swap
Load/Store Byte/Word
Load/Store Multiple
Halfword transfer : Immediate offset (v4 only)
Halfword transfer: Register offset (v4 only)
Branch
Branch Exchange (v4T only)
Coprocessor data transfer
Coprocessor data operation
Coprocessor register transfer
Software interrupt
Cond 0 0 I Opcode S Rn Rd Operand2
Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm
Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm
Cond 0 1 I P U B W L Rn Rd Offset
Cond 1 0 0 P U S W L Rn Register List
Cond 0 0 0 0 1 U A S RdHi RdLo Rs 1 0 0 1 Rm
Cond 0 0 0 P U 1 W L Rn Rd Offset1 1 S H 1 Offset2
Cond 1 0 1 L Offset
Cond 1 1 0 P U N W L Rn CRd CPNum Offset
Cond 1 1 1 0 Op1 CRn CRd CPNum Op2 0 CRm
Cond 1 1 1 0 Op1 L CRn Rd CPNum Op2 1 CRm
Cond 1 1 1 1 SWI Number
Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn
Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm
31 2827 1615 87 0
Instruction set encoding
The instruction set encoding is as shown below

The condition field
Most ARM instructions can be conditionally executed, which means that they
only have their normal effect on the programmers’ model state, memory and
coprocessors if the N, Z, C and V flags in the CPSR satisfy a condition specified
in the instruction. If the flags do not satisfy this condition, the instruction acts as
a NOP: that is, execution advances to the next instruction as normal, including
any relevant checks for interrupts and Prefetch Aborts, but has no other effect.
Every instruction contains a 4-bit condition code field in bits 31 to 28:

The Condition Field
2831 24 20 16 12 8 4 0
Cond
0000 = EQ - Z set (equal)
0001 = NE - Z clear (not equal)
0010 = HS / CS - C set (unsigned higher
or same)
0011 = LO / CC - C clear (unsigned lower)
0100 = MI -N set (negative)
0101 = PL - N clear (positive or zero)
0110 = VS - V set (overflow)
0111 = VC - V clear (no overflow)
1000 = HI - C set and Z clear (unsigned
higher)
1001 = LS - C clear or Z (set unsigned lower or
same)
1010 = GE - N set and V set, or N clear and V clear
(>or =)
1011 = LT - N set and V clear, or N clear and V set
(>)
1100 = GT - Z clear, and either N set and V set, or N
clear and V set (>)
1101 = LE - Z set, or N set and V clear,or N clear
and V set (<, or =)
1110 = AL - always
1111 = NV - reserved.

Study of On-chip peripherals
LPC 2148 Key features
■ 16-bit/32-bit ARM microcontroller in a tiny LQFP64 package.
■ 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit wide
interface/accelerator enables high-speed 60 MHz operation.
■ In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single
flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
■ EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real
Monitor software and high-speed tracing of instruction execution.
■ USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition, the LPC2146/48
provides 8 kB of on-chip RAM accessible to USB by DMA.
■ One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with
conversion times as low as 2.44 μs per channel.
■ Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
■ Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit
(six outputs) and watchdog.

■ Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
■ Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI
and SSP with buffering and variable data length capabilities.
■ Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
■ Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
■ Up to 21 external interrupt pins available.
■ 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of
100 μs.
■ On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.
■ Power saving modes include Idle and Power-down.
■ Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
■ Processor wake-up from Power-down mode via external interrupt or BOD.
■ Single power supply chip with POR and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

Fast general purpose parallel I/O (GPIO)
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers
allow setting or clearing any number of outputs simultaneously. The value of the output
register may be read back, as well as the current state of the port pins.
LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices:
• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
• Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
• All GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of bits in
one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.

10-bit ADC
The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters.
These converters are single 10-bit successive approximation analog to digital converters.
While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available
ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
Features
• 10 bit successive approximation analog to digital converter.
• Measurement range of 0 V to VREF (2.0 V ≤ VREF ≤ VDDA).
• Each converter capable of performing more than 400,000 10-bit samples per second.
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or timer match signal.
• Global Start command for both converters (LPC2142/44/46/48 only).

10-bit DAC
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog
output. The maximum DAC output voltage is the VREF voltage.
Features
• 10-bit DAC.
• Buffered output.
• Power-down mode available.
• Selectable speed versus power.

The USB is a 4-wire serial bus that supports communication between a host and a
number (127 max) of peripherals. The host controller allocates the USB bandwidth
to attached devices through a token based protocol. The bus supports hot plugging,
unplugging, and dynamic configuration of the devices. All transactions are initiated
by the host controller.
The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12
Mbit/s data exchange with a USB host controller. It consists of a register interface,
serial interface engine, endpoint buffer memory and DMA controller. The serial
interface engine decodes the USB data stream and writes data to the appropriate
end point buffer memory. The status of a completed USB transfer or error condition
is indicated via status registers. An interrupt is also generated if enabled. A DMA
controller (available in LPC2146/48 only) can transfer data between an endpoint
buffer and the USB RAM.
USB 2.0 device controller

Features
• Fully compliant with USB 2.0 Full-speed specification.
• Supports 32 physical (16 logical) endpoints.
• Supports control, bulk, interrupt and isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum specification) by software at
run time.
• RAM message buffer size based on endpoint realization and maximum packet size.
• Supports SoftConnect and GoodLink LED indicator. These two functions are sharing one pin.
• Supports bus-powered capability with low suspend current.
• Supports DMA transfer on all non-control endpoints (LPC2146/48 only).
• One duplex DMA channel serves all endpoints (LPC2146/48 only).
• Allows dynamic switching between CPU controlled and DMA modes (only in LPC2146/48).
• Double buffer implementation for bulk and isochronous endpoints.
USB 2.0 device controller

The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive
data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a
fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard
baudrates such as 115200 with any crystal frequency above 2 MHz.
In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware
Features
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
• Built-in fractional baud rate generator covering wide range of baud rates without a need for
external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both
UARTs.
• LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
UARTs

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a
full duplex serial interface, designed to handle multiple masters and
slaves connected to a given bus. Only a single master and a single slave
can communicate on the interface during a given data transfer. During a
data transfer the master always sends a byte of data to the slave, and the
slave always sends a byte of data to the master.
Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex, Communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
SPI serial I/O controller

I2C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial
clock line (SCL), and a serial data line (SDA). Each device is recognized by
a unique address and can operate as either a receiver-only device (e.g., an
LCD driver or a transmitter with the capability to both receive and send
information (such as memory)). Transmitters and/or receivers can operate in
either master or slave mode, depending on whether the chip has to initiate a
data transfer or is only addressed. The I2C-bus is a multi-master bus, it can
be controlled by more than one bus master connected to it. The I2C-bus
implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
(Fast I2C-bus).

Features
• Compliant with standard I2C-bus interface.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus.
• Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.

Unit ii arm7 thumb

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