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Author(s): Youn,Long Steve Lin, Chao,Yang Kao, Hung,Chih Kuo, Jian,Wen
Chen
ISBN(s): 9781441909589, 1441909583
Edition: 2010
File Details: PDF, 29.76 MB
Year: 2010
Language: english

Youn-Long Steve Lin • Chao-Yang Kao
Huang-Chih Kuo • Jian-Wen Chen
VLSI Design for
Video Coding
H.264/AVC Encoding from Standard
Specification to Chip
123

Prof. Youn-Long Steve Lin
National Tsing Hua University
Dept. Computer Science
101 Kuang Fu Road
HsinChu 300
Section 2
Taiwan R.O.C.
Chao-Yang Kao
101 Kuang Fu Road
HsinChu 300
Section 2
Taiwan R.O.C.
Huang-Chih Kuo
101 Kuang Fu Road
HsinChu 300
Section 2
Taiwan R.O.C.
Jian-Wen Chen
101 Kuang Fu Road
HsinChu 300
Section 2
Taiwan R.O.C.
ISBN 978-1-4419-0958-9 e-ISBN 978-1-4419-0959-6
DOI 10.1007/978-1-4419-0959-6
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2009943294
c
Springer Science+Business Media, LLC 2010
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York,
NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in
connection with any form of information storage and retrieval, electronic adaptation, computer software,
or by similar or dissimilar methodology now known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are
not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject
to proprietary rights.
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)

Preface
A video signal is represented as a sequence of frames of pixels. There exists vast
amount of redundant information that can be eliminated with video compression
technology so that its transmission and storage becomes more efficient. To facilitate
interoperability between compression at the video producing source and decompres-
sion at the consumption end, several generations of video coding standards have
been defined and adapted.
After MPEG-1 for VCD and MPEG-2 for DVD applications, H.264/AVC is
the latest and most advanced video coding standard defined by the international
standard organizations. Its high compression ratio comes at the expense of more
computational-intensive coding algorithms. For low-end applications, software so-
lutions are adequate. For high-end applications, dedicated hardware solutions are
needed.
This book describes an academic project of developing an application-specific
VLSI architecture for H.264/AVC video encoding. Each subfunction is analyzed
before a suitable parallel-processing architecture is designed. Integration of sub-
functional modules as well as the integration into a bus-based SOC platform is
presented. The whole encoder has been prototyped using an FPGA.
Intended readers are researchers, educators, and developers in video coding sys-
tems, hardware accelerators for image/video processing, and high-level synthesis
of VLSI. Especially, those who are interested in state-of-the-art parallel architecture
and implementation of intra prediction, integer motion estimation, fractional motion
estimation, discrete cosine transform, context-adaptive binary arithmetic coding,
and deblocking filter will find design ideas from this book.
HsinChu, Taiwan, ROC Youn-Long Lin
Chao-Yang Kao
Huang-Chih Kuo
Jian-Wen Chen
v

Acknowledgments
Cheng-Long Wu, Cheng-Ru Chang, Chun-Hsin Lee, Chun-Lin Chiu, Hao-Ting
Huang, Huan-Chun Tseng, Huan-Kai Peng, Hui-Ting Yang, Jhong-Wei Gu,
Kai-Hsiang Chang, Li-Cian Wu, Ping Chao, Po-Sheng Liu, Sheng-Tsung Hsu,
Sheng-Yu Shih, Shin-Chih Lee, Tzu-Jen Lo, Wei-Cheng Huang, Yu-Chien Kao,
Yuan-Chun Lin, and Yung-Hung Chan of the Theda.Design Group, National Tsing
Hua University contribute to the development of the H.264 Video Encoder System
described in this book.
The authors appreciate financial support from Taiwan’s National Science Council
under Contracts no. 95-2220-E-007-024, 96-2220-E-007-013, and 97-2220-E-007-
003 and Ministry of Economics Affairs under Contracts no. 94-EC-17-A-01-S1-
038, 95-EC-17-A-01-S1-038, and 96-EC-17-A-01-S1-038. Financial support from
Taiwan Semiconductor Manufacturing Company Limited (TSMC) and Industry
Technology Research Institute (ITRI) is also greatly appreciated.
Global Unichip Corp. provided us with its UMVP multimedia SOC platform and
consultation during the FPGA prototyping stage of the development. The authors are
grateful to Chi Mei Optoelectronics for a 52-in. Quad Full HD display panel. Joint
research with the Microprocessor Research Center (MPRC) of Peking University
has been an important milestone of this project.
vii

Contents
1 Introduction to Video Coding and H.264/AVC ............................. 1
1.1 Introduction ............................................................... 1
1.1.1 Basic Coding Unit ............................................... 2
1.1.2 Video Encoding Flow ........................................... 2
1.1.3 Color Space Conversion......................................... 2
1.1.4 Prediction of a Macroblock ..................................... 3
1.1.5 Intraframe Prediction............................................ 4
1.1.6 Interframe Prediction............................................ 4
1.1.7 Motion Vector ................................................... 4
1.1.8 Prediction Error.................................................. 4
1.1.9 Space-Domain to Frequency-Domain
Transformation of Residual Error .............................. 5
1.1.10 Coefficient Quantization ........................................ 5
1.1.11 Reconstruction................................................... 5
1.1.12 Motion Compensation........................................... 5
1.1.13 Deblocking Filtering ............................................ 6
1.2 Book Organization ........................................................ 6
2 Intra Prediction ................................................................ 11
2.1 Introduction ............................................................... 11
2.1.1 Algorithm ........................................................ 12
2.1.2 Design Consideration ........................................... 16
2.2 Related Works ............................................................. 19
2.2.1 Prediction Time Reduction Approaches........................ 19
2.2.2 Hardware Area Reduction Approaches ........................ 19
2.3 A VLSI Design for Intra Prediction ...................................... 20
2.3.1 Subtasks Scheduling ............................................ 20
2.3.2 Architecture...................................................... 24
2.3.3 Evaluation ....................................................... 30
2.4 Summary .................................................................. 30
ix

x Contents
3 Integer Motion Estimation .................................................... 31
3.1 Introduction ............................................................... 31
3.1.1 Algorithms ....................................................... 33
3.1.2 Design Considerations .......................................... 36
3.2 Related Works ............................................................. 37
3.2.1 Architecture...................................................... 37
3.2.2 Data-Reuse Schemes ............................................ 43
3.3 A VLSI Design for Integer Motion Estimation .......................... 44
3.3.1 Proposed Data-Reuse Scheme .................................. 45
3.3.2 Architecture...................................................... 47
3.3.3 Data Flow ........................................................ 49
3.3.4 Evaluation ....................................................... 52
3.4 Summary .................................................................. 53
4 Fractional Motion Estimation ................................................ 57
4.1 Introduction ............................................................... 57
4.1.1 Algorithms ....................................................... 58
4.2 Related Works ............................................................. 61
4.3 A VLSI Design for Fractional Motion Estimation ...................... 63
4.3.1 Proposed Architecture........................................... 63
4.3.2 Proposed Resource Sharing Method
for SATD Generator ............................................. 68
4.3.3 Evaluation ....................................................... 72
4.4 Summary .................................................................. 72
5 Motion Compensation ......................................................... 73
5.1 Introduction ............................................................... 73
5.1.1 Algorithms ....................................................... 73
5.2 Related Works ............................................................. 75
5.2.1 Memory Traffic Reduction...................................... 76
5.2.2 Interpolation Engine............................................. 76
5.3 A VLSI Design for Motion Compensation .............................. 77
5.3.1 Motion Vector Generator........................................ 77
5.3.2 Interpolator ...................................................... 79
5.3.3 Evaluation ....................................................... 83
5.4 Summary .................................................................. 83
6 Transform Coding ............................................................. 85
6.1 Introduction ............................................................... 85
6.1.1 Algorithms ....................................................... 85
6.1.2 Design Consideration ........................................... 97
6.2 Related Works ............................................................. 97
6.2.1 Multitransform Engine Approaches ............................ 97
6.2.2 Trans/Quan or InvQuan/InvTrans Integration Approaches .... 97

Contents xi
6.3 A VLSI Design for Transform Coding................................... 98
6.3.1 Subtasks Scheduling ............................................ 98
6.3.2 Architecture...................................................... 98
6.3.3 Evaluation .......................................................106
6.4 Summary ..................................................................106
7 Deblocking Filter...............................................................107
7.1 Introduction ...............................................................107
7.1.1 Deblocking Filter Algorithm....................................108
7.1.2 Subtasks Processing Order......................................112
7.1.3 Design Considerations ..........................................113
7.2 Related Works .............................................................115
7.3 A VLSI Design for Deblocking Filter....................................116
7.3.1 Subtasks Scheduling ............................................116
7.3.2 Architecture......................................................116
7.3.3 Evaluation .......................................................122
7.4 Summary ..................................................................124
8 CABAC Encoder ...............................................................125
8.1 Introduction ...............................................................125
8.1.1 CABAC Encoder Algorithm ....................................125
8.1.2 Subtasks Processing Order .....................................134
8.1.3 Design Consideration ...........................................134
8.2 Related Works .............................................................136
8.3 A VLSI Design for CABAC Encoder ....................................139
8.3.2 Architecture......................................................140
8.3.3 Evaluation .......................................................147
8.4 Summary ..................................................................148
9 System Integration .............................................................151
9.1 Introduction ...............................................................151
9.1.1 Algorithm ........................................................151
9.1.2 Design Consideration ...........................................153
9.2 Related Works .............................................................155
9.3 A VLSI Design for H.264/AVC Encoder ................................156
9.3.2 Architecture......................................................159
9.3.3 Evaluation .......................................................165
9.4 Summary ..................................................................166
References...........................................................................167
Index.................................................................................173

Chapter 1
Introduction to Video Coding and H.264/AVC
Abstract A video signal is represented as a sequence of frames of pixels. There
exists a vast amount of redundant information that can be eliminated with video
compression technology so that transmission and storage becomes more efficient.
To facilitate interoperability between compression at the video producing source
and decompression at the consumption end, several generations of video coding
standards have been defined and adapted. For low-end applications, software so-
lutions are adequate. For high-end applications, dedicated hardware solutions are
needed. This chapter gives an overview of the principles behind video coding in
general and the advanced features of H.264/AVC standard in particular. It serves as
an introduction to the remaining chapters; each covers an important coding tool and
its VLSI architectural design of an H.264/AVC encoder.
1.1 Introduction
A video encoder takes as its input a video sequence, performs compression, and
then produces as its output a bit-stream data which can be decoded back to a video
sequence by a standard-compliant video decoder.
A video signal is a sequence of frames. It has a frame rate defined as the number
of frames per second (fps). For typical consumer applications, 30 fps is adequate.
However, it could be as high as 60 or 72 for very high-end applications or as low as
10 or 15 for video conferencing over a low-bandwidth communication link.
A frame consists of a two-dimensional array of color pixels. Its size is called
frame resolution. A standard definition (SD) frame has 720 480 pixels per frame
whereas a full high definition (FullHD) one has 1,920 1,088. There are large num-
ber of frame size variations developed by various applications such as computer
monitors.
A color pixel is composed of three elementary components: R, G, and B. Each
component is digitized to an 8-bit data for consumer applications or a 12-bit one for
high-end applications.
Y.-L.S. Lin et al., VLSI Design for Video Coding: H.264/AVC Encoding from Standard
Specification to Chip, DOI 10.1007/978-1-4419-0959-6 1,
c
Springer Science+Business Media, LLC 2010
1

2 1 Introduction to Video Coding and H.264/AVC
The data rate for a raw video signal is huge. For example, a 30-fps FullHD one
will have a data rate of 30 1;920 1;088 3 8 D 1:5Gbps, which is impractical
for today’s communication or storage infrastructure.
Fortunately, by taking advantage of the characteristics of human visual system
and the redundancy in the video signal, we can compress the data by two orders of
magnitude without scarifying the quality of the decompressed video.
1.1.1 Basic Coding Unit
In order for a video encoding or decoding system to handle video of different frame
rates and simplify the implementation, a basic size of 16 16 has been popularly
adopted. Every main stream coding standards from MPEG-1, MPEG-2, : : : to H.264
has chosen a macroblock of 16 16 pixels as their basic unit of processing. Hence,
for video of different resolutions, we just have to process different number of mac-
roblocks. For every 720 480 SD frame, we process 45 30 macroblocks while for
every FullHD frame, we process 120 68 macroblocks.
1.1.2 Video Encoding Flow
Algorithm 1.1 depicts a typical flow of video encoding. frame(t) is the current frame
to be encoded. frame0
(t1) is the reconstructed frame for referencing or called ref-
erence frame. frame0
(t) is the reconstructed current frame. We encode F.t/ one
macroblock (MB) at a time starting from the leftmost MB of the topmost row.
We called the MB being encoded as Curr MB. It can be encoded in one of the
three modes: I for intra prediction, P or unidirectional interprediction, and B for
bidirectional interprediction. The resultant MB from prediction is called Pred MB
and the difference between Curr MB and Pred MB is called Res MB for residu-
als. Res MB goes through space-to-frequency transformation and then quantization
processes to become Res Coef or residual coefficients. Entropy coding then com-
presses Res Coef to get final bit-stream. In order to prepare reconstructed current
frame for future reference, we perform inverse quantization and inverse transform
on Res Coef to get reconstructed residuals called Reconst res. Adding together Re-
const res and Pred MB, we have Reconstruct MB for insertion into frame0
(t).
1.1.3 Color Space Conversion
Naturally, each pixel is composed of R, G, and B 8-bit components. Applying the
following conversion operation, it can be represented as one luminance (luma) com-
ponent Y and two chrominance (chroma) components Cr and Cb. Since the human

1.1 Introduction 3
Algorithm 1.1: Encode a frame.
encode a frame (frame(t), mode)
for I D 1, N do //** N: #rows of MBs per frame
for I D 1, M do //** N: #rows of MBs per frame
Curr MB D MB(frame(t), I, J);
case (mode)
I: Pred MB D Intra Pred (frame(t)’, I, J);
P: Pred MB D ME (frame(t-1)’, I, J);
B: Pred MB D ME (frame(t-1)’, frame(tC1)’, I, J);
endcase
Res MB D Curr MB - Pred MB;
Res Coef D Quant(Transform(Res MB));
Output(Entropy code(Res Coef));
Reconst res D InverseTransform(InverseQuant(Res Coef));
Reconst MB D Reconst res C Pred MB;
Insert(Reconst MB, frame(t)’);
endfor
endfor
end encode a frame;
visual system is more sensitive to luminance component than chrominance ones, we
can subsample Cr and Cb to reduce the data amount without sacrificing the video
quality. Usually one out of two or one out of four subsampling is applied. The for-
mer is called 4:2:2 format and the later 4:2:0 format. In this book, we assume that
4:2:0 format is chosen. Of course, the inverse conversion will give us R, G, B com-
ponents from a set of Y , Cr, Cb components.
Y D 0:299R C 0:587G C 0:114B;
Cb D 0:564.B Y /;
Cr D 0:713.R Y /:
(1.1)
1.1.4 Prediction of a Macroblock
A macroblock M has 1616 D 256 pixels. It takes 2563 D 768 bytes to represent
it in RGB format and 256.1C1=4C1=4/ D 384 bytes in 4:2:0 format. If we can
find during decoding a macroblock M0
which is similar to M, then we only have to
get from the encoding end the difference between M and M0
. If M and M0
are very
similar, the difference becomes very small so does the amount of data needed to
be transmitted/stored. Another way to interpret similarity is redundancy. There exist
two types of redundancy: spatial and temporal. Spatial redundancy results from sim-
ilarity between a pixel (region) and its surrounding pixels (regions) in a frame. Tem-
poral redundancy results from slow change of video contents from one frame to the
next. Redundancy information can be identified and removed with prediction tools.

1.1.5 Intraframe Prediction
In an image region with smooth change, a macroblock is likely to be similar to its
neighboring macroblocks in color or texture. For example, if all its neighbors are
red, we can predict that a macroblock is also red. Generally, we can define sev-
eral prediction functions; each takes pixel values from neighboring macroblocks
as its input and produces a predicted macroblock as its output. To carry out in-
traframe prediction, every function is evaluated and the one resulting in the smallest
error is chosen. Only the function type and the error need to be encoded and
stored/transmitted. This tool is also called intra prediction and a prediction func-
tion is also called a prediction mode.
1.1.6 Interframe Prediction
Interframe prediction, also called interprediction, identifies temporal redundancy
between neighboring frames. We call the frame currently being processed the cur-
rent frame and the neighboring one the reference frame. We try to find from
the reference frame a reference macroblock that is very similar to the current
macroblock of the current frame. The process is called motion estimation. A mo-
tion estimator compares the current macroblock with candidate macroblocks within
a search window in the reference frame. After finding the best-matched candi-
date macroblock, only the displacement and the error need to be encoded and
stored/transmitted. The displacement from the location of the current macroblock
to that of the best candidate block is called motion vector (MV). In other words,
motion estimation determines the MV that results in the smallest interprediction
error. A bigger search window will give better prediction at the expense of longer
estimation time.
1.1.7 Motion Vector
A MV obtained from motion estimation is adequate for retrieving a block from the
reference frame. Yet, we do not have to encode/transmit the whole of it because there
exists similarity (or redundancy) among MVs of neighboring blocks. Instead, we can
have a motion vector prediction (MVP) as a function of neighboring blocks’ MVs
and just process the difference, called motion vector difference (MVD), between the
MV and its MVP. In most cases, the MVD is much smaller than its associated MV.
1.1.8 Prediction Error
We call the difference between the current macroblock and the predicted one as
prediction error. It is also called residual error or just residual.

1.1 Introduction 5
1.1.9 Space-Domain to Frequency-Domain Transformation
of Residual Error
Residual error is in the space domain and can be represented in the frequency
domain by applying discrete cosine transformation (DCT). DCT can be viewed
as representing an image block with a weighted sum of elementary patterns. The
weights are termed as coefficients. For computational feasibility, a macroblock of
residual errors is usually divided into smaller 4 4 or 8 8 blocks before applying
DCT one by one.
1.1.10 Coefficient Quantization
Coefficients generated by DCT carry image components of various frequencies.
Since human visual system is more sensitive to low frequency components and
less sensitive to high frequency ones, we can treat them with different resolution
by means of quantization. Quantization effectively discards certain least significant
bits (LSBs) of a coefficient. By giving smaller quantization steps to low frequency
components and larger quantization steps to high frequency ones, we can reduce the
amount of data without scarifying the visual quality.
1.1.11 Reconstruction
Both encoding and decoding ends have to reconstruct video frame. In the encoding
end, the reconstructed frame instead of the original one should be used as refer-
ence because no original frame is available in the decoding end. To reconstruct, we
perform inverse quantization and inverse DCT to obtain reconstructed residual. Note
that the reconstructed residual is not identical to the original residual as quantization
is irreversible. Therefore, distortion is introduced here. We then add prediction data
to the reconstructed residual to obtain reconstructed image. For an intrapredicted
macroblock, we perform predict function on its neighboring reconstructed mac-
roblocks while for an interpredicted one we perform motion compensation. Both
methods give a reconstructed version of the current macroblock.
1.1.12 Motion Compensation
Given a MV, the motion compensator retrieves from the reference frame a re-
constructed macroblock pointed to by the integer part of the MV. If the MV has
fractional part, it performs interpolation over the retrieved image to obtain the final
reconstructed image. Usually, interpolation is done twice, one for half-pixel accu-
racy and the other for quarter-pixel accuracy.

1.1.13 Deblocking Filtering
After every macroblock of a frame is reconstructed one by one, we obtain a
reconstructed frame. Since the encoding/decoding process is done macroblock-wise,
there exists blocking artifacts between boundaries of adjacent macroblocks or sub-
blocks. Deblocking filter is used to eliminate this kind of artificial edges.
1.2 Book Organization
This book describe a VLSI implementation of a hardware H.264/AVC encoder as
depicted in Fig. 1.1.
Inter Info
Memory
IME
Engine
TransCoding
Engine
FME
Engine
MC
Engine
IntraPred
Engine
IntraMD
Engine
Multiplexer
Recons
Engine
DF
Engine
Unfilter
Memory
ReconsMB
Memory
CABAC
Engine
PE
Engine
DF
MAU
Encoder Core
MB
MAU
SR
MAU
BIT
MAU
MAU Arbiter
Command
Receiver
AMBA
Slave
AMBA
Master
AMBA
MainCtrl
Engine
AMBA Interface
Fig. 1.1 Top-level block diagram of the proposed design

Exploring the Variety of Random
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55° to 56° C., and act only in saline solutions (Ehrlich and
Morgenroth, Berlin. Klin. Woch., pp. 6 and 481). The cytases or
alexins, which will be studied in another volume of this collection,
and which will discuss the active principles of the immunizing
serums, constitute one of the numerous soluble intraleucocytary
ferments, and they pass into the serous liquids of the organism
only as the result of a rupture of or injury to the phagocytes.
Transcriber's Notes
Obvious typographical errors have been silently corrected, but all other variations in
spelling, punctuation and accents are as in the original, with the exception of
Symptomatology (in the contents list) and symptomology (in the text) which has been
corrected to symptomatology.
Variations between the treatment and phrasing of headings in the table of contents and
in the text have not been changed.

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