VLSI ieee projects 2017-2018 | VLSI ieee projects Titles 2017-2018
- 1. VLSI IEEE Projects Titles – 2017-2018 LeMeniz Infotech 36, 100 feet Road, Natesan Nagar(Near Indira Gandhi Statue and Next to Fish-O-Fish), Pondicherry-605 005 Web : www.ieeemaster.com / www.lemenizinfotech.com Mail : info@lemenizinfotech.com / projects@lemenizinfotech.com Phone : 9566355386 / 9962588976 S.No Title Year LOW POWER 1 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging 2017 2 Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication 2017 3 Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture 2017 4 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding 2017 5 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption 2017 6 Resource-Efficient SRAM-based Ternary Content Addressable Memory 2017
- 2. 7 Write-Amount-Aware Management Policies for STT-RAM Caches 2017 8 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA 2017 9 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder 2017 10 High-Speed Parallel LFSR Architectures Based on Improved State- Space Transformations 2017 11 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 2017 12 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map 2017 HIGH SPEED DATA TRANSMISSION 1 Efficient Designs of Multi-ported Memory on FPGA 2017 2 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA 2017 3 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock 2017 4 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique 2017 5 Hardware-Efficient Built-In Redundancy Analysis for Memory With 2017
- 3. Various Spares 6 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm 2017 7 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission 2017 8 Scalable Device Array for Statistical Characterization of BTI-Related Parameters 2017 AREA EFFICIENT/ TIMING & DELAY REDUCTION 1 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding 2017 2 A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits 2017 3 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware 2017 4 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs 2017 5 Efficient Soft Cancelation Decoder Architectures for Polar Codes 2017 6 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition 2017 7 Hybrid LUT Multiplexer FPGA Logic Architectures 2017
- 4. 8 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication 2017 9 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers 2017 10 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields 2017 11 Antiwear Leveling Design for SSDs With Hybrid ECC Capability 2017 12 Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems 2017 Audio, Image and Video Processing 1 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding 2017 2 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High- Speed yet Energy-Efficient Digital Signal Processing 2017 3 Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations 2017 4 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers 2017 5 An FPGA-Based Hardware Accelerator for Traffic Sign Detection 2017
- 5. 6 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations 2017 7 Time-Encoded Values for Highly Efficient Stochastic Circuits 2017 8 Design of Power and Area Efficient Approximate Multipliers 2017 VERIFICATION 1 COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits 2017 2 Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction 2017 NETWORKING 1 Multicast-Aware High-Performance Wireless Network-on-Chip Architectures 2017 VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um) 1 Temporarily Fine-Grained Sleep Technique for Near- and Sub- threshold Parallel Architectures 2017 2 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique 2017 3 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator 2017
- 6. 4 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage 2017 5 Delay Analysis for Current Mode Threshold Logic Gate Designs 2017 6 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications 2017 7 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating 2017 8 A High-Speed and Power-Efficient Voltage Level Shifter for Dual- Supply Applications 2017 9 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS 2017 10 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application 2017 11 An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz 2017 12 A 65-nm CMOS Constant Current Source with Reduced PVT Variation 2017 13 A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy 2017 14 Temporarily Fine-Grained Sleep Technique for Near- and Sub- threshold Parallel Architectures 2017 15 A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression 2017
- 7. 16 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template 2017 17 On Micro-architectural Mechanisms for Cache Wear out Reduction 2017 18 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology 2017 19 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing 2017 20 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures 2017