2. Design rules and Layout
• Why we use design rules?
– Interface between designer and process
engineer
3. Historically, the process
technology referred to the
length of the silicon channel
between the source and
drain terminals in field effect
transistors (see FET). The
sizes of other features are
generally derived as a ratio
of the channel length, where
some may be larger than the
channel size and some
smaller. For example, in a
90 nm process, the length of
the channel may be 90 nm,
but the width of the gate
terminal may be only 50 nm.
4. Design Rules
• Two major approaches:
– “Micron” rules: stated at micron
resolution.
– rules: simplified micron rules with
limited scaling attributes.
• Design rules represents a tolerance which
insures very high probability of correct
fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
5. “Micron” rules
• All minimum sizes and spacing specified in
microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ
based rules
• Standard in industry.
6. Lambda-based Design Rules
• Lambda-based (scalable CMOS) design
rules define scalable rules based on
(which is half of the minimum channel
length)
• Stick diagram is a draft of real layout, it
serves as an abstract view between the
schematic and layout.
7. • Circuit designer in general want tighter, smaller
layouts for improved performance and decreased
silicon area.
• On the other hand, the process engineer wants
design rules that result in a controllable and
reproducible process.
• Generally we find there has to be a compromise for
a competitive circuit to be produced at a reasonable
cost.
8. • All widths, spacing, and distances are written in
the form
• = 0.5 X minimum drawn transistor length
m
9. Design Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more
uneven surface than other conducting layers to ensure their
continuity
Metal
Diffusion
Polysilicon
10. Design Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current
Metal
Diffusion
Polysilicon
11. Design Rules
Diffusion – PolySi To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal
lines can overlap or cross
Metal
Diffusion
Polysilicon
12. Metal Vs PolySi/Diffusion
• Metal lines can pass over both
diffusion and polySi without electrical
effect
• It is recommended practice to leave
between a metal edge and a polySi or
diffusion line to which it is not
electrically connected
Metal
Polysilicon
14. Butting Contact
The gate and source of a depletion device can be connected by a
method known as butting contact. Here metal makes contact to
both the diffusion forming the source of the depletion transistor
and to the polySi forming this device’s gate.
Advantage:
No buried contact mask required and avoids associated
processing.
16. Buried Contact
Here gate length is depend upon the alignment of the
buried contact mask relative to the polySi and therefore
vary by .
2
2
Channel length
Channel length
PolySi
Buried contact
Buried contact
Diffusion
17. Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 22
Metal and polySi or diffusion must overlap this contact area
by so that the two desired conductors encompass the
contact area despite any mis-alignment between conducting
layers and the contact hole
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