VLSI PPT _0.pdf

VLSI Design Lecture PPTs
INSTITUTE OF AERONAUTICAL ENGINEERING
Dundigal, Hyderabad -500 043
1
6/3/2015
Department : ELECTRONICS AND COMMUNICATION ENGINEERING
Course Code : 57035
Course Title : VLSI DESIGN
Course Coordinator : VR. Sheshagiri Rao, Professor
Team of Instructors B. Kiran Kumar, Assistant Professor
Course Structure :
Lectures Tutorials Practicals Credits
4 1 - 4

Unit I
Introduction to IC technology
Topics
• MOS, PMOS, NMOS, CMOS and BiCMOS
Technologies:
• Oxidation
• Lithography
• Diffusion
• Ion implantation
• Metallization
• Encapsulation
• Probe testing
• Integrated Resistors and Capacitors
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Acronym of VLSI
• V -> Very
• L -> Large
• S -> Scale
• I -> Integration
3
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Types of Field Effect Transistors
(The Classification)
» JFET
MOSFET (IGFET)
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n-Channel JFET
p-Channel JFET
n-Channel
EMOSFET
p-Channel
EMOSFET
Enhancement
MOSFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
FET
MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)
Primary component in high-density VLSI chips such as memories and microprocessors
JFET (Junction Field-Effect Transistor)
Finds application especially in analog and RF circuit design

Metal Oxide Semiconductor(MOS)
• Advantages of FET over conventional Transistors
• Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
• Voltage controlled Device (gate voltage controls drain current)
• Very high input impedance (109-1012 )
• Source and drain are interchangeable in most Low-frequency applications
• Low Voltage Low Current Operation is possible (Low-power consumption)
• Less Noisy as Compared to BJT
• No minority carrier storage (Turn off is faster)
• Very small in size, occupies very small space in ICs
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Switch Model of NMOS Transistor
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Gate
Source
(of carriers)
Drain
(of carriers)
| VGS |
| VGS | < | VT | | VGS | > | VT |
Open (off) (Gate = Closed (on) (Gate = )
Ron

Switch Model of PMOS Transistor
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Gate
Source
(of carriers)
Drain
(of carriers)
| VGS |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate = ) Closed (on) (Gate = )
Ron

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MOS transistors Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS Enhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
Channel

MOSFET Circuit Symbols
• (g) and (i) are the most
commonly used symbols
in VLSI logic design.
• MOS devices are
symmetric.
• In NMOS, n+ region at
higher voltage is the
drain.
• In PMOS p+ region at
lower voltage is the drain
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The NMOS Transistor Cross Section
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n areas have been doped with donor ions
(arsenic) of concentration ND - electrons are
the majority carriers
p areas have been doped with acceptor ions
(boron) of concentration NA - holes are the
majority carriers
Gate oxide
n+
Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide
(SiO2)
n+
Polysilicon
Gate
L
W

Carriers and Current
• Carriers always flow from the Source to Drain
• NMOS: Free electrons move from Source to
Drain.
– Current direction is from Drain to Source.
• PMOS: Free holes move from Source to Drain.
– Current direction is from Source to Drain.
–
6/3/2015 12

The MOSFET Channel
• Under certain conditions, a thin channel can
be formed right underneath the Silicon-
Dioxide insulating layer, electrically connecting
the Drain to the Source. The depth of the
channel (and hence its resistance) can be
o t olled the Gate s oltage. The le gth of
the channel (shown in the figures above as L)
a d the ha el s idth W, a e i po ta t
design parameters.
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REGION OF OPERATION
CASE-1 (No Gate Voltage)
• Two diodes back to back exist in series.
• One diode is formed by the pn junction
between the n+ drain region and the p-type
substrate
• Second is formed by the pn junction between
the n+ source region and the p-type substrate
• These diodes prevent any flow of the current.
• There exist a very high resistance.
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REGION OF OPERATION
Creating a channel
• Apply some positive voltage on the gate
terminal.
• This positive voltage pushes the holes
downward in the substrate region.
• This causes the electrons to accumulate under
the gate terminal.
• At the same time the positive voltage on the
gate also attracts the electrons from the n+
region to accumulate under the gate terminal.
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REGION OF OPERATION
Creating a channel
• When sufficient electrons are accumulated under the
gate an n-region is created, connecting the drain and
the source
• This causes the current to flow from the drain to
source
• The channel is formed by inverting the substrate
surface from p to n, thus induced channel is also called
as the inversion layer.
• The voltage between gate and source called vgs at
which there are sufficient electron under the gate to
form a conducting channel is called threshold voltage
Vth.
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Formation of Channel
• First, the holes are
repelled by the
positive gate voltage,
leaving behind
negative ions and
forming a depletion
region. Next,
electrons are attracted
to the interface,
creating a channel
i e sio la e .
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MOS Transistor Current direction
• The source terminal of an n-channel(p-channel)
transistor is defined as whichever of the two terminals
has a lower(higher) voltage.
• When a transistor is turned ON, current flows from the
drain to source in an n-channel device and from source
to drain in a p-channel transistor.
• In both cases, the actual carriers travel from the source
to drain.
• The current directions are different because n-channel
carriers are negative, whereas p-channel carriers are
positive.
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MOS I/V
6/3/2015 25
For a NMOS, a necessary
condition for the channel to exist is:
TH
GS V
V 

REGION OF OPERATION
Applying small Vds
• Now we applying some small voltage between
source and drain
• The voltage Vds causes a current to flow from
drain to gate.
• Now as we increase the gate voltage, more
current will flow.
• Increasing the gate voltage above the threshold
voltage enhances the channel, hence this mode is
called as enhancement mode operation.
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Operation – nMOS Transistor
• Accumulation Mode - If Vgs < 0, then an
electric field is established across the
substrate.
• Depletion Mode -If 0<Vgs< Vtn, the region
under gate will be depleted of charges.
• Inversion Mode – If Vgs > Vtn, the region
below the gate will be inverted.
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V =0
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Voltage-Dependent Resistor
• The inversion channel
of a MOSFET can be
seen as a resistor.
• Since the charge
density inside the
channel depends on
the gate voltage, this
resistance is also
voltage-dependent.

6/3/2015 35
Channel Potential Variation
• “i e the e s a
channel resistance
between drain and
source, and if drain is
biased higher than
the source, then the
potential between
gate and channel will
decrease from
source to drain.

6/3/2015 36
Channel Pinch-Off
• As the potential
difference between drain
and gate becomes more
positive, the inversion
layer beneath the
interface starts to pinch
off around drain.
• When VD s> VGs - Vth,
the channel at drain
totally pinches off, and
when VD s< VGs - Vth,
the channel length starts
to decrease.

Transistor in Saturation Mode
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S
D
B
G
VGS VDS > VGS - VT
ID
VGS - VT
- +
n+ n+
Pinch-off
Assuming VGS > VT
VDS
The current remains constant (saturates).

Du i g pi hoff
6/3/2015 41
 Does this mean that the current i =0 ? Actually, it does not. A MOSFET
that is pinched off at the drain end of the channel still conducts current:
 The large E in the depletion region surrounding the drain will sweep
electrons across the end of the pinched off channel to the drain.
 This is very similar to the operation of the BJT. For an npn BJT, the electric
field of the reversed biased CBJ swept electrons from the base to the
collector regions.

N-Channel MOSFET characteristics
6/3/2015 42

Enhancement-Mode PMOS
Transistors: Structure
• p-type source and drain
regions in n-type substrate.
• vGS < 0 required to create p-
type inversion layer in channel
region
• For current flow, vGS < vTP
• To maintain reverse bias on
source-substrate and drain-
substrate junctions, vSB < 0
and vDB < 0
• Positive bulk-source potential
causes VTP to become more
negative
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P-channel MOSFET characteristics
linear
saturation
p transistor

6/3/2015 47
Depletion-Mode MOSFETS
• NMOS transistors with
• Ion implantation process
is used to form a built-in
n-type channel in the
device to connect source
and drain by a resistive
channel
• Non-zero drain current
for vGS = 0; negative vGS
required to turn device
off.
฀
VTN
0

6/3/2015 50
pMOS are 2.5 time slower than
nMOS due to electron and hole
mobilities

6/3/2015 51
Basic processes involved in fabricating
Monolithic ICs
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Metallization
8. Testing
9. Assembly processing & packaging

6/3/2015 52
Oxidation
1. SiO2 is an extremely hard protective coating & is unaffected
by almost all reagents except by hydrochloric acid. Thus it
stands against any contamination.
2. By selective etching of SiO2, diffusion of impurities through
carefully defined through windows in the SiO2 can be
accomplished to fabricate various components.
Formation of silicon dioxide layer on the surface of Si wafer
1. protects surface from contaminants
2. forms insulating layer between conductors
3. form barrier to dopants during diffusion or ion implantation
4. grows above and into silicon surface
Dry oxidation: lower rate and higher quality
Wet oxidation: higher rate and lower quality

6/3/2015 53
Oxidation
The silicon wafers are stacked up in a quartz boat & then
inserted into quartz furnace tube. The Si wafers are raised
to a high temperature in the range of 950 to 1150oC & at
the same time, exposed to a gas containing O2 or H2O or
both. The chemical action is
Si + 2H2O-----------> Si O2+ 2H2 (Wet )
Si + O2 -------------> SiO2 (Dry )

54
Photolithography
• Coat wafer with photoresist
(PR)
• Shine UV light through mask
to selectively expose PR
• Use acid to dissolve exposed
PR
• Now use exposed areas for
– Selective doping
– Selective removal of material
under exposed PR
Wafer
Photoresist
Mask
UV Light
6/3/2015

55
Adding Materials
• Add materials on top of
silicon
– Polysilicon
– Metal
– Oxide (SiO2) - Insulator
• Methods
– Chemical deposition
– Sputtering (Metal ions)
– Oxidation
Silicon
Added Material
(e.g. Polysilicon)
6/3/2015

56
Oxide (Si02) - The Key Insulator
• Thin Oxide
– Add using chemical deposition
– Used to form gate insulator & block active areas
• Field Oxide (FOX) - formed by oxidation
– Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
– Used to insulate non-active areas
Silicon Wafer Silicon Wafer
SiN / SiO2
FOX FOX
SiO2 Thin Oxide
6/3/2015

57
Patterning Materials using
Photolithography
• Add material to wafer
• Coat with photoresist
• Selectively remove
photoresist
• Remove exposed material
• Remove remaining PR
Silicon
Added Material
(e.g. Polysilicon)
6/3/2015

58
Diffusion
• Introduce dopant via epitaxy or
ion implant e.g. Arsenic (N),
Boron (P)
• Allow dopants to diffuse at high
temperature
• Block diffusion in selective areas
using oxide or PR
• Diffusion spreads both vertically,
horizontally Silicon
Diffusion
Blocking Material
(Oxide)
6/3/2015

Ion Implantation
180 kV
Resolving
Aperture
Ion Source
Equipment Ground
Acceleration Tube
90° Analyzing Magnet
Terminal Ground
20 kV
Focus Neutral beam
and
beam path
gated
Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Y - axis
scanner
Neutral beam trap
and beam gate
Gases
Ar
AsH3
B11F3 *
He
N2
PH3
SiH4
SiF4
Solids
Ga
In
Sb
Liquids
Al(CH3)3
Process Conditions
Flow Rate: 5 sccm
Pressure: 10-5 Torr
Accelerating Voltage: 5
to 200 keV
6/3/2015

Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal
6/3/2015

nMOS fabrication steps
1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the
required p-impurities are introduced as the crystal is grown.
2. A layer of silicon dioxide (Si02) is grown all over the surface of the wafer to protect the surface, act as a
barrier to dopants during processing, and provide a generally insulating substrate on to which other layers
may be deposited and patterned.
3. The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an
even distribution of the required thickness.
4. The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into
which diffusion is to take place together with transistor channels.
5. These areas are subsequently readily etched away together with the underlying silicon dioxide so that the
wafer surface is exposed in the window defined by the mask.
6. The remaining photoresist is removed and a thin layer of Si02 is grown over the entire chip surface and
then polysilicon is deposited on top of this to form the gate structure.
7. Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and
then the thin oxide is removed to expose areas into which
8. Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connections (i.e. contact cuts)
are to be made.
9. The whole chip then has metal (aluminium) deposited over its surface. This metal layer is then masked
and etched to form the required interconnection pattern.
6/3/2015 61

1.
2.
3.
………………………………………
………………………………………
………………………………………
………………………………………
Substrate
Thick oxide
(1m)
Photoresist
p
p
p
6/3/2015 62

4.
5. ………………………………………
………………………………………
………………………………………
………………………………………
Window in
oxide
Mask
UV light
p
p
6/3/2015 63

6.
7.
………………………………………
………………………………………
………………………………………
……………………………………… Patterned
Poly. (1-2 m)
On thin oxide
( 800-1000A0 )
………………………………………
………………………………………
……
……
……
……
…………
………… n+ diffusion
(1 m deep)
p
p
6/3/2015 64

8.
………………………………………
………………………………………
……
……
…….
……
…… …………
………… Contact holes
(cuts)
…………
…………
…………
…………
…………
…………
……
……
……
……
9.
………………………………………
………………………………………
……
……
…….
……
…… …………
…………
Patterned
Metallization
(aluminum
1 m)
…………
…………
…………
…………
…………
…………
……
……
……
……
p
p
6/3/2015 65

CMOS FABRICATION
• There are a number of approaches to CMOS
fabrication, including the p-well, the n-well,
the twin-tub, and the silicon-on-insulator
processes.
6/3/2015 66

The p-well Process
In primitive terms, the structure consists of an n-
type substrate in which p-devices may
be formed by suitable masking and diffusion
and, in order to accommodate n-type devices,
a deep p-well is diffused into the n-type
substrate as shown.
6/3/2015 67

The p-well CMOS fabrication
In all other respects-masking, patterning, and diffusion-the process is similar to
nMOS fabrication. In summary, typical processing steps are:
• Mask 1 - defines the areas in which the deep p-well diffusions are to take place.
• Mask 2 - defines the thinox regions, namely those areas where the thick oxide is
to be stripped and thin oxide grown to accommodate p- and n-transistors and wires.
• Mask 3 - used to pattern the polysilicon layer which is deposited after the thin
oxide.
• Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to define
all areas where p-diffusion is to take place.
• Mask 5 - This is usually performed using the negative form of the p-plus mask and
defines those areas where n-type diffusion is to take place.
• Mask 6 - Contact cuts are now defined.
• Mask 7 - The metal layer pattern is defined by this mask.
Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8 ts
needed to define the openings for access to bonding pads.
6/3/2015 68

……………………
………………… …
…
1. p-well
(4-5 m)
SiO2
……
……
…
… …
…
2. Thin oxide
and
polysilicon
Polysilicon
p
p
n
n
6/3/2015 69

……
……
…
… …
…
3.
p-diffusion
P+ mask
(positive)
……
……
…
… …
…
4.
n-diffusion
P+ mask
(negative)
p
n
p
n
6/3/2015 70

Vin
n
p
Vout
VSS
VDD
CMOS p-well inverter showing VDD and VSS substrate connections
Polysilicon
Oxide
n-diffusion
P-diffusion
6/3/2015 71

Vin
p
n
Vout
VSS
VDD
CMOS n-well inverter showing VDD and VSS substrate connections
Polysilicon
Oxide
n-diffusion
P-diffusion
6/3/2015 72

The n-well Process
• As indicated earlier, although the p-well process is widely used, n-well fabrication
has also gained wide acceptance, initially as a retrofit to nMOS lines.
6/3/2015 73

The twin-tub-Tub Process
A logical extension of the p-well and n-well approaches is
the twin-tub fabrication process.
Here we start with a substrate of high resistivity n-type
material and then create both .. n-well and p-well
regions. Through this process it is possible to preserve the
performance of n-transistors without compromising the
p-transistors. Doping control is more readily achieved
and some relaxation in manufacturing tolerances results.
This is particularly important as far
as latch-up is concerned.
6/3/2015 74

Vin
n
Vout
VSS
VDD
Twin-tub structure
( A logical extension of the p-well and n-well)
Polysilicon
Oxide
n-diffusion
P-diffusion
p
n substrate
well
well
Epitaxial
layer
6/3/2015 75

Bipolar compatible CMOS(Bi-CMOS) technology:
Introduced in early 1980s
Combines Bipolar and CMOS logic
Low power dissipation High speed
High packing density High output
drive
High Noise Margin High transconductance
(gm)
High input impedance
Bi-CMOS
6/3/2015 76

The objective of the Bi-CMOS is to combine bipolar and CMOS so as to
exploit the advantages of both the technologies.
Today Bi-CMOS has become one of the dominant technologies used for
high speed, low power and highly functional VLSI circuits.
The process step required for both CMOS and bipolar are almost similar
The primary approach to realize high performance Bi-CMOS devices is the
addition of bipolar process steps to a baseline CMOS process.
The Bi-CMOS gates could be used as an effective way of speeding up the
VLSI circuits.
The applications of Bi-CMOS are vast.
Advantages of bipolar and CMOS circuits can be retained in Bi-CMOS
chips.
Bi-CMOS technology enables high performance integrated circuits IC’s but
increases process complexity.
Features
6/3/2015 77

Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency
characteristics
Improved I/O speed (particularly significant with the growing importance
of package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current)
low packing density
low delay sensitivity to load
It is essentially unidirectional.
Characteristics of Bipolar Technology
6/3/2015 78

Lower static power dissipation
Higher noise margins
Higher packing density
High yield with large integrated complex functions
High input impedance (low drive current)
Scalable threshold voltage
High delay load sensitivity
Low output drive current (issue when driving large capacitive loads)
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device,
Low gain
Characteristics of CMOS
6/3/2015 79

CMOS process BI-POLAR
process
1 . N-well 1. n+ sub-collector
2. P base doping(extra
step)
3. PMOS source and drain 3. p+ base contact
4. NMOS source and drain 4. n+ emitter
Bi-CMOS FABRICATION PROCESS
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npn-BJT Fabrication
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BJT Processing
6/3/2015 82
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
8. Metal deposition and etching
6. p+ ohmic contact
7. Contact etching
9. Passivation and bond pad opening
p-substrate
n+ buried layer
p-base layer
n+ layer
n+ layer p+ layer

BJT Processing
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6. p+ ohmic contact
7. Contact etching
9. Passivation and bond pad opening p-substrate

BJT Processing
6/3/2015 84
6. p+ ohmic contact
7. Contact etching
n+ buried layer
n epi layer

BJT Processing
6/3/2015 85
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer

BJT Processing
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6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base layer

BJT Processing
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6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base layer
n+ layer
n+ layer

BJT Processing
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6. p+ ohmic contact
7. Contact etching
n+ buried layer
p
+
isolation
layer
p
+
isolation
layer
p-base layer
n+ layer
n+ layer p+ layer

BJT Processing
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6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer

BJT Processing
6/3/2015 90
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer

BJT Processing
6/3/2015 91
6. p+ ohmic contact
7. Contact etching
n+ buried layer
p+ isolation layer
p-base layer
n+ layer
n+ layer p+ layer

Lateral view of npn BJT
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Doping Profiles in a BJT
6/3/2015 94

NMOS PMOS
G D
S G D
S
NPN-BJT
C B E
N Plus Buried Layer
N-Well (Collector)
N-
Diff
N-
Diff
P-Diff P-Diff N-Plus
Emitter
P-SUBSTRATE
P-EPITAXY
BICMOS STRUCTURE
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P-SUBSTRATE
P-SUBSTRATE
P-SUBSTRATE IS TAKEN
P-TYPE SUBSTRATE IS COVERED WITH OXIDE LAYER
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N Plus Buried Layer
P-SUBSTRATE
P-SUBSTRATE
A WINDOW IS OPENED THROUGH OXIDE LAYER
THROUGH THE WINDOW N TYPE IMPURITIES IS HEAVILY DOPED
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N Plus Buried Layer
P-SUBSTRATE
P-EPITAXY
P-EPITAXY LAYER IS GROWN ON THE ENTIRE SURFACE
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N Plus Buried Layer
P-SUBSTRATE
P-EPITAXY
THE ENTIRE SURFACE IS COVERED WITH OXIDE LAYER AND TWO WINDOWS
ARE OPENED THROUGH THE OXIDE LAYER
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N Plus Buried Layer
N-Well (Collector)
N-Well
P-SUBSTRATE
P-EPITAXY
THROUGH THE TWO WINDOWS N-TYPE IMPURITIES ARE DIFFUSED TO
FORM N-WELLS
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N Plus Buried Layer
N-Well (Collector)
N-Well
P-SUBSTRATE
P-EPITAXY
THREE WINDOWS ARE OPENED THROUGH THE OXIDE LAYER , IN THESE
THREE WINDOWS THREE ACTIVE DEVICES NMOS,PMOS AND NPN BJT
ARE FORMED
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N Plus Buried Layer
N-Well (Collector)
N-Well
P-SUBSTRATE
P-EPITAXY
THE ENTIRE SURFACE IS COVERED WITH THINOX AND POLYSILICON
AND ARE PATTERNED TO FORM THE GATE TERMINALS OF THE NMOS
AND PMOS
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N Plus Buried Layer
N-Well (Collector)
N-Well P-Base
P-SUBSTRATE
P-EPITAXY
THROUGH THE 3RD WINDOW THE P-IMPURITIES ARE MODERATELY
DOPED TO FORM THE BASE TERMINAL OF BJT
N-WELL ACTS LIKE THE COLLECTOR TERMINAL
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N Plus Buried Layer
N-Well (Collector)
N-Well P-Base
P-SUBSTRATE
P-EPITAXY
N-
Diff
N-
Diff
N-Plus
Emitter
THE N-TYPE IMPURITES ARE HEAVILY DOPED TO FORM
1.SOURCE AND DRAIN REGION OF NMOS
2.EMITTER TERMINAL OF BJT
3.AND INTO NWELL COLLECTOR REGION FOR CONTACT PURPOSE
6/3/2015 105

N Plus Buried Layer
N-Well (Collector)
N-Well
N-
Diff
N-
Diff
P-Diff P-Diff
P-Base
N-Plus
Emitter
P-SUBSTRATE
P-EPITAXY
THE P-TYPE IMPURITES ARE HEAVILY DOPED TO FORM
1.SOURCE AND DRAIN REGION OF PMOS
2.AND INTO P-BASE REGION FOR CONTACT PURPOSE
6/3/2015 106

N Plus Buried Layer
N-Well (Collector)
N-Well
N-
Diff
N-
Diff
P-Diff P-Diff
P-Base
N-Plus
Emitter
P-SUBSTRATE
P-EPITAXY
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER
6/3/2015 107

N Plus Buried Layer
N-Well (Collector)
N-Well
N-
Diff
N-
Diff
P-Diff P-Diff
P-Base
N-Plus
Emitter
P-SUBSTRATE
P-EPITAXY
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER AND IS
PATTERNED FOR CONTACT CUTS
6/3/2015 108

NMOS PMOS
G D
S G D
S
NPN-BJT
C B E
N Plus Buried Layer
N-Well (Collector)
N-
Diff
N-
Diff
P-Diff P-Diff N-Plus
Emitter
P-SUBSTRATE
P-EPITAXY
METAL CONTACTS ARE FORMED
6/3/2015 109

Resistors & Capacitors
fabrication
6/3/2015 110

6/3/2015 111
Oh s La
• Current I in terms of Jn
• Voltage V in terms of electric field
– Result for R
IR
V 
JtW
JA
I 

L
V
E /

E
W
t
JtW
JA
I 



V
L
W
t
JtW
JA
I




t
W
L
R

1

t
W
L
R



6/3/2015 112
Sheet Resistance (Rs)
• IC resistors have a specified thickness – not
under the control of the circuit designer
• Eliminate t by absorbing it into a new
parameter: the sheet resistance (Rs)





















W
L
R
W
L
t
Wt
L
R sq


Nu e of “ ua es

6/3/2015 113
ELECTRON AND HOLE MOBILITY
Carrier Mobilities versus Doping Concentration
0.00E+00
2.00E+02
4.00E+02
6.00E+02
8.00E+02
1.00E+03
1.20E+03
1.40E+03
1.60E+03
1.00E+14 1.00E+15 1.00E+16 1.00E+17 1.00E+18 1.00E+19
Doping Concentration (Na or Nd)
Carrier
Mobility
(cm2/V-sec)
mu_n
mu_p

6/3/2015 114
DIFFUSED RESISTOR
Aluminum contacts
The n-type wafer is always biased positive with respect to the p-type
diffused region. This ensures that the pn junction that is formed is in
reverse bias, and there is no current leaking to the substrate. Current
will flow through the diffused resistor from one contact to the other.
The I-V characteristic follows Ohm’s Law: I = V/R
n-wafer Diffused p-type region
Silicon dioxide

6/3/2015 115
Layout/Mask Layer 1 - Diffusion
(green)
L
W
L/W is the number of ‘squares’ long the resistor is said to be.
The sheet resistance rhos, is the resistance of each square
5 squares in this case
If rhos is 100 ohms per
square,
R = 500 ohms
The resistance, R = rhos (L/W)
Top View
Side View
P type Diffusion
N wafer
Resistor
termination

6/3/2015 116
IC Fabrication: Ion Implantation
• Si substrate (p-type)
• Grow oxide (thermally)
• Add photoresist
• Expose (visible or UV source)
• Etch (chemical such as HF)
• Ion implantation (inject dopants)
• Diffuse (increase temperature and allow
dopants to diffuse)
P-type Si Substrate
oxide
N-type diffusion region

6/3/2015 117
Using Sheet Resistance (Rs)
• Ion-i pla ted o diffused IC esisto

P-type Si Substrate
6/3/2015 118
Poly Film Resistor
• To lower the capacitive parasitics, we should
build the resistor further away from substrate
• We a deposit a thi fil of pol “i hea il
doped) material on top of the oxide
• The poly will have a certain resistance (say 10
Ohms/sq)
Oxide
Polysilicon Film (N+ or P+ type)

6/3/2015 119
Diffused Resistor
-Dope a region of the silicon (n-type or p-type) to an acceptable
NA or ND.
-Then place a contact at each end of the diffusion region.
-The diffusion region will have a given resistivity specified in
"Oh s / “ ua e
-Then alter the geometry (L/W ration) to get the desired
resistance - typically these have a sheet resistance between 100
to 200 ohms/sq - to save space
-These are laid out using a serpentine geometry

-The interesting thing about the l/W ratio is that if l=W, then the
shape is a square and R=Rs, this is true no matter how big the
square is.
-In fact, the l/W ratio is actually the number of squares in a given
trace geometry - We typically just count the squares and use:
R= Rs*(no.of.squares)
6/3/2015 120

6/3/2015 121
Polysilicon Resistor
-Another way to fabricate a resistor is to use Polysilicon.
-Polysilicon has a high resistivity prior to Ion Implantation
-Use undoped Polysilicon to create a high value resistor
Before Ion Implantation : Rs = 10M Ohms/Square
After Ion Implantation : Rs = 20 to 40 Ohms/Square
- Typically don't even need 1 square to get our resistively so we
don't need to do a serpentine layout
- One drawback is that the resistance can vary widely with
process when using less than 1 square to get a resistor in the k-
Ohms range.
- These are typically used when we just want a BIG resistor and
don't care about the exact value

6/3/2015 122
Metal Resistor
-Metal can also be used for very small resistors
-The M1 layer typically has sheet resistance on the order of
mohms/sq.
- Use a serpentine layout to get a small resistor (1-10 ohms)

Cross sections of resistors of various types available from a typical n-well CMOS process.
-n-well process is used for medium value of resistors, while the n+
and p+ diffusions are useful for low value resistors.
-The resistance value depends on the length and width of the
diffused regions, the tolerance of the resistor value is very poor
(i.e., 20 to 50 %)
6/3/2015 123

6/3/2015 124
Capacitors
• Composed of two conductive plates separated
by an insulator (or dielectric).
– Commonly illustrated as two parallel metal plates
separated by a distance, d.
– C = e A/d
– where e = er eo
– er is the relative dielectric constant
– eo is the vacuum permittivity

6/3/2015 125
CMOS Capacitors
-There are 3 common ways to make a capacitor
1) MOS Capacitor:
-simply create a MOS structure where the Gate (Metal) terminal
is one terminal and the Body (Semiconductor) terminal is
Ground
- while this is easy to implement, the capacitance changes with
the bias voltage (i.e., VG) due to the depletion and inversion
which occurs

6/3/2015 126
MIM Capacitor
-"Metal Insulator Metal"-this is simply a parallel plate capacitor
using two metals and an insulator
-This type of capacitor is created using an extra process step that
puts in an additional metal layer that can be very close to one of
the other metal layers to get a smaller plate-to-plate separation
-Since the plates are made of metal, the capacitance doesn't
change with bias voltage-these capacitors are not as large as MOS
capacitors

Interpoly and MOS capacitors in an n-well CMOS process.
6/3/2015 127

UNIT 2
BASIC ELECTRICAL PROPERTIES
Topics
• Basic electrical properties of MOS and BiCMOS
circuits:
• Ids-Vds relationships
• MOS transistor threshold voltage, gm, gds
• figure of merit wo
• pass transistor
• NMOS inverter
• Various pull-ups
• CMOS inverter analysis and design
• BiCMOS inverters
6/3/2015 129

MOSFET I-V Characteristics
I-V Plots, Channel Length Modulation
– Saturation
equation yields
curves
independent of
VDS. Not sure! So
we consider the
effect of channel
length
modulation.
130
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
VDS(V)
I
D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
6/3/2015

Channel Length Modulation
• Channel Length
Modulation
– With pinch-off the
channel at the point
y such that
Vc(y)=VGS - VT0,
The effective
channel length is
e ual to L = L – ΔL
– ΔL is the length
of channel segment
over which QI=0.
– Pla e L i the
ID(SAT) equation:
2
0
)
( )
(
2
V
V
L
W
C
I T
GS
ox
n
SAT
D 



ΔL
Drain
n+
Source
n+
Substrate (p-Si)
(p+) (p+)
Oxide
0 y L’ L
ChannelPinch-off point (QI=0)
Depletion region
VB=0
VS=0
VGS>VT0
VDS>VDSAT
6/3/2015 131

Channel Length Modulation
– ΔL increases with an increase in VDS.
We can use
– λ: channel length modulation
coefficient
– ID(SAT) can be rewritten as
– The above form produces a
discontinuity of current at VDS=VGS-
VT0. We can include the term in ID(lin)
with little error since λ is typically less
than 0.1. We will usually ignore λ in
manual calculations.
 
V
L
V
L
L
ΔL
L
L
ΔL
L
L
ΔL
L
L
DS
DS











 1
1
1
1
1
1
1
1
1
1
1
'
1
)
1
(
)
(
2
2
0
)
( V
V
V
L
W
C
I DS
T
GS
ox
n
SAT
D 




6/3/2015 132

Substrate Bias Effect
– So far, VSB=0 and thus VT0 used in the equations.
– Clearly not always true – must consider body effect
– Two MOSFETs in series:
–
–
– V“B M = VD“ M ≠ . Thus, VT i the M e uatio is epla ed
by VT = VT(VSB) as developed in the threshold voltage section.
D
S
G
D
G
M1
M2 VSB
S
6/3/2015 133

Substrate Bias Effect (Cont.)
• The general form of ID can be written as
• ID = f (VGS,VDS,VSB)
• which due to the body effect term is non-
linear and more difficult to handle in manual
calculations
6/3/2015 134

Summary of Analytical Equations
– The voltage directions and relationships for the three
modes of pMOS are in contrast to those of nMOS.
nMOS
Mode ID Voltage Range
Cut-off 0 VGS<VT
Linear (ȝnCox/2)(W/L)[2(VGS-
VT)VDS-VDS
2]
VGSVT，VDS< VGS
-VT
Saturatio
n
(ȝnCox/2)(W/L)(VGS-
VT)2(1+ȜVDS)
VGS  VT，VDS 
VGS -VT
pMOS
Cut-off 0 VGS>VT
Linear (ȝnCox/2)(W/L)[2(VGS-
VT)VDS-VDS
2]
VGS  VT，VDS>
VGS -VT
Saturatio (ȝnCox/2)(W/L)(VGS-
2
VGS  VT，VDS
G
D
B
S
VDS
VSB
VGS ID
G
S
B
D
VDS
VSB
VGS
ID
6/3/2015 135

6/3/2015 136
Pass-Transistor Logic Circuits (1)
 A simple approach for implementing logic functions utilizes series and
parallel combinations of switches that are controlled by input variables to
connect the input and output nodes.
 Each of the switches can be implemented either
by a single NMOS transistor or by a pair of CMOS
transistors connected in CMOS transmission gate
configuration.
CMOS transmission gate
Y=AC

6/3/2015 137
 An essential requirement in the design of pass-transistor logic is
ensuring that every circuit node has at all times a low-resistance path to
VDD or to ground.
 If B is high, S1 closes and Y=A.
 Y will be VDD if A is high or ground if
A is low.
 If B is low, S1 opens and Y becomes
a high-impedance node.
 If voltage of Y is initially zero, it will
remain so.
 If voltage of Y is initially high at VDD,
then the inevitable leakage current will
discharge the C and can no longer be
considered a static circuit.
A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided
in
(b) through switch S2.

6/3/2015 138
 The problem can be easily solved by establishing for node Y a low-
resistance path that is activated when B goes low.
 Another switch, S2, controlled by B
is connected between Y and ground.
 When B goes low, S2 closes and
establishes a low-resistance path
between Y and ground.
A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in
(b) through switch S2.

Terminal Voltages
• Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
• Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
• nMOS body is grounded.
• Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-
6/3/2015 140

nMOS Cutoff
• No channel
• Ids = 0
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-type body
b
g
s d
6/3/2015 141

nMOS Linear
• Channel forms
• Current flows from d to s
– e- from s to d
• Ids increases with Vds
• Similar to linear resistor
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s d
Ids
6/3/2015 142

nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
+
-
Vgs
> Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids
6/3/2015 143

I-V Characteristics
• In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
6/3/2015 144

Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
6/3/2015 145

Channel Charge
• Qchannel = CV
• C =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
= 3.9)
polysilicon
gate
6/3/2015 146

Channel Charge
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL
• V =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
= 3.9)
polysilicon
gate
Cox = ox / tox
6/3/2015 147

Channel Charge
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
= 3.9)
polysilicon
gate
Cox = ox / tox
6/3/2015 148

Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
6/3/2015 149

Carrier velocity
• v = mE m called mobility
• E =energy
6/3/2015 150

Carrier velocity
• E = Vds/L
• Time for carrier to cross channel:
– t =
6/3/2015 151

Carrier velocity
• E = Vds/L
• Time for carrier to cross channel:
– t = L / v
6/3/2015 152

nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
ds
I 
6/3/2015 153

nMOS Linear I-V
• Now we know
channel
ds
Q
I
t


6/3/2015 154

nMOS Linear I-V
• Now we know
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V



 
  
 
 
 
  
 
 
ox
=
W
C
L
 
6/3/2015 155

nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
ds
I 
6/3/2015 156

nMOS Saturation I-V
2
dsat
ds gs t dsat
V
I V V V
  
  
 
 
6/3/2015 157

nMOS Saturation I-V
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 
6/3/2015 158

nMOS I-V Summary
• Shockley 1st order transistor models
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


6/3/2015 159

Example
• Example: a 0.6 mm process from AMI
semiconductor
– tox = 100 Å
– m = 350 cm2/V*s
– Vt = 0.7 V
• Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 l
 
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L
  


 
   
  
 
 
  
 
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
Vds
I
ds
(mA)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs
= 1
6/3/2015 160

MOS Transistor Basics
Two Terminal Structure
• Two terminal structure (p-substrate): The MOS
capacitor
• Important derived parameters. With VG = VB = 0:
– F – Buck Fermi Potential (Substrate)
– S – Surface Potential (Substrate)
161
A D I
VG
VB
6/3/2015

Two Terminal Structure (Continued)
– VSB – Flat Band Voltage (applied
external voltage to G-B to flatten bands
of substrate – equal to built-in potential
difference of MOS – equal to work
function difference GB between the
substrate (channel) and gate.
• Operation
– With VG<0, VB=0, Accumulation – Holes
accumulate at substrate-oxide interface
due to attraction of negative bias
– With VG>0, but small, VB=0,
Depletion – Holes repelled from
substrate-oxide interface due to
positive bias leaving negatively charged
fixed acceptors ions behind. The result
is a region below the interface that is
depleted of mobile carriers.
• Depletion region thickness
N
q A
F
S
d
S
i
x


 

2
6/3/2015 162

• Depletion region charge density
– Note that this density is per unit of area.
– With VG>0 and larger, VB=0, Inversion –
A n-type inversion layer forms, a
condition known as surface inversion.
The surface is inverted when the
density of electrons at the surface
equals the density of holes in the bulk.
This implies that s has the same
magnitude but opposite sign to F. At
the point depletion depth fixed and the
maximum depletion region depth is at
s = -F. This depth is:
N
q A
F
S
dm
i
x

 2
2



 F
s
S
A
d
A i
N
q
x
N
q
Q 



 2
6/3/2015 163

– The corresponding
depletion charge density
(per unit area) at surface
inversion is
– The inversion phenomena
is the mechanism that
forms the n-channel. The
depletion depth and the
depletion region charge
are critical in determining
properties of MOSFET.

 F
S
A
d
A i
N
q
x
N
q
Q 2
2
0 




6/3/2015 164

Four Terminal Structure
• p-Substrate
• The MOS n-channel
transistor structure:
L
G(ate)
D(rain)
n+
B(Body, Bulk or Substrate)
S(ource)
n+
p
6/3/2015 165

Four Terminal Structure (Continued)
• Symbols: n-channel - p-substrate; p-
channel – n-substrate
• N-channel (for P-channel, reverse
arrow or add bubbles)
•
P-
channel
• Enhancement mode: no conducting
channel exists at VGS = 0
• Depletion mode: a conducting
channel exists at VGS = 0
G
D
B
S
G
D
S
G
D
S
G G
D
S
S
D
6/3/2015 166

Four Terminal Structure (Continued)
• Source and drain identification
G
D
B
S
VDS
VSB
VGS
6/3/2015 167

Threshold Voltage Components
• Consider the prior 3-D drawing: Set VS=0, VDS=0,
and VSB=0.
– Increase VGS until the channel is inverted. Then a
conducting channel is formed and the depletion
region thickness (depth) is maximum as is the surface
potential.
– The value of VGS needed to cause surface inversion
(channel creation) is the threshold voltage VT0. The 0
refers to VSB=0.
– VGS< VT0: no channel implies no current flow possible.
With VGS> VT0, existence the channel implies possible
current flow.
6/3/2015 168

Threshold Voltage Components (Cont.)
• GC work function difference between gate and
channel material which is the built-in voltage that
must be offset by voltage applied to flatten the
bands at the surface.
• Apply voltage to achieve surface inversion -2F
• Additional voltage must be applied to offset the
depletion region charge due to the acceptor ions. At
inversion, this charge with VSB=0 is QB0= Q0.
• For VSB non-zero,
• The voltage required to offset the
depletion region charge is defined by –QB/Cox
where Cox = εox/tox with tox, the oxide thickness,
and Cox, the gate oxide capacitance per unit area.
• 4) The final component is a fixed positive
charge density that appears at the interface
between the oxide and the substrate, Qox. The
voltage to offset this charge is:
V
N
q
Q SB
F
S
A i



 
 2
2
C
Q
ox
ox

6/3/2015 169

• These components together give:
• For VSB=0, VT0 has QB replaced by QB0. This
gives a relationship between VT and VT0
which is:
• Thus the actual threshold voltage VT differs
from VT0 by the term given. Going back to
the definition of QB, this term is equal to:
• In which γ is the substrate-bias (or body
effect) coefficient.
ox
B
B
T
T
C
Q
Q
V
V 0
0



 
F
SB
F V 

 2
2 



ox
ox
ox
B
F
GC
T
C
Q
C
Q
V 



 
2
6/3/2015 170

• The final expression for VT0 and VT
are
• and
– The threshold voltage depends on
the source-to-bulk voltage which is
clearly separated out. The
component is referred to as body
effect. If the source to body voltage
VSB is non-zero, the corrective term
must be applied to VT0.
C
N
q
ox
S
A i


2

 
F
SB
F
T
T V
V
V 

 2
2
0 




ox
ox
ox
B
F
GC
T
C
Q
C
Q
V 



 0
0 2
6/3/2015 171

•
• Those parameters in the VT
equation are signed. The following
table gives their signs for nMOS and
pMOS transistor.
• For real designs, the threshold
voltage, due to variation in oxide
thickness, impurity concentrations,
etc., VT0 and γ should be measured
from the actual process.
Parameter nMOS pMOS
F  
QB, QB0  
γ  
VSB  
6/3/2015 172

R
Vss
R
1 0
0 1
Vo
•Inverter : basic requirement for
producing a complete range of
Logic circuits
6/3/2015 173

Vdd
Vss
Vo
Vin
R Pull-Up
Pull Down
Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
Supply rail
Output is taken from the drain and control
input connected between gate and ground
Resistors are not easily formed in silicon
- they occupy too much area
Transistors can be used as the pull-up device
6/3/2015 174

Vdd
Vss
Vo
Vin
D
S
D
S
• Pull-Up is always on – Vgs = 0; depletion
• Pull-Down turns on when Vin > Vt
NMOS Depletion Mode Transistor Pull - Up
Vt
V0
Vdd
Vi
• With no current drawn from outputs, Ids
for both transistors is equal
Non-zero output
6/3/2015 175

Vgs=0.2VDD
Vgs=0.4 VDD
Vgs=0.6 VDD
Vgs=0.8VDD
Vgs=VDD
Ids
Vds
VDD
Vo
VDD
VDD
Vin
Ids
VDD –Vds
Ids
Vds
Vgs=-0.6VDD
Vgs=-0.4 VDD
Vgs=-0.2 VDD
Vgs=0
Vgs=0.2VDD
6/3/2015 176

Vo
VDD
VDD
Vin
Vinv
• Point where Vo = Vin is called Vinv
Decreasing
Zpu/Zpd
Increasing
Zpu/Zpd
• Transfer Characteristics and Vinv can be shifted by altering ratio
of pull-up to Pull down impedances
6/3/2015 177

NMOS Depletion Mode Inverter
Characteristics
• Dissipation is high since rail to rail current
flows when Vin = Logical 1
• Switching of Output from 1 to 0 begins when
Vin exceeds Vt of pull down device
• When switching the output from 1 to 0, the
pull up device is non-saturated initially and
this presents a lower resistance through which
to charge capacitors (Vds < Vgs – Vt)
6/3/2015 178

Vss
Vo
Vin
D
S
D
S
NMOS Enhancement Mode Transistor Pull - Up
Vdd
Vgg
Vt (pull down)
V0
Vdd
Vt (pull up)
Non zero output
Vin
• Dissipation is high since current flows when Vin = 1
• Vout can never reach Vdd (effect of channel)
• Vgg can be derived from a switching source (i.e. one phase
of a clock, so that dissipation can be significantly reduced
• If Vgg is higher than Vdd, and extra supply rail is required
6/3/2015 179

When cascading logic devices care must be taken
to preserve integrity of logic levels
i.e. design circuit so that Vin = Vout = Vinv
Cascading NMOS Inverters
Determine pull – up to pull-down ratio for driven inverter
6/3/2015 180

Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore:Ids = K (W/L) (Vgs – Vt)2/2
Depletion mode transistor has gate connected to source, i.e. Vgs = 0
Ids = K (Wpu/Lpu) (-Vtd)2/2
Ids = K (Wpd/Lpd) (Vinv – Vt)2/2
Enhancement mode device Vgs = Vinv, therefore
Assume currents are equal through both channels (no current drawn by load)
(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2
Convention Z = L/W
Vinv = Vt – Vtd / (Zpu/Zpd)1/2
Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd
This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inverter
6/3/2015 181

Vdd Vdd
A B C
Inverter 1 Inverter 2
Vin1 Vout2
Pull-Up to Pull-Down Ratio for an nMOS inverter driven
through 1 or more pass transistors
It is often the case that two inverters are connected via a series of switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade the logic levels into
Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)
6/3/2015 182

Complimentary Transistor Pull – Up (CMOS)
Vdd
Vss
Vo
Vin
Vout
Vin
Vdd
Vss
Vtn Vtp
Logic 0 Logic 1
P on
N off
Both On
N on
P off
6/3/2015 183

Vout
Vin
Vdd
Vss
Vtn Vtp
P on
N off
Both On
N on
P off
1 2 3 4 5
1: Logic 0 : p on ; n off
5: Logic 1: p off ; n on
2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
4: same as 2 except reversed p and n
3: Both transistors are in saturation
Large instantaneous current flows
6/3/2015 184

CMOS INVERTER CHARACTERISTICS
Current through n-channel pull-down transistor
 2
2
tn
in
n
n V
V
I 


Current through p-channel pull-up transistor
 
 2
2
tp
DD
in
p
p V
V
V
I 




At logic threshold, In = Ip
   
 
   
 
 
tp
DD
tn
p
n
p
n
in
tp
DD
in
tn
in
p
n
tp
DD
in
p
tn
in
n
tp
DD
in
p
tn
in
n
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V





































1
2
2
2
2
2
2
p
n
p
n
tn
tp
DD
in
V
V
V
V








1
If n = p and Vtp = –Vtn
2
DD
in
V
V 
n
n
n
p
p
p
L
W
L
W 


Mobilities are unequal : µn = 2.5 µp
Z = L/W
Zpu/Zpd = 2.5:1 for a symmetrical CMOS inverter
6/3/2015 185

CMOS Inverter Characteristics
• No current flow for either logical 1 or logical 0
inputs
• Full logical 1 and 0 levels are presented at the
output
• For devices of similar dimensions the p –
channel is slower than the n – channel device
6/3/2015 186

CMOS Inverter VTC
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
V
out
(V)
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS sat
PMOS sat
NMOS res
PMOS sat NMOS res
PMOS off
6/3/2015 187

Cutoff Linear Saturation
pMOS Vin -VDD= VGS> VT Vin -VDD=VGS< VT
Vin -Vout=VGD< VT
Vin -VDD=VGS> VT
Vin -Vout=VGD>VT
nMOS Vin = VGS< VT Vin =VGS> VT
Vin -Vout =VGD> VT
Vin =VGS> VT
Vin -Vout =VGD< VT
VDD
Vin Vout
CL
G S
D
D
G
S
Regions of operations
For nMOS and pMOS
In CMOS inverter
6/3/2015 188

Impact of Process Variation
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
V
out
(V)
Nominal
Good PMOS
Bad NMOS
Bad PMOS
Good NMOS
Pprocess variations (mostly) cause a shift in the switching
threshold
6/3/2015 189

Cmos Inverter
• Look at why our NMOS and PMOS inverters
might not be the best inverter designs
• Introduce the CMOS inverter
• Analyze how the CMOS inverter works
6/3/2015 190

NMOS Inverter
• When VIN changes to logic 0, transistor gets
cutoff. ID goes to 0.
• ‘esisto oltage goes to ze o. VOUT pulled
up to 5 V.
D
ID = 5/R
+
VDS
_
R
5 V
VOUT
VIN
5 V
0 V
D
ID = 0
+
VDS
_
R
5 V
VOUT
VIN
0 V
5 V
When VIN is logic 1, VOUT is
logic 0.
Constant nonzero current
flows through transistor.
Power is used even though
no new computation is being
performed.
6/3/2015 191

PMOS Inverter
• When VIN changes to logic 1, transistor gets
cutoff. ID goes to 0.
• ‘esisto oltage goes to ze o. VOUT pulled
do to V.
5 V
VOUT
ID = -5/R
-
VDS
+
R
5 V
When VIN is logic 0, VOUT is
logic 1.
Constant nonzero current
flows through transistor.
Power is used even though
no new computation is being
performed.
VIN
0 V
5 V
VOUT
ID = 0
-
VDS
+
R
0 V
VIN
5 V
6/3/2015 192

Analysis of CMOS Inverter
• We can follow the same procedure to solve for
currents and voltages in the CMOS inverter as
we did for the single NMOS and PMOS
circuits.
• Remember, now we have two transistors so
we write two I-V relationships and have twice
the number of variables.
• We can roughly analyze the CMOS inverter
graphically.
D
S
VDD (Logic1)
D
S
VOUT
VIN
NMOS is “pull-down device”
PMOS is “pull-up device”
Each shuts off when not pulling
6/3/2015 193

D
S
VDD (Logic 1)
D
S
VOUT
VIN
VGS(n) = VIN
VGS(p) = VIN – VDD
VGS(p) = VDS(n) - VDD
ID(p) = -ID(n)
VDS(n) = VOUT
VDS(p) = VOUT – VDD
VDS(p) = VDS(n) - VDD
+
VDS(n)
_
Use these equations
to write both I-V equations in terms of
VDS(n) and ID(n)
Linear KVL and KCL Equations
6/3/2015 194

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
0.9 V
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
6/3/2015 195

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
1.5 V
6/3/2015 196

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
2.0 V
6/3/2015 197

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
2.5 V
6/3/2015 198

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
3.0 V
6/3/2015 199

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
3.5 V
6/3/2015 200

VDS(n)
ID(n)
VDD
NMOS I-V curve
PMOS I-V curve
NMOS variables)
CMOS Analysis
VIN = VGS(n) =
4.1 V
6/3/2015 201

VOUT
VIN
C
B
A E
D
VDD
VDD
CMOS Inverter VOUT vs. VIN
NMOS:
cutoff
PMOS:
triode
NMOS:
saturation
PMOS:
triode
NMOS:
triode
PMOS:
saturation
NMOS:
triode
PMOS:
cutoff
both
sat.
curve very steep
here; only in “C”
for small interval
of VIN
6/3/2015 202

ID
VIN
C
B
A E
D
VDD
CMOS Inverter ID
6/3/2015 203

D
S
VDD
D
S
VOUT1
VIN
D
S
VDD
D
S
VOUT2
Important Points
• No ID current flow in Regions A and E if
nothing attached to output; current flows only
during logic transition
• If another inverter (or other CMOS logic)
attached to output, transistor gate terminals
of attached stage do not permit current:
current still flows only during logic transition
6/3/2015 204

Impact of Process Variation
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
V
out
(V)
Nominal
Good PMOS
Bad NMOS
Bad PMOS
Good NMOS
Pprocess variations (mostly) cause a shift in the switching
threshold
6/3/2015 205

Beta Ratio
• If bp / bn  1, switching point will move from
VDD/2
Vout
0
Vin
VDD
VDD
0.5
1
2
10
p
n



0.1
p
n



6/3/2015 206

Unit III
VLSI CIRCUIT DESIGN PROCESSES
Topics
• VLSI design flow
• MOS layers
• Stick diagrams
• Design Rules and Layout
• 2 um CMOS design rules for wires
• Contacts and Transistors
• Layout diagrams for NMOS and
• CMOS inverters and gates, Scaling of MOS circuits
6/3/2015 207

VLSI Design of approach of IC
208
6/3/2015

Layer Types
• p-substrate
• n-well
• n+
• p+
• Gate oxide (thin oxide)
• Gate (polycilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation
6/3/2015 209

Stick diagram
Encodings for a simple single metal nMOS process
COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER
MONOCROME MONOCROME
GREEN
RED
BLUE
BLACK
GRAY
n-
diffusion
n+active
Thniox
Polysilicon
Metal 1
Contact cut
Overglass
NOT
APPLICABLE
nMOS
ONLY
YELLO
W
Implant
Buried
contact
nMOS
ONLY
BROWN
N
D
NP
N
M
N
C
N
G
NI
NB
6/3/2015 210

Stick Diagrams
Metal
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Buried Contact
Contact Cut
6/3/2015 211

Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information through
colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and
the actual layout.
6/3/2015 212

Stick Diagrams
• Does show all components/vias.
• It shows relative placement of
components.
• Goes one step closer to the layout
• Helps plan the layout and routing
6/3/2015 213

Stick Diagrams
• Does not show
– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub
boundaries.
– Any other low level details such as
parasitics..
6/3/2015 214

Stick Diagrams – Some rules
• Rule 1.
• Whe t o o o e sti ks of the sa e t pe
cross or touch each other that represents
electrical contact.
Stick Diagrams
6/3/2015 215

• Rule 2.
• Whe t o o o e sti ks of diffe e t t pe
cross or touch each other there is no electrical
contact.
(If electrical contact is needed we have to
show the connection explicitly).
Stick Diagrams
6/3/2015 216

• Rule 3.
• When a poly crosses diffusion it represents
a transistor.
Note: If a contact is shown then it is not a transistor.
Stick Diagrams
6/3/2015 217

• Rule 4.
• In CMOS a demarcation line is drawn to
avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all nMOS
will have to be on the other side.
Stick Diagrams
6/3/2015 218

5 V
Dep
Vout
Enh
0V
Vin
5 v
0 V
Vin
5 v
NMOS INVERTER
6/3/2015 220

Sticks design CMOS NAND:
• Start with NAND gate:
6/3/2015 228

6/3/2015 229
NAND sticks
VDD
a
VSS
out
b

Stick Diagram - Example
NOR Gate
OUT
B
A
6/3/2015 230

Stick Diagram - Example
Power
Ground
B
C
Out
A
6/3/2015 231

Design Rules
• Design rules are a set of geometrical
specifications that dictate the design of the layout
masks
• A design rule set provides numerical values
– For minimum dimensions
– For minimum line spacings
• Design rules must be followed to insure
functional structures on the fabricated chip
• Design rules change with technological advances
(www.mosis.org)
6/3/2015 238

Silicon Foundry
• A standard
• A foundry allows designers to submit designs
using a state-of-the-art process
• Each foundry state simpler set of design rules
called lambda design rules
• All widths, spacings, and distances are written in
the form
– Value =
– TSMC (Thailand Semiconductor Manufacturing
Corporation)

m
6/3/2015 239

Design Rules Classification
• Minimum width
• Minimum spacing
• Surround
• Extension
6/3/2015 240

Physical Limitations
• Line width limitation of an imaging system
– The reticle shadow projected on the photoresist
does not have sharp edges due to optical
diffraction
• Etching process problem
– Undercutting of the resist due to lateral etching
decreases the resolution
6/3/2015 241

6/3/2015 242
Etching Process Problem
Substrate
Vertical etching
Lateral
Etching
Substrate
Isotropic etch

Depletion Region
• If depletion regions of adjacent pn junctions
touch, then
– The current blocking characteristics are altered
– Current can flow between the two
Substrate
n+ n+
Limits on n+ spacing
Spacing
6/3/2015 243

Electrical Capacitive Coupling
• This occurs between closely spaced
conducting lines
• This leads to a problem called crosstalk
– A portion of the electrical energy is coupled to
another causing noise
– This is a major problem in high-density design
6/3/2015 244

Electrical Rules
• An example of an electrical rule is the allowed
width of a metal interconnect line
– To avoid electromigration effects
– The design rule set will stipulate the maximum
current flow level permitted
6/3/2015 245

3D Perspective
Polysilicon Aluminum
6/3/2015 246

Design rules and Layout
• Why we use design rules?
– Interface between designer and process engineer
– Guidelines for constructing process masks
6/3/2015 247

Design Rules
Minimum length or width of a feature on a layer is 2
Why?
To allow for shape contraction
Minimum separation of features on a layer is 2
Why?
To ensure adequate continuity of the intervening
materials.
6/3/2015 248

Design Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven
surface than other conducting layers to ensure their continuity
2
Metal
Diffusion
Polysilicon
3
2
6/3/2015 249

Design Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current
2
Metal
Diffusion
Polysilicon
2
3
6/3/2015 250

Design Rules
Diffusion – PolySi  To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines
can overlap or cross

Metal
Diffusion
Polysilicon
6/3/2015 251

Metal Vs PolySi/Diffusion
• Metal lines can pass over both diffusion and
polySi without electrical effect
• It is recommended practice to leave 
between a metal edge and a polySi or
diffusion line to which it is not electrically
connected

Metal
Polysilicon
6/3/2015 252

 poly-poly spacing 2
 diff-diff spacing 3
(depletion regions tend to spread outward)
 metal-metal spacing 2
 diff-poly spacing 
6/3/2015 253
Review:

Note
• Two Features on different mask layers can be
misaligned by a maximum of 2l on the wafer.
• If the overlap of these two different mask
layers can be catastrophic to the design, they
must be separated by at least 2l
• If the overlap is just undesirable, they must
be separated by at least l
6/3/2015 254

When a transistor is formed?
Gate is formed where polySi crosses diffusion with
thin oxide between these layers.
Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2
And
6/3/2015 255

The polySi of the gate extends 2 beyond the gate area on
to the field oxide to prevent the drain and source from shorting.
no overlap overlap
diffusion
short
• Diffusion Problems
PolySi extends in the gate region…
6/3/2015 256

Depletion Transistor
We need depletion implant
An implant surrounding the Transistor by 2
Ensures that no part of the transistor remains
in the enhancement mode
A separation of 2 from the gate of an
enhancement transistor avoids affecting
the device.
2
6/3/2015 257

Depletion Transistor
Implants are separated by 2to prevent them from merging
2
6/3/2015 258

Butting Contact
The gate and source of a depletion device can be connected
by a method known as butting contact. Here metal makes
contact to both the diffusion forming the source of the
depletion transistor and to the polySi forming this device’s
gate.
Advantage:
No buried contact mask required and avoids
associated processing.
6/3/2015 259

Butting Contact
n+ n+
Insulating
Oxide
Metal
Gate Oxide PolySi
Problem: Metal descending the hole has a tendency to
fracture at the polySi corner, causing an open circuit.
6/3/2015 260

Buried Contact
It is a preferred method. The buried contact window
defines the area where oxide is to be removed so that
polySi connects directly to diffusion.
Contact Area must be a min. of 2*2to ensure
adequate contact area.
2
2
Contact Area
6/3/2015 261

Buried Contact
The buried contact window surrounds this contact by in all
directions to avoid any part of this area forming a transistor.
Separated from its related transistor gate by  to prevent gate
area from being reduced.

6/3/2015 262

Buried Contact
Here gate length is depend upon the alignment of the
buried contact mask relative to the polySi and therefore
vary by .
2
2
  Channel length 
PolySi
Buried contact
Diffusion
6/3/2015 263

Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 2*2
Metal and polySi or diffusion must overlap this contact area
by so that the two desired conductors encompass the contact
area despite any mis-alignment between conducting layers
and the contact hole
4
6/3/2015 264

Contact Cut
Contact cut – any gate: 2apart
Why? No contact to any part of the gate. 
4
2
6/3/2015 265

Contact Cut
Contact cut – contact cut: 2apart
Why? To prevent holes from merging. 
2
6/3/2015 266

Rules for CMOS layout
Similar to those for NMOS except No
1. Depletion implant
2. Buried contact
Additional rules
1. Definition of n-well area
2. Threshold implant of two types of transistor
3. Definition of source and drains regions for the
NMOS and PMOS.
6/3/2015 267

To ensure the separation of the PMOS and NMOS devices,
n-well supporting PMOS is 6away from the active
area of NMOS transistor.
Why?
Avoids overlap
of the associated
regions
n-well
n+
6
6/3/2015 268

2
2
N-well must completely
surround the PMOS
device’s active area by 2
6/3/2015 269

2
2
The threshold implant
mask covers all n-well
and surrounds the n-well
by 
6/3/2015 270

2
2
The p+ diffusion mask
defines the areas to
receive a p+ diffusion.
It is coincident with the
threshold mask
surrounding the PMOS
transistor but excludes
the n-well region to be
connected to the supply.
6/3/2015 271

A p+ diffusion is required to effect the ground connection
to the substrate. Thus mask also defines this substrate
region. It surrounds the conducting material of this
contact by .
4
6/3/2015 272

Total contact area = 2*4
Neither NMOS nor CMOS usually allow contact cuts
to the gate of a transistor, because of the danger of
etching away part of the gate
6/3/2015 273

UNIT-IV
GATE LEVEL DESIGN
Topics
• Logic gates and other complex gates
• Switch logic
• Alternate gate circuits
• Time delays
• Driving large capacitive loads
• Wiring capacitances
• Fan-in and fan-out, Choice of layers
6/3/2015 274

6/3/2015 275
NMOS Gate construction
A
B
A • B
A B
A + B
•NMOS devices in series implement a NAND function
•NMOS devices in parallel implement a NOR function
0
1
1
1
0
1
1
1
0
1
0
0
F
B
A
0
1
1
0
0
1
0
1
0
1
0
0
F
B
A

6/3/2015 276
PMOS Gate construction
A • B
A B
•PMOS devices in parallel implement a NAND function
A + B
A
B
•PMOS devices in series implement a NOR function
0
1
1
1
0
1
1
1
0
1
0
0
F
B
A
0
1
1
0
0
1
0
1
0
1
0
0
F
B
A

Parasitics and Performance
• Consider the
following layout:
• What is the impact
on performance of
parasitics
– At point a (VDD rail)?
– At point b (input)?
– At Point c (output)?
b
a
c
6/3/2015 277

• a - power supply
connections
– capacitance - no
effect on delay
– resistance - increases
delay (see p. 135)
• minimize by reducing
difffusion length
• minimize using
parallel vias
b
a
c
6/3/2015 278

• b - gate input
– capacitance
increases delay on
previous stage (often
transistor gates
dominate)
– resistance increases
delay on previous
stage
b
a
c
6/3/2015 279

• c - gate output
– resistance, capacitance
increase delay
– Resistance & capacitance
"near" to output causes
additional delay
b
a
c
6/3/2015 280

Driving Large Loads
• Off-chip loads, long wires, etc. have high capacitance
• Increasing transistor size increases driving ability
(and speed), but in turn increases gate capacitance
• Solution: stages of progressively larger transistors
– Use nopt = ln(Cbig/Cg).
– Scale by a factor of a=e
6/3/2015 281

Summary: Static CMOS
• Advantages
– High Noise Margins (VOH=VDD, VOL=Gnd)
– No static power consumption (except for leakage)
– Comparable rise and fall times (with proper sizing)
– Robust and easy to use
• Disadvantages
– Large transistor counts (2N transistors for N inputs)
• Larger area
• More parasitic loading (2 transistor gates on each input)
– Pullup issues
• Lower driving capability of P transistors
• Series connections especially problematic
• Sizing helps, but increases loading on gate inputs
6/3/2015 282

Alternatives to Static CMOS
• Switch Logic
• nmos
• Pseudo-nmos
• Dynamic Logic
• Low-Power Gates
6/3/2015 283

Switch Logic
• Key idea: use transistors as switches
• Concern: switches are bidirectional
AND
A B
OR
6/3/2015 284

Switch Logic - Pass Transistors
• Use n-t a sisto as s it hes
• Th eshold p o le
– Transistor switches off when Vgs < Vt
– VDD input -> VDD-Vt output
• “pe ial gate eeded to esto e alues
IN:
VDD
A:
VDD
OUT:
VDD-Vtn
6/3/2015 285

Switch Logic - Transmission Gates
• Complementary transistors - n and p
• No threshold problem
• Cost: extra transistor, extra control input
• Not a perfect conductor!
A
A’
A
A’
6/3/2015 286

Switch Logic Example - 2-1 MUX
IN
6/3/2015 287

Charge Sharing
• Consider transmission gates in series
– Each node has parasitic capacitances
– Problems occur when inputs change to
redistribute charge
– Solution: design network so there is always a path
from VDD or Gnd to output
6/3/2015 288

Aside: Transmission Gates in Analog
• Transmission Gates
work with analog values, too!
• Example:
Voltage-Scaling D/A Converter
6/3/2015 289

NMOS Logic
• Used before CMOS was widely
available
• Uses only n transistors
– Normal n transistors in pull-
down network
– depletion-mode n transistor
(Vt < 0) used for pull-up
– "ratioed logic" required
• Tradeoffs:
– Simpler processing
– Smaller gates
– higher power!
– Additional design
considerations
for ratioed logic
Passive Pullup Device:
depletion Mode
n-transistor (Vt < 0)
OUT
Pulldown
Network
6/3/2015 290

Pseudo-nmos Logic
• Same idea, as nmos, but use p-
transistor for pullup
• "ratioed logic" required for
proper design (more about
this next)
• Tradeoffs:
– Fewer transistors -> smaller
gates, esp. for large number
of inputs
– less capacitative load on gates
that drive inputs
– larger power consumption
– less noise margin (VOL > 0)
– additional design
considerations due to ratioed
logic
Passive Pullup Device:
P-Transistor
OUT
Pulldown
Network
6/3/2015 291

6/3/2015 292
Rationed Logic for Pseudo-nmos
• Approach:
– Assume VOUT=VOL =0.25*VDD
– Assume 1 pulldown transistor is on
– Equate currents in p, n transistors
– Solve for ratio between sizes of p, n
transistors to get these conditions
– Further calculations necessary for
series connections
Idn  Ipn
1
2
k' n
Wn
Ln
Vgs,n  Vtn
 2

1
2
k' p
Wp
Lp
2 Vgs,p  Vtp
 Vds,p  Vds,p
2
  (EQ 3 21)
Wp
Lp
Wn
Ln
 3.9 (EQ 3 22)  Assu min g VDD  3.3V
Idp
OUT
Pulldown
Network
Idn

DCVS Logic
• DCVS - Differential
Cascode Voltage Switch
• Differential inputs, outputs
• Two pulldown networks
• Tradeoffs
– Lower capacitative loading
than static CMOS
– No ratioed logic needed
– Low static power
consumption
– More transistors
– More signals to route
between gates
OUT
Pulldown
Network
OUT’
OUT’
Pulldown
Network
OUT
A
B
C
A’
B’
C’
6/3/2015 293

Pulldown
Network
CS


A
B
C
Dynamic Logic
• Key idea: Two-step operation
– precharge - charge CS to logic high
– evaluate - conditionally discharge CS
• Control - precharge clock f
Storage Node
Storage
Capacitance
Precharge
Signal
Precharge Evaluate Precharge
6/3/2015 294

Domino Logic
• Key idea: dynamic gate + inverter
• Cascaded gates - o oto i all i easi g
Pulldown
Network
CS


B
C

in4
x1
x2
x3
6/3/2015 295

Domino Logic Tradeoffs
• Fewer transistors -> smaller gates
• Lower power consumption than pseudo-nmos
• Clocking required
• Logic not complete (AND, OR, but no NOT)
6/3/2015 296

More Techniques for Saving Power
• Reduce VDD (tradeoff: delay)
• Multiple Power Supplies
– High VDD fo fast logi
– Lo VDD fo slo logi
• Dealing with leakage currents
– Multiple-Threshold CMOS (MTCMOS)
– Variable-Threshold CMOS (VTCMOS)
6/3/2015 297

UNIT V
DATAPATH SUBSYSTEMS
Topics
• Sub system design,
• Shifters,
• Adders,
• ALUs,
• Multipliers,
• Parity generators,
• Comparators,
• Zero/One detectors,
• Counters.
6/3/2015 298

s & s Dete to s
• s dete to : N-input AND gate
• s dete to : NOTs + s dete to N-input
NOR)
299
A0
A1
A2
A3
A4
A5
A6
A7
allones A0
A1
A2
A3
allzeros
allones
A1
A2
A3
A4
A5
A6
A7
A0
6/3/2015

Comparators
• s dete to : A = …
• s dete to : A = …
• Equality comparator: A = B
• Magnitude comparator: A < B
300
6/3/2015

Equality Comparator
• Check if each bit is equal (XNOR, aka equality
gate)
• s dete t o it ise e ualit
301
A[0]
B[0]
A = B
A[1]
B[1]
A[2]
B[2]
A[3]
B[3]
6/3/2015

Magnitude Comparator
• Compute B – A and look at sign
• B – A = B + ~A + 1
• For unsigned numbers, carry out is sign bit
302
A0
B0
A1
B1
A2
B2
A3
B3
A = B
Z
C
A B

N A B

6/3/2015

Signed vs. Unsigned
• For signed numbers, comparison is harder
– C: carry out
– Z: zero (all bits of B – A are 0)
– N: negative (MSB of result)
– V: overflow (inputs had different signs, output sign
 B)
– S: N xor V (sign of result)
–
303
6/3/2015

Shifters
• Logical Shift:
– “hifts u e left o ight a d fills ith s
• 1011 LSR 1 = 0101 1011 LSL1 = 0110
• Arithmetic Shift:
– Shifts number left or right. Rt shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110
• Rotate:
– Shifts number left or right and fills with lost bits
• 1011 ROR1 = 1101 1011 ROL1 = 0111
304
6/3/2015

Adders
• Single-bit Addition
• Carry-Ripple Adder
• Carry-Skip Adder
• Carry-Look ahead Adder
• Carry-Select Adder
• Carry-Increment Adder
• Tree Adder
305
6/3/2015

Barrel Shifter
• Barrel shifters perform right rotations using
wrap-around wires.
• Left rotations are right rotations by N – k = k +
1 bits.
• Shifts are rotations with the end bits masked
off.
306
6/3/2015

Single-Bit Addition
• Half Adder Full Adder
307
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A B C Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Cout
out
S A B
C A B
 
 out ( , , )
S A B C
C MAJ A B C
  

6/3/2015

PGK
• For a full adder, define what happens to
carries
• (in terms of A and B)
– Generate: Cout = 1 independent of C
• G = A • B
– Propagate: Cout = C
• P = A  B
– Kill: Cout = 0 independent of C
• K = ~A • ~B
308
6/3/2015

Full Adder Design I
• Brute force implementation from eqns
309
out ( , , )
S A B C
C MAJ A B C
  

A
B
C
S
Cout
MAJ
A
B
C
A
B B
B
A
C
S
C
C
C
B B
B
A A
A B
C
B
A
C
B
A A B C
Cout
C
A
A
B
B
6/3/2015

Full Adder Design II
• Factor S in terms of Cout
• S = ABC + (A + B + C)(~Cout)
• Critical path is usually C to Cout in ripple
adder
•
310
S
S
Cout
A
B
C
Cout
MINORITY
6/3/2015

Layout
• Clever layout circumvents usual line of
diffusion
– Use wide transistors on critical path
– Eliminate output inverters
311
6/3/2015

Full Adder Design III
• Complementary Pass Transistor Logic (CPL)
– Slightly faster, but more area
312
A
C
S
S
B
B
C
C
C
B
B
Cout
Cout
C
C
C
C
B
B
B
B
B
B
B
B
A
A
A
6/3/2015

Full Adder Design IV
• Dual-rail domino
– Very fast, but large and power hungry
– Used in very fast multipliers
313
Cout
_h
A_h B_h
C_h
B_h
A_h

Cout
_l
A_l B_l
C_l
B_l
A_l

S_h
S_l
A_h
B_h B_h
B_l
A_l
C_l
C_h C_h

6/3/2015

Carry Propagate Adders
• N-bit adder called CPA
– Each sum bit depends on all previous carries
– How do we compute all these carries quickly?
314
+
BN...1
AN...1
SN...1
Cin
Cout
11111
1111
+0000
0000
Aguatda.com/cmx.p4...1
carries
Bguatda.com/cmx.p4...1
Sguatda.com/cmx.p4...1
Cin
Cout
00000
1111
+0000
1111
Cin
Cout
6/3/2015

Carry-Ripple Adder
• Simplest design: cascade full adders
– Critical path goes from Cin to Cout
– Design full adder to have fast carry delay
315
Cin
Cout
B1
A1
B2
A2
B3
A3
B4
A4
S1
S2
S3
S4
C1
C2
C3
6/3/2015

Inversions
• Critical path passes through majority gate
– Built from minority + inverter
– Eliminate inverter and use inverting full adder
316
Cout
Cin
B1
A1
B2
A2
B3
A3
B4
A4
S1
S2
S3
S4
C1
C2
C3
6/3/2015

Generate / Propagate
• Equations often factored into G and P
• Generate and propagate for groups spanning i:j
• Base case
• Sum:
317
: : : 1:
: : 1:
i j i k i k k j
i j i k k j
G G P G
P P P


 

:
:
i i i i i
i i i i i
G G A B
P P A B
 
  
0:00:00inGCP
0:00:00inGCP
0:0 0
0:0 0 0
in
G G C
P P
 
 
1:0
i i i
S P G 
 
6/3/2015

6/3/2015 318
PG Logic
S1
B1
A1
P1
G1
G0:0
S2
B2
P2
G2
G1:0
A2
S3
B3
A3
P3
G3
G2:0
S4
B4
P4
G4
G3:0
A4
Cin
G0
P0
1: Bitwise PG logic
2: Group PG logic
3: Sum logic
C0
C1
C2
C3
Cout
C4

6/3/2015 319
Carry-Ripple Revisited
:0 1:0
i i i i
G G P G 
 
S1
B1
A1
P1
G1
G0:0
S2
B2
P2
G2
G1:0
A2
S3
B3
A3
P3
G3
G2:0
S4
B4
P4
G4
G3:0
A4
Cin
G0
P0
C0
C1
C2
C3
Cout
C4

Carry-Skip Adder
• Carry-ripple is slow through all N stages
• Carry-skip allows carry to skip over groups of n
bits
– Decision based on n-bit propagate signal
320
Cin
+
S4:1
P4:1
A4:1
B4:1
+
S8:5
P8:5
A8:5
B8:5
+
S12:9
P12:9
A12:9
B12:9
+
S16:13
P16:13
A16:13
B16:13
Cout
C4
1
0
C8
1
0
C12
1
0
1
0
6/3/2015

Carry-Lookahead Adder
• Carry-lookahead adder computes Gi:0 for
many bits in parallel.
• Uses higher-valency cells with more than two
inputs.
321
Cin
+
S4:1
G4:1
P4:1
A4:1
B4:1
+
S8:5
G8:5
P8:5
A8:5
B8:5
+
S12:9
G12:9
P12:9
A12:9
B12:9
+
S16:13
G16:13
P16:13
A16:13
B16:13
C4
C8
C12
Cout
6/3/2015

Carry-Select Adder
• Trick for critical paths dependent on late input
X
– Precompute two possible outputs for X = 0, 1
– Select proper output when X arrives
• Carry-select adder precomputes n-bit sums
– For both possible carries into n-bit group
322
Cin
+
A4:1
B4:1
S4:1
C4
+
+
0
1
A8:5
B8:5
S8:5
C8
+
+
0
1
A12:9
B12:9
S12:9
C12
+
+
0
1
A16:13
B16:13
S16:13
Cout
0
1
0
1
0
1
6/3/2015

Tree Adder
• If lookahead is good, lookahead across
lookahead!
– Recursive lookahead gives O(log N) delay
• Many variations on tree adders
323
6/3/2015

Tree Adder Taxonomy
• Ideal N-bit tree adder would have
– L = log N logic levels
– Fanout never exceeding 2
– No more than one wiring track between levels
• Describe adder with 3-D taxonomy (l, f, t)
– Logic levels: L + l
– Fanout: 2f + 1
– Wiring tracks: 2t
• Known tree adders sit on plane defined by
• l + f + t = L-1
324
6/3/2015

6/3/2015 325
Summary
Architecture Classification Logic
Levels
Max
Fanout
Tracks Cells
Carry-Ripple N-1 1 1 N
Carry-Skip n=4 N/4 + 5 2 1 1.25N
Carry-Inc. n=4 N/4 + 2 4 1 2N
Brent-Kung (L-1, 0, 0) 2log2N – 1 2 1 2N
Sklansky (0, L-1, 0) log2N N/2 + 1 1 0.5 Nlog2N
Kogge-Stone (0, 0, L-1) log2N 2 N/2 Nlog2N
Adder architectures offer area / power / delay tradeoffs.
Choose the best one for your application.

Multi-input Adders
• Suppose we want to add k N-bit words
– Ex: 0001 + 0111 + 1101 + 0010 = 10111
• Straightforward solution: k-1 N-input CPAs
– Large and slow
326
+
+
0001 0111
+
1101 0010
10101
10111
1000
6/3/2015

Carry Save Addition
• A full adder sums 3 inputs and produces 2
outputs
– Carry output has twice weight of sum output
• N full adders in parallel are called carry save
adder
– Produce N sums and N carry outs
327
Z4
Y4
X4
S4
C4
Z3
Y3
X3
S3
C3
Z2
Y2
X2
S2
C2
Z1
Y1
X1
S1
C1
XN...1
YN...1
ZN...1
SN...1
CN...1
n-bit CSA
6/3/2015

CSA Application
• Use k-2 stages of CSAs
– Keep result in carry-save redundant form
• Final CPA computes actual result
328
4-bit CSA
5-bit CSA
0001 0111 1101 0010
+
1011
0101_
01010_ 00011
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
00011
01010_
X
Y
Z
S
C
01010_
+ 00011
10111
A
B
S
10111
6/3/2015

Multiplication
• Example:
• M x N-bit multiplication
– Produce N M-bit partial products
– Sum these to produce M+N-bit product
329
1100 : 1210
0101 : 510
1100
0000
1100
0000
00111100 : 6010
multiplier
multiplicand
partial
products
product
6/3/2015

General Form
• Multiplicand: Y = (yM-1, yM- , …, ,
• Multiplier: X = (xN-1, xN- , …, ,
• Product:
330
1 1 1 1
0 0 0 0
2 2 2
M N N M
j i i j
j i i j
j i i j
P y x x y
   

   
  
 
  
 
 
  
x0
y5
x0
y4
x0
y3
x0
y2
x0
y1
x0
y0
y5
y4
y3
y2
y1
y0
x5
x4
x3
x2
x1
x0
x1
y5
x1
y4
x1
y3
x1
y2
x1
y1
x1
y0
x2
y5
x2
y4
x2
y3
x2
y2
x2
y1
x2
y0
x3
y5
x3
y4
x3
y3
x3
y2
x3
y1
x3
y0
x4
y5
x4
y4
x4
y3
x4
y2
x4
y1
x4
y0
x5
y5
x5
y4
x5
y3
x5
y2
x5
y1
x5
y0
p0
p1
p2
p3
p4
p5
p6
p7
p8
p9
p10
p11
multiplier
multiplicand
partial
products
product
6/3/2015

Dot Diagram
• Each dot represents a bit
331
partial products
multiplier
x
x0
x15
6/3/2015

6/3/2015 332
Array Multiplier
y0
y1
y2
y3
x0
x1
x2
x3
p0
p1
p2
p3
p4
p5
p6
p7
B
A
Sin Cin
Sout
Cout
B
A
Cin
Cout
Sout
Sin
=
CSA
Array
CPA
critical path B
A
Sout
Cout Cin
Cout
Sout
=
Cin
B
A

Rectangular Array
• Squash array to fit rectangular floorplan
333
y0
y1
y2
y3
x0
x1
x2
x3
p0
p1
p2
p3
p4
p5
p6
p7
6/3/2015

Fewer Partial Products
• Array multiplier requires N partial products
• If we looked at groups of r bits, we could form
N/r partial products.
– Faster and smaller?
– Called radix-2r encoding
• Ex: r = 2: look at pairs of bits
– Form partial products of 0, Y, 2Y, 3Y
– First three are easy, but 3Y requires adder 
334
6/3/2015

Booth Encoding
• Instead of 3Y, try –Y, then increment next
partial product to add 4Y
• Similarly, for 2Y, try –2Y + 4Y in next partial
product
335
6/3/2015

Booth Hardware
• Booth encoder generates control lines for
each PP
– Booth selectors choose PP bits
336
6/3/2015

Advanced Multiplication
• Signed vs. unsigned inputs
• Higher radix Booth encoding
• Array vs. tree CSA networks
337
6/3/2015

Unit VI
Array Sub Systems
Topics:
SRAM
DRAM
ROM
Serial Access Memories
Content Addressable Memory
6/3/2015 338

339
Semiconductor Memory Types
Semiconductor Memories
Read/Write (R/W) Memory
or Random Access Memory (RAM) Read-Only Memory (ROM)
1. Mask (Fuse) ROM
2. Programmable ROM (PROM)
3. Flash Memory
4. Ferroelectric RAM (FRAM)
Erasable PROM (EPROM)
Electrically Erasable PROM (EEPROM)
Dynamic RAM
(DRAM)
Static RAM
(SRAM)

Semiconductor Memory Types (Cont.)
 Design Issues
» Area Efficiency of Memory Array:  of stored data bits per
unit area
» Memory Access Time: the time required to store and/or
retrieve a particular data bit.
» Static and Dynamic Power Consumption
• Requirements
» Easy reading
» Easy Writing
» High density
» Speed, more speed and still more speed
340

Memory Architecture
 Stores large number of bits
• m x n: m words of n bits each
• k = Log2(m) address input signals
• or m = 2k words
• e.g., 4,096 x 8 memory:
» 32,768 bits
» 12 address input signals
» 8 input/output data signals
 Memory access
• r/w: selects read or write
• enable: read or write only when asserted
• multiport: multiple accesses to different locations simultaneously
341
m × n memory
…
…
n bits per word
m
words
enabl
e
2k × n read and write
memory
A0
…
r/w
…
Q0
Qn-1
Ak-1
memory external view

 RAM: the stored data is volatile
• DRAM
» A capacitor to store data, and a transistor to access the
capacitor
» Need refresh operation
» Low cost, and high density  it is used for main memory
• SRAM
» Consists of a latch
» Don’t need the refresh operation
» High speed and low power consumption it is mainly used for
cache memory and memory in hand-held devices
342

RAM: “Random-access” memory
 Typically volatile memory
• bits are not held without power supply
 Read and written to easily by microprocessor
during execution
 Internal structure more complex than ROM
• a word consists of several memory cells, each storing 1 bit
• each input and output data line connects to each cell in its column
• rd/wr connected to every cell
• when row is enabled by decoder, each cell has logic that stores
input data bit when rd/wr indicates write or outputs stored bit when
rd/wr indicates read
343
enable
2k × n read and write
memory
A0
…
r/w
…
Q0
Qn-1
Ak-1
External view
4×4 RAM
2×4
decoder
Q0
Q3
A0
enable
A1
Q2 Q1
Memory
cell
I0
I3 I2 I1
rd/wr To every cell
Internal view

344
Memory Chip Configuration
Row
Dec
Memory Cell Array
Row Address
N bits
Complete Address
N+M Bits
2
M
Cells
Din
Dout
I/O Control
din
dout
Column Dec.
2
N
Cells
WL
DL
Cell
Control
Signals
I/O
Interface
Column Address
M Bits

Static Random Access Memory (SRAM)
• SRAM: The stored data can be retained indefinitely, without any
need for a periodic refresh operation.
345
• Complementary Column arrangement is to achieve a more
reliable SRAM operation
bit line C bit line C
VDD
load load
word line word line
1-bit SRAM cell

346
4T-SRAM(Resistive-Load SRAM Cell )
VDD
R R
word line word line
pass transistors to
activated by a row select
(RS) signal to enable
read/write operators
Basic cross-coupled 2-inverter
latch with 2 stable op points for
storing one-bit
SRAM cell is accessed via
two bit (column) lines C
and its complement for
reliable operation
undoped polysilicon resistor

347
6T-SRAM
VDD
word line word line
Full CMOS SRAM
Cell
VDD
word line word line
Depletion-Load
SRAM Cell

348
SRAM Operation Principles
• RS=0: The word line is not selected. M3 and M4 are OFF
• One data-bit is held: The latch preserves one of its two stable states.
• If RS=0 for all rows: CC and CC are charged up to near VDD by pulling up of
MP1 and MP2 (both in saturation)
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS
Pull-up transistor (one per column)

349
SRAM Operation Principles (Cont.)
• RS=1: The word line is now selected. M3 and M4 are ON
• Four Operations
• Write “1” Operation (V1=VOL, V2=VOH at t=0-):
• VC  VOL by the data-write circuitry. Therefore, V2  VOL, then M1 turn
off V1VOH and M2 turns on pulling down V2  VOL.
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

350
• Read “1” Operation (V1=VOH, V2=VOL at t=0-):
• VC retains pre-charge level, while VC  VOL by
M2 ON. Data-read circuitry detects small voltage
difference VC – VC > 0, and amplifies it as a “1”
data output.
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

351
• Write “0” Operation (V1=VOH, V2=VOL at t=0-):
• VC  VOL by the data-write circuitry.
• Since V1  VOL, M2 turns off, therefore V2  VOH.
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

• Read “0” Operation (V1=VOL, V2=VOH at t=0-):
• VC retains pre-charge level, while VC  VOL by M1 ON.
• Data-read circuitry detects small voltage difference VC – VC < 0, and
amplifies it as a “0” data output.
352
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

353
3. Write “0” Operation (V1=VOH, V2=VOL at t=0-
):
VC  VOL by the data-write circuitry.
Since V1  VOL, M2 turns off, therefore V2  VOH.
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

354
4. Read “0” Operation (V1=VOL, V2=VOH at t=0-
):
VC retains pre-charge level, while VC  VOL by M1 ON.
Data-read circuitry detects small voltage difference VC – VC < 0,
and amplifies it as a “0” data output.
VDD
R R
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS

355
Circuit of CMOS SRAM Cell
 Advantages
• Very low standby power consumption
• Large noise margins than R-load SRAMS
• Operate at lower supply voltages than R-load SRAMS
 Disadvantages
• Larger die area: To accommodate the n-well for pMOS transistors
and polysilicon contacts. The area has been reduced by using multi-
layer polysilicon and multi-layer metal processes
• CMOS more complex process
VDD
word line
VDD VDD
CC CC
M1 M2
M3 M4
MP1 MP2
V1 V2
VC VC
RS
M5 M6
(Column voltages can reach to full VDD)

356
Dynamic Read-Write Memory (DRAM) Circuits
• SRAM: 4~6 transistors per bit
4~5 lines connecting as charge on capacitor
• DRAM: Data bit is stored as charge on capacitor
Reduced die area
Require periodic refresh
M3 M4
WL
BL BL
M1 M2
parasitic storage
capacitances
Four-Transistor DRAM Cell

357
DRAM Circuits (Cont.)
M3
WL(read)
BL(write)
M1
M2
parasitic storage
capacitances
WL(write)
BL(read)
Three-Transistor DRAM Cell
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTn
X

358
3T-DRAM — Layout
BLR BLW GND
RWL
WWL
M3
M2
M1
Source: Digital Integrated Circuits 2nd

359
One-Transistor DRAM Cell
BL
M1 explicit storage
capacitances
WL
One-Transistor DRAM Cell
• Industry standard for high density dram arrays
• Smallest component count and silicon area per bit
• Separate or “explicit” capacitor (dual poly) per cell

360
Operation of Three-Transistor DRAM Cell
• The binary information is stored as the charge in C1
• Storage transistor M2 is on or off depending on the charge in C1
• Pass transistors M1 and M3: access switches
• Two separate bit lines for “data read” and “data write”
M2
RS
DATA
M1
M3
WS
MP1 MP2
VDD
C1
C2
Precharge devices
PC
C3
Data_in Data_out
C2, C3 >> C1(>10C1)

361
Operation of Three-Transistor DRAM Cell (Cont.)
• The operation is based on a two-phase non-overlapping clock scheme
» The precharge events are driven by 1, and the “read” and “write”
operations are driven by 2.
» Every “read” and “write” operation is preceded by a precharge
cycle, which is initiated with PC going high.
M2
RS
DATA
M1
M3
WS
MP1 MP2
VDD
C1
C2
Precharge devices
PC
C3
Data_in Data_out
PC
PC PC PC PC
write 1 read 1 write 0 read 0
WS
DATA
① 2 ③ 4 ⑤ 6 ⑦ 8
Din
Stored data
RS
Dout

362
• Write “1” OP: DATA = 0, WS = 1; RS = 0
» C2, C1 Share charge due to M1 ON
» Since C2 >> C1, the storage node C1 attains approximately the
same logic level.
MP1 MP2
VDD
C2
Precharge devices
PC
C3
Pre-charge Cycle
RS
M2
DATA
M1
M3
WS
C1
C2 C3
Data_in Data_out

363
• Read “1” OP: DATA = 0, WS = 0; RS = 1
» M2, M3 ON  C3, C1 discharges through M2 and M3, and the
falling column voltage is interpreted bt the “data read” circuitry
as a stored logic “1”.
RS
M2
DATA
M1
M3
WS
C1
C2 C3
Data_in Data_out

364
• Write “0” OP: DATA = 1, WS = 1; RS = 0
» M2, M3 ON  C2 and C1 discharge to 0 through M1 and data_in
nMOS.
RS
M2
DATA
M1
M3
WS
C1
C2 C3
Data_in
Data_out

365
• Read “0” OP: DATA = 1, WS = 0; RS = 1
» C3 does not discharge due to M2 OFF, and the logic-high level
on the Data_out column is interpreted by the data read circuitry
as a stored “0” bit.
RS
M2
DATA
M1
M3
WS
C1
C2 C3
Data_in Data_out

366
Operation of One-Transistor DRAM Cell
• Write “1” OP: BL = 1, WL = 1 (M1 ON)C1 charges to “1”
• Write “0” OP: BL = 0, WL = 1 (M1 ON)C1 discharges to “0”
• Read OP: destroys stored charge on C1  destructive refresh is
needed after every data read operation
BL
M1
WL
1-bit DRAM Cell
C1
C2
Column
capacitance
C2>>C1

RAM
 DRAM
WL
DL
SRAM
VDD
WL
WL
DL
DL
367

368
 ROM: 1, nonvolatile memories
2, only can access data, cannot to modify data
3, lower cost: used for permanent memory in printers,
fax, and game machines, and ID cards
• Mask ROM: data are written during chip fabrication by a photo mask
• PROM: data are written electrically after the chip is fabricated.
» Fuse ROM: data cannot be erased and modified.
» EPROM and EEPROM: data can be rewritten, but the number of
subsequent re-write operations is limited to 104-105.
• EPROM uses ultraviolet rays which can penetrate through the crystal
glass on package to erase whole data simultaneously.
• EEPROM uses high electrical voltage to erase data in 8 bit units.
• Flash Memory: similar to EEPROM

369
ROM: “Read-Only” Memory
 Nonvolatile
 Can be read from but not written to, by a
processor in an microcomputer system
 Traditionally written to, “programmed”,
before inserting to microcomputer system
 Uses
• Store software program for general-purpose
processor
• Store constant data (parameters) needed by system
• Implement combinational circuits (e.g., decoders)
2k × n ROM
…
Q0
Qn-1
A0
…
enable
Ak-1
External view

370
Example: 8 x 4 ROM
 Horizontal lines = words
 Vertical lines = data
 Lines connected only at circles
 Decoder sets word 2’s line to 1 if
address input is 010
 Data lines Q3 and Q1 are set to 1
because there is a “programmed”
connection with word 2’s line
 Word 2 is not connected with data
lines Q2 and Q0
 Output is 1010
8 × 4 ROM
3×8
decoder
Q0
Q3
A0
enabl
e
A2
word 0
word 1
A1
Q2 Q1
programm
able
connection
word
line
data
line
word 2
Internal view

Memory – ROM
 Nonvolatile Memory
- SRAM and DRAM and attractive due to their speed
- however, they are volatile which means when the power is removed, the data
is lost
- for a microcomputer, we need a nonvolatile storage device so that upon
power-up, the computer knows what to do.
- currently, the most popular semiconductor ROM is Flash (or EEprom)
- before looking at the details of a Flash transistor, let’s first look at the
different types of ROM arrays and addressing modes
371

Memory – ROM
 ROM Arrays
- There are two basic types of ROM arrays
1) NOR-based ROM
2) NAND-based ROM
NOR-based ROM
- All Column Lines are pulled-up using a PMOS transistor (or resistor)
- The Row Lines are connected to the gates of NMOS transistors at the intersection of
Row and Column Lines
- The presence or absence of the NMOS transistors dictates whether a 1 or a 0 is stored
- If the NMOS transistor is present, it will pull down the Column Line when its gate is
driven high by the Row Line
- If the NMOS transistor is absent, the Column Line will not be pulled down, so it will
remain pulled up by the PMOS’s
372

Memory – ROM
 NOR-based ROM
- In order to Read from the array, the Row line is asserted and the desired Column line is observed
- a NOR-based ROM is similar to a Hex Keypad
373

Memory – ROM
 NAND-based ROM
- NAND-based ROM is a different array architecture
- it uses a depletion-load NMOS as the pull-up transistor
- the Column NMOS’s are connected in series with the
column lines (i.e. a NAND configuration)
- If an NMOS exists in the Column line and the Row line
is asserted, the NMOS will pull the Column Line down
and represent a stored ’0’
- If an NMOS is absent on the Column line and the
Row line is asserted, the Column Line will remain
pulled high by the depletion NMOS and represent
a stored ‘1’
- since all of the NMOS’s are in series, in order to Read
from a Row, all other Rows much be turned ON
- this means in order to distinguish the Row we are asserting,
we write a ‘0’ to it
374

Memory – ROM
 NAND-based ROM
- In this configuration, if an NMOS is present, it will
represent a “stored 1” since in order to address its
location, the Row line is driven to a ‘0’ and the NMOS
not turned on. This leaves the Column line pulled HIGH
- if an NMOS is absent, it will represent a “stored 0”
since all of the other Row NMOS’s are turned on
and will pull the Column Line LOW
- this gives the opposite behavior as in a NOR-based ROM
NOR NAND
NMOS present 0 1
NMOS absent 1 0
- it also gives a complementary addressing scheme
NOR NAND
Address Row Line by driving: 1 0
All other Row Lines driven to: 0 1
375

376
Mask-programmed ROM
 Connections “programmed” at fabrication
• set of masks
 Lowest write ability
• only once
 Highest storage permanence
• bits never change unless damaged
 Typically used for final design of high-volume systems
• spread out NRE (non-recurrent engineering) cost for a low unit cost

377
OTP ROM: One-time programmable ROM
 Connections “programmed” after manufacture by user
• user provides file of desired contents of ROM
• file input to machine called ROM programmer
• each programmable connection is a fuse
• ROM programmer blows fuses where connections should not exist
 Very low write ability
• typically written only once and requires ROM programmer device
 Very high storage permanence
• bits don’t change unless reconnected to programmer and more fuses
blown
 Commonly used in final products
• cheaper, harder to inadvertently modify

378
.
(d)
(a)
(b)
source drain
+15V
source drain
0V
(c)
source drain
floating gate
5-30 min
EPROM: Erasable programmable ROM
 Programmable component is a MOS transistor
• Transistor has “floating” gate surrounded by an insulator
• (a) Negative charges form a channel between source and drain
storing a logic 1
• (b) Large positive voltage at gate causes negative charges to
move out of channel and get trapped in floating gate storing a
logic 0
• (c) (Erase) Shining UV rays on surface of floating-gate causes
negative charges to return to channel from floating gate restoring
the logic 1
• (d) An EPROM package showing quartz window through which
UV light can pass
 Better write ability
• can be erased and reprogrammed thousands of times
 Reduced storage permanence
• program lasts about 10 years but is susceptible to
radiation and electric noise
 Typically used during design development

381
EEPROM: Electrically erasable programmable
ROM
 Programmed and erased electronically
• typically by using higher than normal voltage
• can program and erase individual words
 Better write ability
• can be in-system programmable with built-in circuit to provide higher
than normal voltage
» built-in memory controller commonly used to hide details from memory user
• writes very slow due to erasing and programming
» “busy” pin indicates to processor EEPROM still writing
• can be erased and programmed tens of thousands of times
 Similar storage permanence to EPROM (about 10 years)
 Far more convenient than EPROMs, but more expensive

382
FLASH
 Extension of EEPROM
• Same floating gate principle
• Same write ability and storage permanence
 Fast erase
• Large blocks of memory erased at once, rather than one word at a time
• Blocks typically several thousand bytes large
 Writes to single words may be slower
• Entire block must be read, word updated, then entire block written back
 Used with embedded microcomputer systems storing large data
items in nonvolatile memory
• e.g., digital cameras, MP3, cell phones

Serial Access Memories
 Serial access memories do not use an address
 – Shift Registers
 – Serial In Parallel Out (SIPO)
 – Parallel In Serial Out (PISO)
 – Queues (FIFO, LIFO)
383

 FIFOs are commonly used in electronic circuits for buffering and flow
control which is from hardware to software.
 In its hardware form, a FIFO primarily consists of a set of read and write
pointers, storage and control logic.
 Storage may be SRAM, flip-flops, latches or any other suitable form of
storage. For FIFOs of non-trivial size, a dual-port SRAM is usually used,
where one port is dedicated to writing and the other to reading.
 A synchronous FIFO is a FIFO where the same clock is used for both
reading and writing. An asynchronous FIFO uses different clocks for
reading and writing.
 FIFO full/empty
 A hardware FIFO is used for synchronization purposes. It is often
implemented as a circular queue, and thus has two pointers:
 Read Pointer/Read Address Register
 Write Pointer/Write Address Register
388

What is CAM?
 Content Addressable Memory
is a special kind of memory!
 Read operation in traditional
memory:
 Input is address location of the content
that we are interested in it.
 Output is the content of that address.
 In CAM it is the reverse:
 Input is associated with something
stored in the memory.
 Output is location where the
associated content is stored.
1 0 1 X X
0 1 1 0 X
0 1 1 X X
1 0 0 1 1
0 1 1 0 1
0 0
0 1
1 0
1 1
0 1
Content Addressable
Memory
1 0 1 X X
0 1 1 0 X
0 1 1 X X
1 0 0 1 1
0 1
0 0
0 1
1 0
1 1
0 1 1 0 X
Traditional Memory
392

CAM for Routing Table Implementation
 CAM can be used as a search engine.
 We want to find matching contents in a database
or Table.
 Example Routing Table
Source: http://pagiamtzis.com/cam/camintro.html
393

Simplified CAM Block Diagram
 The input to the system is the search word.
 The search word is broadcast on the search lines.
 Match line indicates if there were a match btw. the search and stored word.
 Encoder specifies the match location.
 If multiple matches, a priority encoder selects the first match.
 Hit signal specifies if there is no match.
 The length of the search word is long ranging from 36 to 144 bits.
 Table size ranges: a few hundred to 32K.
 Address space : 7 to 15 bits.
Source: K. Pagiamtzis, A. Sheikholeslami,
“Content-Addressable Memory (CAM)
Circuits and Architectures:
A Tutorial and Survey,”
IEEE J. of Solid-state circuits. March 2006
394

CAM Memory Size
 Largest available
around 18 Mbit (single
chip).
 Rule of thumb: Largest
CAM chip is about half
the largest available
SRAM chip.
 A typical CAM cell consists
of two SRAM cells.
 Exponential growth rate
Source: K. Pagiamtzis, A. Sheikholeslami, “Content-Addressable
Memory (CAM) Circuits and Architectures: A Tutorial and
Survey,” IEEE J. of Solid-state circuits. March 2006
395

CAM Basics
 The search-data word is loaded
into the search-data register.
 All match-lines are pre-
charged to high (temporary
match state).
 Search line drivers broadcast
the search word onto the
differential search lines.
 Each CAM core compares its
stored bit against the bit on the
corresponding search-lines.
 Match words that have at least
one missing bit, discharge to
ground.
Source: K. Pagiamtzis, A. Sheikholeslami, “Content-Addressable
Memory (CAM) Circuits and Architectures: A Tutorial and
Survey,” IEEE J. of Solid-state circuits. March 2006
396

Type of CAMs
 Binary CAM (BCAM) only stores 0s and 1s
• Applications: MAC table consultation. Layer 2 security related
VPN segregation.
 Ternary CAM (TCAM) stores 0s, 1s and don’t
cares.
• Application: when we need wilds cards such as, layer 3 and 4
classification for QoS and CoS purposes. IP routing (longest prefix
matching).
 Available sizes: 1Mb, 2Mb, 4.7Mb, 9.4Mb, and
18.8Mb.
 CAM entries are structured as multiples of 36 bits
rather than 32 bits.
397

CAM Advantages
 They associate the input (comparand) with their memory contents in
one clock cycle.
 They are configurable in multiple formats of width and depth of search
data that allows searches to be conducted in parallel.
 CAM can be cascaded to increase the size of lookup tables that they
can store.
 We can add new entries into their table to learn what they don’t know
before.
 They are one of the appropriate solutions for higher speeds.
398

CAM Disadvantages
 They cost several hundred of dollars per CAM even in
large quantities.
 They occupy a relatively large footprint on a card.
 They consume excessive power.
 Generic system engineering problems:
• Interface with network processor.
• Simultaneous table update and looking up requests.
399

Unit VII
SEMICONDUCTOR INTEGRATED CIRCUIT
DESIGN
 Programmable
Logic Array (PLA)
 Programmable
Array Logic(PAL)
 FPGAs
 CPLDs
 Standard cells
 Design Approach
 Parameters influencing low power design
Programmable logic
devices (PLD)
400

PLD
Programmable logic is defined as a device with configurable
logic and flip-flops linked together with programmable
interconnect.
Why we are going for PLDs
 Problems by Using Basic Gates
 Many components on PCB:
• As no. of components rise, nodes interconnection complexity grow
exponentially
• Growth in interconnection will cause increase in interference, PCB size, PCB
design cost, and manufacturing time
402

PROGRAMMABLE LOGIC DEVICES (PLD)
PLD Hierarchical Architecture
405

PLD
 The purpose of a PLD device is to permit elaborate digital logic
designs to be implemented by the user in a single device.
 Can be erased electrically and reprogrammed with a new
design, making them very well suited for academic and
prototyping
 Types of Programmable Logic Devices
 SPLDs (Simple Programmable Logic Devices)
• ROM (Read-Only Memory)
• PLA (Programmable Logic Array)
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
 CPLD (Complex Programmable Logic Device)
 FPGA (Field-Programmable Gate Array)
406

General structure of PLDs.
407

PLD
 The first three varieties(ROM, PLA, PAL) are
quite similar to each other:
• They all have an input connection matrix, which
connects the inputs of the device to an array of AND-
gates.
• They all have an output connection matrix, which
connect the outputs of the AND-gates to the inputs of
OR-gates which drive the outputs of the device.
 The gate array is significantly different and will be
described later.
408

PLD
 The differences between the first three categories
are these:
• 1. In a ROM, the input connection matrix is hardwired.
The user can modify the output connection matrix.
• In a PAL/GAL the output connection matrix is
hardwired. The user can modify the input connection
matrix.
• In a PLA the user can modify both the input connection
matrix and the output connection matrix.
409

(a) Before programming. (b) After programming.
Programming by blowing fuses.
410

415
PLA
• A 3×2 PLA with 4 product terms.

JK FF implementation using PLA
416

418
Design for PLA:
Example
• Implement the following functions using PLA
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
1 = asserted in term
0 = negated in term
- = does not participate
Input Side:
1 = term connected to output
0 = no connection to output
Output Side:
Outputs
Inputs
Product
term
Reuse
of
terms
A
1
-
1
-
1
B
1
0
-
0
-
C
-
1
0
0
-
F0
0
0
0
1
1
F1
1
0
1
0
0
F2
1
0
0
1
0
F3
0
1
0
0
1
A B
B C
A C
B C
A

419
Example: Continued
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Personality Matrix
Outputs
Inputs
Product
term
Reuse
of
terms
A
1
-
1
-
1
B
1
0
-
0
-
C
-
1
0
0
-
F0
0
0
0
1
1
F1
1
0
1
0
0
F2
1
0
0
1
0
F3
0
1
0
0
1
A B
B C
A C
B C
A
A B C
F0 F1 F2 F3
AB
B’C
AC’
B’C’
A

420
BCD to Gray Code Converter
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'
Minimized Functions:
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
K-map for W
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
K-map for X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
K-map for Y
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
K-map for Z

421
4 product terms per each OR gate
A B C D
A
BD
BC
W X Y Z
BC’
B
C
BCD
AD’
BCD’
Product terms cannot be shared !
PLA achieves higher flexibility
at the cost of lower speed!

42
5
PALs
 Programmable Array Logic
• a fixed OR array.
Inputs
Dense arrayof
AND gates Product
terms
Dense arrayof
OR gates
Outputs

A simple four-input, three-output PAL device.
426

An example of using a PAL device to realize two
Boolean functions. (a) Karnaugh maps. (b) Realization.
427

428
PAL
W = ABC + CD
X = ABC + ACD + ACD + BCD
Y = ACD + ACD + ABD
x
x
x

FPGA AND CPLD
1. FPGA - Field-Programmable Gate Array.
2. CPLD - Complex Programmable Logic Device
3. FPGA and CPLD is an advance PLD.
4. Support thousands of gate where as PLD only
support hundreds of gates.
429

What is an FPGA?
 Before the advent of programmable logic, custom logic circuits were
built at the board level using standard components, or at the gate
level in expensive application-specific (custom) integrated circuits.
 FPGA is an integrated circuit that contains many (64 to over 10,000)
identical logic cells that can be viewed as standard components. Each
logic cell can independently take on any one of a limited set of
personalities.
 Individual cells are interconnected by a matrix of wires and
programmable switches. A user's design is implemented by
specifying the simple logic function for each cell and selectively
closing the switches in the interconnect matrix.
 Array of logic cells and interconnect form a fabric of basic building
blocks for logic circuits. Complex designs are created by combining
these basic blocks to create the desired circuit
430

What does a logic cell do?
 The logic cell architecture varies between different device families.
 Each logic cell combines a few binary inputs (typically between 3 and
10) to one or two outputs according to a Boolean logic function
specified in the user program .
 In most families, the user also has the option of registering the
combinatorial output of the cell, so that clocked logic can be easily
implemented.
 Cell's combinatorial logic may be physically implemented as a small
look-up table memory (LUT) or as a set of multiplexers and gates.
 LUT devices tend to be a bit more flexible and provide more inputs
per cell than multiplexer cells at the expense of propagation delay.
431

What does 'Field Programmable' mean?
 Field Programmable means that the FPGA's function is defined by a
user's program rather than by the manufacturer of the device.
 A typical integrated circuit performs a particular function defined at
the time of manufacture. In contrast, the FPGA's function is defined
by a program written by someone other than the device
manufacturer.
 Depending on the particular device, the program is either 'burned'
in permanently or semi-permanently as part of a board assembly
process, or is loaded from an external memory each time the device
is powered up.
 This user programmability gives the user access to complex
integrated designs without the high engineering costs associated with
application specific integrated circuits.
432

How are FPGA programs created?
 Individually defining the many switch connections and cell logic
functions would be a daunting task.
 This task is handled by special software. The software translates a
user's schematic diagrams or textual hardware description language
code then places and routes the translated design.
 Most of the software packages have hooks to allow the user to
influence implementation, placement and routing to obtain better
performance and utilization of the device.
 Libraries of more complex function macros (eg. adders) further
simplify the design process by providing common circuits that are
already optimized for speed or area.
433

FPGA
 FPGA applications:-
i. DSP
ii. Software-defined radio
iii. Aerospace
iv. Defense system
v. ASIC Prototyping
vi. Medical Imaging
vii. Computer vision
viii. Speech Recognition
ix. Cryptography
x. Bioinformatic
xi. And others.
434

Xilinx Spartan-3E Starter Kit
FPGA
switches
buttons LEDs
435

FPGA Principles
 A Field-Programmable Gate Array (FPGA) is an
integrated circuit that can be configured by the
user to emulate any digital circuit as long as there
are enough resources
 An FPGA can be seen as an array of Configurable
Logic Blocks (CLBs) connected through
programmable interconnect (Switch Boxes)
436

FPGA structure
CLB SB
SB SB
CLB
SB
CLB SB CLB
Configurable Logic Blocks
Interconnection Network
I/O Signals (Pins)
437

Simplified CLB Structure
CLB SB
SB SB
CLB
SB
CLB SB CLB
I/O Signals (Pins)
Look-Up
Table
(LUT)
Q
Q
SET
CLR
D
MUX
6/3/2015 438

Example: 4-input AND gate
A
B
C
D
O
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Q
Q
SET
CLR
D
MUX
A
B
C
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Configuration bits
O
0
6/3/2015 439

Example 2: Find the configuration
bits for the following circuit
Q
Q
SET
CLR
D
2-to-1
MUX
A0
A1
S
Clock
Q
Q
SET
CLR
D
MUX
A0
A1
S
Configuration bits
A0 A1 S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6/3/2015 440

CLB SB
SB SB
CLB
SB
CLB SB CLB
I/O Signals (Pins)
Configuration
bits 1
0
0
0
0
0
6/3/2015 441

Example 3
 Determine the configuration bits for the following circuit implementation in
a 2x2 FPGA, with I/O constraints as shown in the following figure.
Assume 2-input LUTs in each CLB.
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
Output
Input3
Q
Q
SET
CLR
D
Input1
Input2
Input3
Output
6/3/2015 442

CLBs required
Q
Q
SET
CLR
D
Input1
Input2
Input3
Output
CLB 1 CLB 2
Q
Q
SET
CLR
D
MUX
Input1
Input2
0
0
0
1
Configuration bits
O
1 Q
Q
SET
CLR
D
MUX
O
Input3
0
1
1
0
Configuration bits
Output
0
6/3/2015 443

Placement: Select CLBs
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
Output
Input3
444

Routing: Select path
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
Output
Input3
Configuration bits
SB1
1
0
0
0
0
0
Configuration bits
SB4
0
0
0
0
1
0
445

Configuration Bitstream
 The configuration bitstream must include ALL CLBs and
SBs, even unused ones
 CLB0: 00011
 CLB1: 01100
 CLB2: XXXXX
 CLB3: ?????
 SB0: 000000
 SB1: 000010
 SB2: 000000
 SB3: 000000
 SB4: 000001
446

FPGA Advantages
 Long time availability
 Can be updated and upgraded at your customer's
site
 Extremely short time to market
 Fast and efficient systems
 Performance gain for software applications
 Real time applications
 Massively parallel data processing
447

FPGA EDA Tools
 Must provide a design environment based on
digital design concepts and components (gates,
flip-flops, MUXs, etc.)
 Must hide the complexities of placement, routing
and bitstream generation from the user. Manual
placement, routing and bitstream generation is
infeasible for practical FPGA array sizes and
circuit complexities.
448

Silicon Wafers: Basic unit
• Silicon Wafers Basic processing unit
• 150, 200, 300 mm disk, 0.5 mm thick
• Newest ones 300 mm (12 inches)
• Typical process 25 - 1000 wafers/run
• Each wafer: 100 - 1000's of microchips (die)
• Wafer cost $10 - $100's
• 200 mm wafer weight 0.040 Kg
• Typical processing costs $1200/wafer (200
mm)
• Typical processed wafer value $11,000
(all products, modest yield)
• Value/Mass of processed wafer $275,000/Kg
451

CPLD
1. Complexity of CPLD is between FPGA and PLD.
2. CPLD featured in common PLD:-
i. Non-volatile configuration memory – does not need an external
configuration PROM.
ii. Routing constraints. Not for large and deeply layered logic.
3. CPLD featured in common FPGA:-
i. Large number of gates available.
ii. Can include complicated feedback path.
4. CPLD application:-
i. Address coding
ii. High performance control logic
iii. Complex finite state machines
452

CPLD
5. CPLD architecture:-
LAB – Logic Array Block / uses PALs
PIA – Programmable Interconnect Array
453

Using a PROM for logic design
(a) Truth table. (b) PROM realization.
455

Unit VIII
CMOS TESTING
• CMOS Testing
• Need for testing
• Test principles
• Design strategies for test
• Chip level test techniques
• System-level test techniques
• Layout design for improved testability
456

Need for Testing
 Testing is one of the most expensive parts of chips
• Logic verification accounts for > 50% of design effort for many
chips
• Debug time after fabrication has enormous opportunity cost
• Shipping defective parts can sink a company
 Example: Intel FDIV bug (1994)
• Logic error not caught until > 1M units shipped
• Recall cost $450M (!!!)
457

Logic Verification
 Does the chip simulate correctly?
• Usually done at HDL level
• Verification engineers write test bench for HDL
» Can’t test all cases
» Look for corner cases
» Try to break logic design
 Ex: 32-bit adder
• Test all combinations of corner cases as inputs:
» 0, 1, 2, 231-1, -1, -231, a few random numbers
 Good tests require ingenuity
458

Silicon Debug
 Test the first chips back from fabrication
• If you are lucky, they work the first time
• If not…
 Logic bugs vs. electrical failures
• Most chip failures are logic bugs from inadequate simulation
• Some are electrical failures
» Crosstalk
» Dynamic nodes: leakage, charge sharing
» Ratio failures
• A few are tool or methodology failures (e.g. DRC)
 Fix the bugs and fabricate a corrected chip
459

Manufacturing Test
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
• Must test chips after manufacturing before delivery to customers to
only ship good parts
 Manufacturing testers are
 very expensive
• Minimize time on tester
• Careful selection of
• test vectors
460

461
Manufacturing Failures
SEM images courtesy Intel Corporation

Stuck-At Faults
 How does a chip fail?
• Usually failures are shorts between two conductors or opens in a
conductor
• This can cause very complicated behavior
 A simpler model: Stuck-At
• Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted
to GND or VDD
• Not quite true, but works well in practice
462

Observability & Controllability
 Observability: ease of observing a node by
watching external output pins of the chip
 Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip
 Combinational logic is usually easy to observe and
control
 Finite state machines can be very difficult,
requiring many cycles to enter desired state
• Especially if state transition diagram is not known to the test
engineer
464

Test Pattern Generation
 Manufacturing test ideally would check every
node in the circuit to prove it is not stuck.
 Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.
 Good observability and controllability reduces
number of test vectors required for manufacturing
test.
• Reduces the cost of testing
• Motivates design-for-test
465

Test Example
» SA1 SA0
 A3 {0110} {1110}
 A2 {1010} {1110}
 A1 {0100} {0110}
 A0 {0110} {0111}
 n1 {1110} {0110}
 n2 {0110} {0100}
 n3 {0101} {0110}
 Y {0110} {1110}
 Minimum set: {0100, 0101, 0110, 0111, 1010,
466
A3
A2
A1
A0
Y
n1
n2 n3

Design for Test
 Design the chip to increase observability and
controllability
 If each register could be observed and controlled,
test problem reduces to testing combinational
logic between registers.
 Better yet, logic blocks could enter test mode
where they generate test patterns and report the
results automatically.
467

Scan
 Convert each flip-flop to a scan register
• Only costs one extra multiplexer
 Normal mode: flip-flops behave as usual
 Scan mode: flip-flops behave as shift register
 Contents of flops
 can be scanned
 out and new
 values scanned
 in
468
Flop
Q
D
CLK
SI
SCAN
scanout
scan-in
inputs outputs
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Logic
Cloud
Logic
Cloud

Scannable Flip-flops
0
1
Flop
CLK
D
SI
SCAN
Q
D




X
Q
Q




(a)
(b)
SCAN
SI
D


X
Q
Q




SI
s
s
(c)

d
d
d
s
SCAN
469

ATPG
 Test pattern generation is tedious
 Automatic Test Pattern Generation (ATPG) tools
produce a good set of vectors for each block of
combinational logic
 Scan chains are used to control and observe the
blocks
 Complete coverage requires a large number of
vectors, raising the cost of test
 Most products settle for covering 90+% of
potential stuck-at faults
470

Built-in Self-test
 Built-in self-test lets blocks test themselves
• Generate pseudo-random inputs to comb. logic
• Combine outputs into a syndrome
• With high probability, block is fault-free if it produces the
expected syndrome
471

PRSG
 Linear Feedback Shift Register
• Shift register with input taken from XOR of state
• Pseudo-Random Sequence Generator
472
Flop
Flop
Flop
Q[0] Q[1] Q[2]
CLK
D D D
Step Y
0 111
1 110
2 101
3 010
4 100
5 001
6 011
7 111 (repeats)
Flops reset to 111
Y

BILBO
 Built-in Logic Block Observer
• Combine scan with PRSG & signature analysis
473
MODE C[1] C[0]
Scan 0 0
Test 0 1
Reset 1 0
Normal 1 1
Flop
Flop
Flop
1
0
D[0] D[1] D[2]
Q[0]
Q[1]
Q[2] / SO
SI
C[1]
C[0]
PRSG
Logic
Cloud
Signature
Analyzer

Boundary Scan
 Testing boards is also difficult
• Need to verify solder joints are good
» Drive a pin to 0, then to 1
» Check that all connected pins get the values
 Through-hold boards used “bed of nails”
 SMT and BGA boards cannot easily contact pins
 Build capability of observing and controlling pins
into each chip to make board test easier
474

Boundary Scan Example
SerialData In
SerialData Out
PackageInterconnect
IOpad andBoundaryScan
Cell
CHIP A
CHIP B CHIP C
CHIP D
475

Boundary Scan Interface
 Boundary scan is accessed through five pins
• TCK: test clock
• TMS: test mode select
• TDI: test data in
• TDO: test data out
• TRST*: test reset (optional)
 Chips with internal scan chains can access the
chains through boundary scan for unified test
strategy.
476

Summary
 Think about testing from the beginning
• Simulate as you go
• Plan for test after fabrication
 “If you don’t test it, it won’t work! (Guaranteed)”
477

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