Vlsi.pptxbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
- 1. Subject: VLSI Design Automation (PE-EC802C) Topic: Physical Design: Floor Planning Group 9 Priyanshu Mandal 11500321079 Purnima Naskar 11500321080 Ritam Santra 11500321083 Sayantika Paul 11500321084
- 2. Introduction • Floor planning is a crucial step in VLSI physical design. • Determines optimal placement of functional blocks, macros, and standard cells. • Objectives: Minimize area, power consumption, and delay while ensuring routability.
- 3. Importance of Floor Planning in VLSI • Defines chip performance and manufacturability. • Determines wire length and routing congestion. • Ensures efficient power and clock distribution.
- 4. Inputs to Floor Planning • Netlist: Logical connectivity of the design. • Library: Standard cell and macro definitions. • Technology File: Constraints from fabrication technology. • Design Constraints: Timing, power, and area requirements.
- 5. Components of Floor Planning • Core Area: Region containing all logic components. • Macros (Hard IPs): Pre-designed blocks like RAM, PLLs, etc. • Standard Cells: Logic gates and flip-flops. • I/O Pads: Interfaces with external signals.
- 6. Floor Planning Steps Define chip size and aspect ratio. Macro placement to optimize connectivity. Power planning to ensure reliable power delivery. Standard cell placement in remaining space. Congestion analysis and optimization.
- 7. Types of Floor Planning
- 8. Macro Placement Strategies Place macros near I/O pads for efficient routing.. Align macros to minimize congestion and delays. Avoid creating routing blockages for standard cells.
- 9. Power Planning in Floor Planning • Power Rails and Rings: Distribute power across the chip. • Power Grids: Mesh structure to minimize IR drop. • Decoupling Capacitors: Reduce power noise.
- 10. Standard Cell Placement Cells are arranged in rows inside the core area. Optimized for timing, area, and routability. Utilization Factor: Balance between density and routing space.
- 11. Design Constraints in Floor Planning Area Utilization: Should be optimal (70–85%). Timing Closure: Meet delay constraints. Power Considerations: Avoid excessive IR drop and thermal issues. Manufacturability: Follow DFM (Design for Manufacturability) rules.
- 12. Optimization Techniques in Floor Planning • Hierarchical Design: Improves placement efficiency. • Blockage Insertion: Guides routing paths. • Iterative Refinement: Continuous analysis and improvements.
- 13. Conclusion • Floor planning is a critical step in VLSI design flow. • Good floor planning reduces area, improves timing, and optimizes power. • Ensures successful silicon implementation with minimal design iterations.
- 14. Thank You