Floorplan, Powerplan and Data Setup, Stages
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The document outlines the processes involved in floor planning and power planning for chip design, detailing objectives such as minimizing die size, meeting timing requirements, and ensuring proper power routing. It discusses the steps required for an effective floor plan, including macro placement, power grid creation, and the importance of reducing IR drop and ground bounce. Additionally, it provides insights into various design considerations, inputs needed, and checks for ensuring functional and efficient designs.
Floorplan, Powerplan and Data Setup, Stages
- 1. Floor Plan and Power Plan
- 2. Floorplan • Die size Estimation • Macro placement Guidelines • Measures to be taken to have good floorplan Powerplan • Creation of Power Grid • Robustness of Power grid • IR analysis 2 Agenda
- 3. FLOORPLAN & Data Setup 3
- 4. Objectives of floorplan Minimize the die size Meet the timing requirements Power routing should meet the IR/EM targets maximize the routability minimize the delays Decides the area for standard cell Routing complications are reduced by good floorplanning. 4
- 5. What is Floorplanning ? • Floorplanning is the process of deciding the die size, proper placement of the IO’s , macros (PLL , PHY etc. ) and memories and Power routing the design to meet the requirements of the specification. • Good floorplan would reduce the no. of iterations during the Design/Timing closure • Require lots of manual intervention during this stage. • This is the first step towards the Design of chip. 5
- 6. Place Macro & Memories Add halo Add Tap cells Create proper Blockages Able to Create proper power mesh Pin Placement Signal/Power Pad Placement 6 What to do to Create Floorplan
- 7. 7 Floorplan Inputs ● Netlist(.v) ● SDC(.sdc) ● Timing library(.lib) ● Physical library(.lef) ● Technology file(.tf)
- 8. 8 SANITY CHECKS Netlist Uniqueness Unconnected Nets Undriven nets Feedthrough Input Output No Input should be floating Remove assignment statements All are scan flip flop
- 9. 9 Check Timing Skew Multipath False path Input/Output delay Clock period Latency Uncertainity Check Library Lib - -> Timing/power/Operating condition Lef -- >Physical information of cell It will check missing library also
- 10. Read Gate Level Netlist Uniquifying Netlist Linking Reading Timing Constraint DATA PREPARATION 10
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- 12. Die Size Estimation - Factors Total Die Area comprises - • Core Area 1. Standard cell area – Total area of all modules in the design and area of all buffers added for timing fixes. 2. Memory area 3. Analog Macros area IO Area 1. Total no of Signal Pads 2. Total no of Power Pads Aspect Ratio • Aspect Ratio = Height/width • Decide the aspect ratio based on the available horizontal & vertical routing tracks. Utilization: Should be less than 70% 12
- 13. Design can become - 1. Core limited Design – The size of the chip is decided based on the size of the core region (logic). The number of pads are less, so that the pads can be placed around the core. 2. Pad Limited Design – Size of the chip is decided based on the No. of pads, because the core region is very small. The size of the die is decided based on the below factors – Core Limited/Pad Limited Die – Number of IO’s – Area of the standard cells – Macro area Die Size Estimation 13
- 14. Standard cells Memories Input / Output buffers 14
- 15. 15 Floor Planning Top Level View
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- 17. •Blockages can also be added in the floorplan to prohibit standards cells from being placed in those areas Floor plan 17
- 18. 18 Macro placement ➢ Macro should be place near to the boundary. ➢ Macro should be place according to their hierarchy ➢ Macro channel space should be proper ➢ Macro stacking should be limited ➢ Macro pins should be accessible ➢ Macro pins orientation should correct or towards the core ➢ Maximum space for the standard cell and routing
- 19. 19 Floorplan checks ● No floating pin should be there. ● There should be open connection. ● Channel should not narrow. ● Timing should be meet. ● Delay should be minimum.
- 21. • Flat Floorplan Design: • • It support optimization across functional boundaries resulting in smaller,faster • chips • • This design easily maps with todays flat place and route technologies • • It requires EDA tools to support high capacity • • Does not help scope with the complexity 21 Flat Design
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- 23. Power Planning
- 24. 1. To distribute the power from power pads to all elements of the chip. 2. Unified supply of power with less voltage drop. 3. A proper Power design should aim at using as less routing resources as possible. 4. Power Analysis checks (IR/EM) should be done after power planning is Completed 24 Objectives of Power Routing
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- 26. 26 Power Estimation ● Power estimation is based on total power consumed by the chip Power Estimation includes – Core Power Memory/Macro Power IO Power Core Power = Combinational logic Power + Sequential + Clock Power
- 27. 27 Power Plan Inputs ● Floorplan Netlist(.v) ● SDC(.sdc) ● LIB(.lib) ● LEF(.lef) ● TECH FILE(.tech) ● TLU(.tlu)
- 28. • Switching power • Power dissipated due to standard cell, pads and macros charging and discharging the • output load(interconnect+fanout loads) • Internal power • Power dissipated due to cell internal loads and short circuit current • Short circuit current , current flowing from Vdd to vss when both PMOS and NMOS are • completely/partially on • Leakage power • Due to leakage current in MOS • Designs can have as high as 40% leakage contributions 28 Types of power
- 29. 29 Power Planning • Power Planning includes proper estimation of power of chip and power routing the design based on the estimation. • In the power planning we create a mesh kind of structure. So that instance can take direct supply from the nearest cell • In the power planning we create multiple VDD and VSS lines
- 30. 1. To distribute the power from power pads/pins to all elements of the chip. 2. Uniformly distribute power with less voltage drop. 3. For meet IR/EM targets 4. Reducing delay 5. For meet timing requirement ➢ Sometime its happened that many instantaneous are switch from 0 to 1 at the same time, that time they required a huge amount of current so in this scenario this mesh kind of structure is very helpful Why create mesh kind of structure 30
- 31. Standard cells Memories Input / Output buffers 31 Std cell rows : the rows on which std cells are placed are called as std cell rows Std cells height is fixed for certain technology Power rails (sometimes called row straps or standard cell preroutes), straps, and trunks cross the entire die or sections of the die. The horizontal wires are often referred to as rails while the vertical wires are referred to as straps Tracks are defined for metal routing Rows are defined for std cell routing.
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- 33. 33 Power planning issues ● IR Drop ● Ground bounce ● EM violations
- 34. 34 IR Drop Reduction in voltage that occurs on power supply networks (VDD) IC design expects availability of ideal power supply In reality, localized voltage drops within the power grid Increasing current/area on die Narrower metal line widths (increases power grid resistance) Results in decreased power supply voltage at cells/transistors Decreases the operating voltage of the chip, resulting in timing and functional failures
- 35. 35 Ground Bounce Increase in voltage that occurs on ground networks (VSS or GND) in integrated circuits Increase in ground voltage decreases the operating voltage of the chip, resulting in timing and functional problems
- 36. 36 Em violations ● When metal density increase beyond the limit,the electrons starts move with high velocity and strikes from the atoms and atom release get more free.and this electrons and strike to the other atom.so mass flux is induced in oppsite direction of current. ● As a results metal get open/shots.
- 37. 37 Reasons of IR Drop ● Power structure is not proper. ● Cell density is very high. ● Instance are not get proper power because of no straps over there ● Mesh structure is proper but there is no via.
- 38. 38 How to reduce IR drop ● Routing should be from top layer. ● By adding some more power stripes ● By increasing the width of the metal. ● By adding Decaps. ● By using some low power techniques
- 39. 39 Reasons and Solution of EM violation • Reasons of EM violation :- Narrow metal width Metal slotting • Solution – By increase Metal width ● ●
- 40. 40 Power plan checks ● There should be no open connection ● All the macros should be hooked up. ● IR/EM target should be meet. ● Missing via should be taken care ● There should be no hot shots.
- 41. Wire Bonding And Flip Chip Wires and Solder Balls
- 42. IR drop In Wire Bond In Flip chip 42
- 43. 1.Tech File 2.TLU + 3.IO TDF file 4.Netlist 5.SDC 1.IO pads placed 2.Chip/core boundary 3.Cell rows, wire tracks created 4.Macro placement final Output place_opt clock_opt route_opt Chip finishing and DFM Power plan 1.Std cells placed 2.Clock tree(s) built 3.Clock and signal routing completed Output Floorplan 43 IC Compiler Data Flow DEF MW Design Planning
- 44. • www.asic_soc_blogs.in • www.vlsi-experts.com • www.cadence.com • www.synopsys.com 44 References
- 45. 45 Thank You Asha Lata DSG Group