1. MODULE 2
Floor planning and placement: Goals and objectives, Measurement of delay in
Floor planning, Floor planning tools, Channel definition, I/O and Power planning and
Clock planning.
Placement: Goals and Objectives, Min-cut Placement algorithm, Iterative
Placement Improvement,Time driven placement methods, Physical Design Flow.
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global
routing between blocks, Back annotation. Text Book 1
3. • Floorplanning is the art of any physical design. A well
and perfect floorplan leads to an ASIC design with
higher performance and optimum area.
• Floorplanning can be challenging in that, it deals with
the placement of I/O pads and macros as well as
power and ground structure.
• Before we are going for the floor planning to make
Floor planning
Inputs for floorplan:
• Netlist (.v)
• Technology file (techlef)
• Timing Library files (.lib)
• Physical library (.lef)
• Synopsys design constraints (.sdc)
• Tlu+
4. After physical design database creation using
imported netlist and corresponding library and
technology file, steps are
• Decide core width and height for die size
estimation.
• IO pad sites are created for placement of IO pad
placement.
• Placement of macros.
• The standard cell rows created for standard cell
placement.
• Power planning (pre routing)
• Adding physical only cells
• apart from this aspect ratio of the core,
utilization of core area, cell orientation, and core
to IO clearance are also taken care of during the
floorplan stages.
5. Goals :
• arrange the blocks on a chip,
• decide the location of the I/O pads,
• decide the location and number of the power pads,
• decide the type of power distribution, and
• decide the location and type of clock distribution.
Objectives of floorplanning :
• The objectives of floorplanning are to minimize the chip area and minimize delay.
Measuring area is straightforward, but measuring delay is more difficult
6. Measurement of Delay in Floorplanning
• Floorplanning is crucial for predicting performance in the ASIC design
process.Delay prediction is necessary before completing routing, based on
interconnect parasitics (capacitance & resistance).
• At the floorplanning stage, only the fanout (FO) of a net and block size are
known.Interconnect capacitance is estimated from past chip routing
statistics.Delay prediction is inaccurate due to unknown net routing shapes.
Wire-load tables predict interconnect capacitance based on fanout and block
size.Tools may use average or worst-case capacitance for estimationshows
• how we derive and use wire-load tables and illustrates the following facts:
7. Measurement of Delay in Floorplanning
• Predicted capacitance. (a) Interconnect lengths as a
function of fanout (FO) and circuit-block size. (b)
Wire- load table. There is only one capacitance
value for each fanout (typically the average value).
(c) The wire-load table predicts the capacitance and
delay of a net (with a considerable error). Net A and
net B both have a fanout of 1, both have the same
predicted net delay, but net B in fact has a much
greater delay than net A in the actual layout (of
8. Measurement of Delay in Floorplanning
• Fanout and Interconnect Statistics
• anout (FO) = 1: 60-70% of nets; distribution has a long tail.Twin-peaked distributions reflect
routing within and between blocks.Fanout > 1: More symmetrical and flatter distributions.
• Factors Affecting Wire-Load Tables
• Different block sizes impact predicted interconnect lengths.
• Aspect ratio of blocks and type of netlist synthesis affect delay prediction.
• E.g., logic delay optimization results in different netlists than minimum area optimization.
• Scaling and Interconnect Delay
• As feature sizes scale down, but chip size remains the same, the worst-case interconnect
delay increases.
• Example:A 0.25 µm process may have worse delay than a 0.35 µm process.
9. Floorplanning Tools:
• Figure a shows the Randomly
generated by floorplanning tools.
• Flexible blocks (A and C): Total area
is fixed but shape (aspect ratio) and
connector locations can be adjusted
during placement.
• Fixed blocks (RAM, ROM, compiled
cells): Dimensions and connectors
are only modified during creation.
10. Floorplanning Tools:
• Seeding in FloorplanningSeeding: Assigning specific logic cells to flexible blocks by name
using wildcards (e.g., ram_control*).
• Hard seed: Fixed placement not allowed to move.
• Soft seed: Initial suggestion, can be altered by the floorplanner a shows the Randomly
generated by floorplanning tools.
• Flexible blocks (A and C): Total area is fixed but shape (aspect ratio) and connector locations
can be adjusted during placement.
• Fixed blocks (RAM, ROM, compiled cells): Dimensions and connectors are only modified
during creation.
• Estimated placement: Determines connector positions at block boundaries.
11. Floorplanning Tools:
• The figure shows the congestion analysis and
routability.
• Visual display of channel congestion.
• Channel capacity: Maximum number of
interconnects a channel can handle.
• Channel density: Actual number of
interconnects needed.
• Congestion is the difference between density
and capacity.
• Dark areas on the map show regions with
12. Floorplanning Tools:
• Floorplan Optimization
• Adjust aspect ratio to match chip and
die cavity (e.g., from 2:1.5 to 1:1
aspect ratio).
• Resize flexible blocks to alleviate
congestion (Figure 16.7).
• Routing T-Junctions :T-junction routing: Critical for reducing congestion in two-level
metal routing.
• Route channel A (stem) before channel B (top) to avoid fixing the width of channel A
prematurely.
• Conclusion: Effective floorplanning reduces congestion and improves routability. Human
13. Channel Definition
and
Routing in ASIC Design :
Channel Definition: The process of
assigning areas between blocks for
interconnects.
Channel Ordering: Ensuring that
channels are routed in an appropriate
sequence.
• Importance of T-Junction Routing:
• Stem of the T (vertical) should
be routed first.
14. Slicing Floorplan and Routing
Slicing Process:
Sequential cuts divide a chip into circuit
blocks.
Cut without slicing through blocks
(Figure (a)).The slicing order defines the
hierarchy of blocks.
Routing Order: Reverse slicing order to
route T-junctions properly.
Example: Route channels in order of 4, 3,
15. Challenges in Non-Slicing
Floorplans
Cyclic Constraints: Floorplans with cyclic constraints hinder
channel routing (Figure a)).Entire channels must be routed
simultaneously.
Solutions:
Adjust the blocks to achieve a slicing structure.
Use L-shaped or switch-box based routing for complex
regions.
Figure illustrates possible issues and the inefficiency of
16. Removing Cyclic Constraints and Merging Blocks
Merging Blocks to Resolve Cyclic Constraints: Combining standard cell areas (e.g., A and C) can
remove cyclic constraints (Figure (a)).
Results in better routing efficiency.
Flattening the Netlist: Selectively flattening blocks can reduce routing complexity.
17. I/O and Power Planning
Pad-limited and core-limited die. (a) A pad-limited die.The number of pads determines the die size.
(b) A core-limited die:The core logic determines the die size.
(c) Using both pad-limited pads and core-limited pads for a square die.
18. Bonding pads. (a) This chip uses both pad-limited
and core-limited pads. (b) A hybrid corner pad. (c)
A chip with stagger-bonded pads. (d) An area-
bump bonded chip (or flip-chip). The chip is
turned upside down and solder bumps
connect the pads to the lead frame.
19. Gate-array I/O pads. (a) Cell-based ASICs may contain pad cells
of different sizes and widths. (b) A corner
of a gate-array base. (c) A gate-array base with different I/O cell
and pad pitches.
20. Power distribution. (a) Power distributed
using m1 for VSS and m2 for VDD. This
helps minimize the number
of vias and layer crossings needed but
causes problems in the routing channels.
(b) In this floorplan m1 is run parallel to
the longest side of all channels, the
channel spine. This can make automatic
routing easier but may increase the
number of
vias and layer crossings. (c) An expanded
view of part of a channel (interconnect is
shown as lines). If power runs on
different layers along the spine of a
channel, this forces signals to change
layers. (d) A closeup ofVDD andVSS buses
as
they cross. Changing layers requires a large
number of via contacts to reduce
resistance.
23. • Once the designer has floorplanned a chip and the logic cells within the
flexible blocks have been placed, it is time to make the connections by
routing the chip.
• This is still a hard problem that is made easier by dividing it into smaller
problems.
• Routing is usually split into global routing followed by detailed routing .
24. Global Routing
Goals :
• The goal of global routing is to provide complete instructions to the
detailed router on where to route every net.
Objectives of global routing :
• Minimize the total interconnect length.
• Maximize the probability that the detailed router can complete the
routing.
• Minimize the critical path delay.
• The input to the global router is a floorplan that includes the locations
of all the fixed and flexible blocks.
• The placement information for flexible blocks and the locations of all
the logic cells.
25. • Sequential global routing Perhaps the most straightforward strategy for
routing is to select a specific net order and then to route nets sequentially
in that order.
• However, this sequential approach often leads to a poor routing result,
because an earlier routed net might block the routing for its subsequent
nets. Therefore, the quality of the routing solution greatly depends on the
net ordering.
• Algorithms can be classified into sequential and concurrent approaches,
26. Sequential routing
•One of the approach for global routing picks up each
net in turn and calculates the shortest path using tree
algorithms also known as Sequential routing
•As this algorithm proceeds, some channels will become
more congested since they hold more nets than others.
•There are two different ways that a global router
handles this congestion problem.
1. Using order-independent and
2. Order-dependent routing.
27. Routing for different net orderings,
(a) One layer routing case with two two-pin nets 1 and 2,
(b) Net ordering of 1 followed by 2 and it is inferior solution,
(c) A better solution by net ordering 2 followed by 1.
28. There are some popular net-ordering schemes as follows:
(1) Order the nets in the ascending order according to the number of
pins within their bounding boxes.
(2) Order the nets in the ascending or descending order of their
lengths if routability is the most critical issue.
Research shows that routing shorter nets first often leads to better
routability.
(3) Order the nets on the basis of their timing criticality.
Other method hierarchical (top down and bottom up)
29. Concurrent routing
• The major drawback of the sequential approach is that it suffers from the
net ordering problem.
• In any net ordering scheme, it is more difficult to route the nets that are
processed later, because they are subjected to more blockages.
• Moreover, when the sequential routing does find a feasible solution, we do
not know whether or not this solution is optimal or how far it is from the
optimal solution.
• One popular concurrent approach is to formulate global routing as a 0-1
integer linear programming algorithm
30. Global Routing Between Blocks
Global routing for a cell-based ASIC formulated as a graph problem.
(a) A cell-based ASIC with numbered channels.
(b) The channels form the edges of a graph.
(c) The channel-intersection graph. Each channel corresponds to an edge on a
graph whose weight corresponds to the channel length.
31. Back-annotation
• Used in connection to netlist simulations and STA where the
propagation delay(s) through each cell in the netlist is overridden by
the delay value(s) specified in a special file called sdf (synopsys delay
format) file.
• The process of putting delays from a given source for the cells in a
netlist during netlist simulation is called Back Annotation.
• Normally the values of the delays corresponding to each cell in the
netlist would come from the simulation library
i.e verilogmodel of library cells.
• But those delays are not the actual delays of cells, as each of them is
instantiated in a netlist in different surroundings, different physical
locations, different loads, different fan in.
32. • The delay of two similar cells in the netlist at two different physical
locations in a chip can be significantly different depending upon above said
factors.
• Therefore in order to have actual delays for the cells in your netlist, an SDF
is written out, by a EDA tool can be a synthesis tool or a layout tool etc..
• which contains the delays of each instance of each library cell in the
netlist, under the circumstances the cell is in.
• During simulations or Static Timing Analysis, each cell in the netlist gets its
correponding delay read, or more technically 'annotated' from the SDF
file.
