vlsi report

GURGAON COLLEGE OF
ENGINEERING
INDUSTRIAL INTERNSHIP REPORT
Undertaken at

SSPL, DRDO
(Defense Research & Development Organization)
June 7th2011-july 31st 2011

ON THE TOPIC OF

“INTRODUCTION OF PHOTOLITHOGRAPHY AND
STUDY OF METALLIZATION IN GaAs”

Under the Supervisors: Submitted by:

Ms. Seema Vinayak Aayush Bhatnagar
Scientist F
(Electronics & Comm.Engg)
Mr. Robert Laishram 4nd Year
Scientist D 0803001

INTRODUCTION OF PHOTOLITHOGRAPHY
AND STUDY OF METALLIZATION IN GaAs
Submitted by: -

NAME :- AAYUSH BHATNAGAR

ROLL NO :- 0803001

In partial fulfillment of requirements for the award of the degree of

B.TECH (Electronics and communication),

GURGAON COLLEGE OF ENGINEERING

Summer training

JUNE 7th 2011-JULY 31ST 2011

Supervisors

Ms. Seema Vinayak Mr. Robert
Laishram

Scientist F Scientist D

Project undertaken at

Solid State Physics Laboratory(SSPL)

Defence Research and Development Organisation(DRDO)

Lucknow Road

Timarpur , Delhi - 110054

ACKNOWLEDGEMENT
I am deeply intended to Dr R Murlidharan, Director, Solid State Physics Laboratory, Lucknow
road, Delhi for providing me the opportunity to work on project ―INTRODUCTION OF
PHOTOLITHOGRAPHY AND STUDY OF METALLIZATION IN GaAs ― as part of my
B.TECH (Electronics and communication) curriculum.

My special thanks to Ms. SEEMA VINAYAK, Scientist (F), my in charge for her constant support
and guidance .I strongly record my deep sense of gratitude and thankfulness with utmost respect
to my project guide Mr. ROBERT LAISHRAM, Scientist (D), for providing me with valuable
information and help without which this project would not have been a success.

I am thankful to Mr. D.S. RAWAL , Scientist (F) ,Mr. A. NAYAK ,Scientist (F),Mr. and Mr.
RUPESH SIR ,SCIENTIST (D) and Ms. Henalika, Scientist (D) without their continuous
guidance and support; this project would not have been possible.

Again I shall be thankful to all the department members for providing me the
same opportunity.

ABSTRACT

This report basically deals with the fabrication of GaAs ,technique used for it and
metallization of GaAs.

First there is a brief idea about the MMIC ,what are they and why they are used, Difference
between two families of electronic devices.

Mid section of report deals with fabrication of GaAs , lithography and its types

Latter part contain metallization technique ,types of contacts and difference between different
techniques.

Table of content
 Introduction
 Chapter -1 DRDO
 SSPL
 Chapter -2 MMIC
 Fabrication of MMIC
 chapter- 3 Electronic devices (transistor) Family
 Difference Between BJT and FET
 differences
 chapter- 4 GaAs
 Comparison with silicon
 GaAs advantages
 Silicon advantages over GaAs
 CHAPTER-5 LITHOGRAPHY
 Photolithography

a) Wafer Cleaning, Barrier Formation and Photoresist
Application

b) Soft-Baking

c) Alignment

d) Mask Alignment and Exposure

1. Contact Printing
2. Proximity Printing
3. Projection Printing

e) Development

f) Hard-Baking

g) Etching

1. Wet etching
2. Plasma etching

 OVERALL PROCEDURE

 Photoresists
 Lift off
 Etching
 CHAPTER-5 Metallization

1) Ohmic contacts

2) Schottky Contact

 Techniques of metallization
 Physical vapor deposition
 Sputtering
 Conclusion
 Bibliography

INTRODUCTION

This basically deals with the GaAs as fabrication material of future ICs. The GaAs is profoundly
used in the various application of defense. GaAs has various advantages over silicon because of
these advantages it is preferred over silicon.

I have done my summer training in Solid State Physical Laboratory(SSPL) where I deal with the
fabrication of GaAs and its various process.

Some of the instrument I used in training includes Surface Profiler, Dektak , Curve Tracer,
Automatic Photolithography Machine etc.

Report is divided into 5 chapters :-

Chapter-1:DRDO

Chapter-2:MMIC

Chapter-3:Electronic devices (transistor) Family

Chapter-4:GaAs

Chapter-5:Lithogrophy

Chapter-6:Metallization

Chapter -1
DRDO
DRDO (Defence Research & Development Organization) was formed in 1958 from
the amalgamation of the then already functioning Technical Development
Establishment (TDEs) of the Indian Army and the Directorate of Technical
Development & Production (DTDP) with the Defence Science Organization (DSO).

DRDO was then a small organization with 10 establishments or laboratories. Over the years, it
has grown multi-directionally in terms of the variety of subject disciplines, number of
laboratories, achievements and stature.

Today, DRDO is a network of 51 laboratories which are deeply engaged in
developing defence technologies covering various disciplines, like aeronautics,
armaments, electronics, combat vehicles, engineering systems, instrumentation,
missiles, advanced computing and simulation, special materials, naval systems,
lifesciences,training, information systemsand agriculture.

Presently, the Organization is backed by over 5000 scientists and about 25,000 other scientific,
technical and supporting personnel.
Several major projects for the development of missiles, armaments, light combat aircrafts,
radars, electronic warfare systems etc are on hand and significant achievements have
already been made in several such technologies.

DRDO - Vision

Make India prosperous by establishing world class science and technology base and provide our
Defence Services decisive edge by equipping them with internationally competitive systems and
solutions.

DRDO - Mission
Design, develop and lead to production state-of-the-art sensors, weapon
systems, platforms and allied equipment for our Defence Services.
 rovide technological solutions to the Services to optimise combat
P
effectiveness and to promote well-being of the troops.
Develop infrastructure and committed quality manpower and build strong
indigenous technology base.

SSPL

Figure 1

Solid State Physics Laboratory (sspl), one of the establishments under the
DEFENCE RESEARCH AND DEVELOPMENT ORGANISATION (DRDO),
Ministry of Defence, was established in 1962 with the broad objective of
developing an R&D base in the field of Solid State Materials, Devices and Sub-
systems.

The Laboratory has a vision to be the centre of excellence in the development of
Solid State Materials, Devices and has a Mission to develop and characterize
high purity materials and solid state devices and to enhance infrastructure,
technology for meeting the futuristic challenges.

ACHIEVEMENTS

The Laboratory has contributed immensely on the growth of materials and
development of devices. Some of the achievements are:

SPST Switch
GaAs MMIC technology
Remotely activated acoustic warning system (RAAWS)
Silicon Photo diodes & Silicon Quadrant Detectors
GaAs Gunn Diodes for W-band applications
Thermo – Electric Coolers

AREAS OF WORK

Over the years, the Laboratory has developed core competence in the design and
development in the following areas:-

GaAs based Microwave devices and circuits
SAW devices & sensors
MEMs components
IR devices and Materials Development & Characterization

CHAPTER-2
MMIC
A Monolithic Microwave Integrated Circuit, or MMIC (sometimes pronounced
"mimic"), is a type of integrated circuit (IC) device that operates at microwave
frequencies (300 MHz to 300 GHz). These devices typically perform functions
such as microwave mixing, power amplification, low noise amplification, and
high frequency switching. Inputs and outputs on MMIC devices are frequently
matched to a characteristic impedance of 50 ohms. This makes them easier to use,
as cascading of MMICs does not then require an external matching network.
Additionally most microwave test equipment is designed to operate in a 50 ohm
environment.

MMICs are dimensionally small (from around 1 mm² to 10 mm²) and can be
mass produced, which has allowed the proliferation of high frequency devices
such as cellular phones. MMICs were originally fabricated using gallium arsenide
(GaAs), an III-V compound semiconductor. It has two fundamental advantages
over Silicon (Si), the traditional material for IC realization: device (transistor)
speed and a semi-insulating substrate. Both factors help with the design of high
frequency circuit functions. However, the speed of Si-based technologies has
gradually increased as transistor feature sizes have reduced and MMICs can now
also be fabricated in Si technology. The primary advantage of Si technology is its
lower fabrication cost compared with GaAs. GaAs has high speed, large
bandwidth, high saturated drift velocity, more radiation resistance, low noise.

Fabrication of MMIC
It includes following steps :-

Wafer processing
o Wet cleans
o Photolithography
o Ion implantation (in which dopants are embedded in the wafer
creating regions of increased (or decreased conductivity)
o Etching: dry and wet
o Thermal treatments : Rapid thermal anneal and Thermal oxidation
o vapour deposition :

a. physical and chemical
b. Molecular beam epitaxy (MBE)
c. Chemical-mechanical planarization (CMP)
d. Wafer testing (where the electrical performance is verified)

IC packaging

o Die attachment
o IC Bonding :

a. Wire bonding
b. Wafer bonding
c. Tab bonding

o IC encapsulation : Baking, Plating, Laser marking, Trim and form

IC testing

CHAPTER-3
Electronic devices (transistor) Family

Flowchart

Electronic
devices
(transistor)

Bipolar Unipolar

Heterojunction
Homojunction Homojunction Heterojunction
bipolar
(BJT) FET FET
transistor (HBT)

MESFET MOSFET HEMT

JFET HIGFET

Figure-2

Difference Between BJT and FET
BJT vs FET
Both BJT (Bipolar Junction Transistor) and FET (Field Effect Transistor) are two
types of transistors. Transistor is an electronic semiconductor device that gives a
largely changing electrical output signal for small changes in small input signals.
Due to this quality, the device can be used as either an amplifier or a switch.
Transistor was released in 1950s and it can be considered as one of the most
important invention in 20th century considering its contribution to the
development of IT. Different types of architectures for transistor have been
tested.

Bipolar Junction Transistor (BJT)
BJT is consists of two PN junctions (a junction made by connecting a p type
semiconductor and n type semiconductor). These two junctions are formed using
connecting three semiconductor pieces in the order of P-N-P or N-P-N. There for
two types of BJTs known as PNP and NPN are available.

Three electrodes are connected to these three semiconductor parts and middle lead
is called ‘base’. Other two junctions are ‘emitter’ and ‘collector’.

In BJT, large collector emitter (IC) current is controlled by the small base emitter
current (IB) and this property is exploited to design amplifiers or switches. There
for it can be considered as a current driven device. BJT is mostly used in amplifier
circuits.

Field Effect Transistor (FET)
FET is made of three terminals known as ‘Gate’, ‘Source’ and ‘Drain’. Here
drain current is controlled by the gate voltage. Therefore, FETs are voltage
controlled devices.

Depending on the type of semiconductor used for source and drain (in FET both
of them are made of the same semiconductor type), a FET can be an N channel
or P channel device. Source to drain current flow is controlled by adjusting the
channel width by applying an appropriate voltage to gate. There are also two
ways of controlling the channel width known as depletion and enhancement.
Therefore FETs are available in four different types such as N channel or P

channel with either in depletion or enhancement mode.

There are many types of FETs such as MOSFET (Metal Oxide Semiconductor
FET), HEMT (High Electron Mobility Transistor) and IGBT (Insulated Gate
Bipolar Transistor). CNTFET (Carbon Nanotube FET) which was resulted by
the development of nanotechnology is the latest member of FET family.

Differences
1. BJT is basically a current driven device, though FET is considered as a
voltage controlled device.

2. Terminals of BJT are known as emitter, collector and base, whereas FET is
made of gate, source and drain.

3. In most of the new applications, FETs are used than BJTs.

4. BJT uses both electrons and holes for conduction, whereas FET uses only one
of them and hence referred to as unipolar transistors.

5. FETs are power efficient than BJTs.

CHAPTER-4
GaAs

Gallium arsenide (GaAs) is a compound of the elements gallium and arsenic. It
is a III/Vsemiconductor, and is used in the manufacture of devices such as
microwave frequencyintegrated circuits, monolithic microwave integrated
circuits, infrared light-emitting diodes, laser diodes, solar cells, and optical

windows.
Figure-3

Comparison with silicon

GaAs advantages
1. It has a higher saturated electron velocity and higher electron mobility,
allowing transistors made from it to function at frequencies in excess of
250 GHz.
2. Unlike silicon junctions, GaAs devices are relatively insensitive to heat
due to their higher bandgap.
3. GaAs devices tend to have less noise than silicon devices especially at
high frequencies which is a result of higher carrier mobilities and lower
resistive device parasitics. These properties recommend GaAs circuitry
in mobile phones, satellite communications, microwave point-to-point
links, and higher frequency radarsystems. It is used in the manufacture of
Gunn diodes for generation of microwaves.
4. GaAs has a direct band gap, which means that it can be used to emit light
efficiently. Silicon has an indirect bandgap and so is very poor at
emitting light. Due to its lower bandgap though, Si LEDs can not emit

visible light and rather work in IR range while GaAs LEDs function in
visible red light.
5. As a wide direct band gap material and resulting resistance to radiation
damage, GaAs is an excellent material for space electronics and optical
windows in high power applications.Because of its wide bandgap, pure
GaAs is highly resistive.
6. Combined with the high dielectric constant, this property makes GaAs a
very good electrical substrate and unlike Si provides natural isolation
between devices and circuits. This has made it an ideal material for
microwave and millimeter wave integrated circuits, MMICs, where
active and essential passive components can readily be produced on a
single slice of GaAs.

Silicon advantages over GaAs
Silicon has three major advantages over GaAs for integrated circuit
manufacture.
1. silicon is abundant and cheap to process. Si is highly abundant in the
Earth's crust, in the form of silicate minerals. The economy of scale
available to the silicon industry has also reduced the adoption of GaAs.
2. a Si crystal has an extremely stable structure mechanically and it can be
grown to very large diameter boules and can be processed with very high
yields. It is also a decent thermal conductor thus enable very dense
packing of transistors, all very desirable for design and manufacturing of
very large ICs. Such good mechanical characteristics also make it a
suitable material for the rapidly developing field of nanoelectronics.
3. The major advantage of Si is the existence of silicon dioxide—one of the
best insulators. Silicon dioxide can easily be incorporated onto silicon
circuits, and such layers are adherent to the underlying Si. GaAs does not
easily form such a stable adherent insulating layer and does not have
stable oxide either.
4. The perhaps most important, advantage of silicon is that it possesses a
much higher hole mobility. This high mobility allows the fabrication of
higher-speed P-channel field effect transistors, which are required for
CMOS logic. Because they lack a fast CMOS structure, GaAs logic
circuits have much higher power consumption, which has made them
unable to compete with silicon logic circuits.

CHAPTER-5

LITHOGRAPHY
Lithography (from Greek λίθος - lithos, 'stone' + γράφειν - graphein, 'to write')
It is a general name given to processes used to transfer patterns on to a substrate
to define structures that make up devices.

Types of lithography:

(a) Photolithography (or optical lithography) uses UV radiation.

(b) X-ray lithography uses X-ray.

(c) Electron-beam lithography uses electron beam.
(d) ion beam lithography uses ion beam.

Photolithography
Photolithography is the process of transferring geometric shapes on a mask to
the surface of a silicon wafer. The steps involved in the photolithographic
process are wafer cleaning; barrier layer formation; photoresist application; soft
baking; mask alignment; exposure and development; and hard-baking.

a) Wafer Cleaning, Barrier Formation and Photoresist
Application
In the first step, the wafers are chemically cleaned to remove particulate matter
on the surface as well as any traces of organic, ionic, and metallic impurities.
After cleaning, silicon dioxide, which serves as a barrier layer, is deposited on
the surface of the wafer. After the formation of the SiO2 layer, photoresist is
applied to the surface of the wafer. High-speed centrifugal whirling of silicon
wafers is the standard method for applying photoresist coatings in IC
manufacturing. This technique, known as "Spin Coating," produces a thin
uniform layer of photoresist on the wafer surface.

Positive and Negative Photoresist
There are two types of photoresist: positive and negative. For positive resists,
the resist is exposed with UV light wherever the underlying material is to be
removed. In these resists, exposure to the UV light changes the chemical
structure of the resist so that it becomes more soluble in the developer. The
exposed resist is then washed away by the developer solution, leaving windows
of the bare underlying material. In other words, "whatever shows, goes." The
mask, therefore, contains an exact copy of the pattern which is to remain on the
wafer.

Negative resists behave in just the opposite manner. Exposure to the UV light
causes the negative resist to become polymerized, and more difficult to

dissolve. Therefore, the negative resist remains on the surface wherever it is
exposed, and the developer solution removes only the unexposed portions.
Masks used for negative photoresists, therefore, contain the inverse (or
photographic "negative") of the pattern to be transferred. The figure below
shows the pattern differences generated from tuseopositive and negative resist.
Negative resists were popular in the early history of integrated circuit
processing, but positive resist gradually became more widely used since they
offer better process controllability for small geometry features. Positive resists
are now the dominant type of resist used in VLSI fabrication processes.

Figure-5

b) Soft-Baking
Soft-baking is the step during which almost all of the solvents are removed from
the photoresist coating. Soft-baking plays a very critical role in photo-imaging.
The photoresist coatings become photosensitive, or imageable, only after
softbaking. Oversoft-baking will degrade the photosensitivity of resists by either
reducing the developer solubility or actually destroying a portion of the
sensitizer. Undersoft-baking will prevent light from reaching the sensitizer.
Positive resists are incompletely exposed if considerable solvent remains in the
coating. This undersoft-baked positive resists is then readily attacked by the
developer in both exposed and unexposed areas, causing less etching resistance.

c) Alignment
In order to make useful devices the patterns for different lithography steps that
belong to a single structure must be aligned to one another. The first pattern
transferred to a wafer usually includes a set of alignment marks, which are high
precision features that are used as the reference when positioning subsequent
patterns, to the first pattern (as shown in figure 4). Often alignment marks are

included in other patterns, as the original alignment marks may be obliterated as
processing progresses. It is important for each alignment mark on the wafer to
be labeled so it may be identified, and for each pattern to specify the alignment
mark (and the location thereof) to which it should be aligned. By providing the
location of the alignment mark it is easy for the operator to locate the correct
feature in a short time. Each pattern layer should have an alignment feature so
that it may be registered to the rest of the layers

Figure-6

d) Mask Alignment and Exposure
One of the most important steps in the photolithography process is mask
alignment. A mask or "photomask" is a square glass plate with a patterned
emulsion of metal film on one side. The mask is aligned with the wafer, so that
the pattern can be transferred onto the wafer surface. Each mask after the first
one must be aligned to the previous pattern.

Once the mask has been accurately aligned with the pattern on the wafer's
surface, the photoresist is exposed through the pattern on the mask with a high
intensity ultraviolet light. There are three primary exposure methods: contact,
proximity, and projection. They are shown in the figure below.

Contact Printing

In contact printing, the resist-coated silicon wafer is brought into physical
contact with the glass photomask. The wafer is held on a vacuum chuck, and the

whole assembly rises until the wafer and mask contact each other. The
photoresist is exposed with UV light while the wafer is in contact position with
the mask. Because of the contact between the resist and mask, very high
resolution is possible in contact printing (e.g. 1-micron features in 0.5 microns
of positive resist). The problem with contact printing is that debris, trapped
between the resist and the mask, can damage the mask and cause defects in the
pattern.

Proximity Printing

The proximity exposure method is similar to contact printing except that a small
gap, 10 to 25 microns wide, is maintained between the wafer and the mask
during exposure. This gap minimizes (but may not eliminate) mask damage.
Approximately 2- to 4-micron resolution is possible with proximity printing.

Projection Printing

Projection printing, avoids mask damage entirely. An image of the patterns on
the mask is projected onto the resist-coated wafer, which is many centimeters
away. In order to achieve high resolution, only a small portion of the mask is
imaged. This small image field is scanned or stepped over the surface of the
wafer. Projection printers that step the mask image over the wafer surface are
called step-and-repeat systems. Step-and-repeat projection printers are capable
of approximately 1-micron resolution.

e) Development:
One of the last steps in the photolithographic process is development. The
figure below shows response curves for negative and positive resist after
exposure and development.

At low-exposure energies, the negative resist remains completely soluble in the
developer solution. As the exposure is increased above a threshold energy Et,
more of the resist film remains after development. At exposures two or three
times the threshold energy, very little of the resist film is dissolved. For positive
resists, the resist solubility in its developer is finite even at zero-exposure
energy. The solubility gradually increases until, at some threshold, it becomes
completely soluble. These curves are affected by all the resist processing
variables: initial resist thickness, prebake conditions, developer chemistry,
developing time, and others.

f) Hard-Baking
Hard-baking is the final step in the photolithographic process. This step is
necessary in order to harden the photoresist and improve adhesion of the
photoresist to the wafer surface.

g) Etching
In etching, a liquid ("wet") or plasma ("dry") chemical agent removes the
uppermost layer of the substrate in the areas that are not protected by
photoresist.

In semiconductor fabrication, dry etching techniques are generally used, as they
can be made anisotropic, in order to avoid significant undercutting of the
photoresist pattern. This is essential when the width of the features to be defined
is similar to or less than the thickness of the material being etched (i.e. when the
aspect ratio approaches unity).

Etching is a critically important process module, and every wafer undergoes
many etching steps before it is complete. For many etch steps, part of the wafer
is protected from the etchant by a "masking" material which resists etching. In
some cases, the masking material is a photoresist which has been patterned
using photolithography.

The two fundamental types of etchants are:-

(1) liquid-phase ("wet") and
(2) plasma-phase ("dry").

Wet etching

The first etching processes used liquid-phase ("wet") etchants. The wafer can be
immersed in a bath of etchant, which must be agitated to achieve good process
control. Wet etchants are usually isotropic, which is often indispensable for
microelectromechanical systems, where suspended structures must be
"released" from the underlying layer. They also require the disposal of large
amounts of toxic waste.

Plasma etching

Modern VLSI processes avoid wet etching, and use plasma etching instead.
Plasma etching can be isotropic, i.e., exhibiting a lateral undercut rate on a
patterned surface approximately the same as its downward etch rate, or can be
anisotropic, i.e, exhibiting a smaller lateral undercut rate than its downward etch
rate. Such anisotropy is maximized in deep reactive ion etching.

Plasma etching is a form of plasma processing used to fabricate integrated
circuits. It involves a high-speed stream of glow discharge (plasma) of an
appropriate gas mixture being shot (in pulses) at a sample. It is based on
physical bombardment with ions or atoms.

Plasma is used to energize a chemically inert projectile so that it moves at
high velocity when it strikes the substrate. Momentum is transferred during the
collision. Substrate atoms are dislodged if projectile energy exceeds bonding
energy. This process is very similar to ion implantation, but low-energy ions are
used to avoid implantation damage. Argon is the most commonly used ion
source.

Photoresists
Photoresists are classified into two groups: positive resists and negative resists.

A positive resist is a type of photoresist in which the portion of the
photoresist that is exposed to light becomes soluble to the photoresist
developer. The portion of the photoresist that is unexposed remains
insoluble to the photoresist developer.

A negative resist is a type of photoresist in which the portion of the
photoresist that is exposed to light becomes insoluble to the photoresist
developer. The unexposed portion of the photoresist is dissolved by the
photoresist developer.

Differences between tone types

Characteristic Positive Negative

Adhesion to Silicon Fair Excellent

Relative Cost More Expensive Less Expensive

Developer Base Aqueous Organic

Minimum Feature 0.5 μm and below ± 2 μm

Step Coverage Better Lower

Wet Chemical Resistance Fair Excellent

Lift off

Lift-off process in microstructuring technology is a method of creating
structures (patterning) of a target material on the surface of a substrate (ex.
wafer) using a sacrificial material. It is an additive technique as opposed to
more traditional subtracting technique like etching.

An inverse pattern is first created in the sacrificial stencil layer (ex. photoresist),
deposited on the surface of the substrate. This is done by etching openings
through the layer so that the target material can reach the surface of the
substrate in those regions, where the final pattern is to be created. The target
material is deposited over the whole area of the wafer, reaching the surface of
the substrate in the etched regions and staying on the top of the sacrificial layer
in the regions, where it was not previously etched. When the sacrificial layer is
washed away (photoresist in a solvent), the material on the top is lifted-off and
washed together with the sacrificial layer below.

After the lift-off, the target material remains only in the regions where it had a
direct contact with the substrate.

Etching

The process of etching is to remove the semiconductor layer that is left
exposed by developing process. Control parameters for etching are time,
uniformity, temperature and concentration of each species and these should be
taken into account. Etchants should be used at particular temperature specified
for them. Care should taken ensure that only clean and dry wafer enter for
etching. During etching complete removal of the development resist should be
taken to ensure as any residue left on the semi-conducting layer may inhibit
etching action. During etching, movement or rotation should be such that they
enhance the uniformity of phenomenon.
wet etching
For isotropic wet etching, a mixture of hydrofluoric acid, nitric acid, and acetic
acid (HNA) is the most common etchant solvent for silicon. The concentrations
of each etchant determines the etch rate. Silicon dioxide or silicon nitride is
usually used as a masking material against HNA. As the reaction takes place,
the material is removed laterally at a rate similar to the speed of etching
downward. This lateral and downward etching process takes places even with
isotropic dry etching which is described in the dry etch section. Wet chemical
etching is generally isotropic even though a mask is present since the liquid
etchant can penetrate underneath the mask (Figure 2b). If directionality is very
important for high-resolution pattern transfer, wet chemical etching is normally
not used.

Dry etching
Synonyms: plasma etching, gas etching, physical dry etching, chemical
dry etching, physical-chemical etching

Definition:
In dry etching, plasmas or etchant gasses remove the substrate
material. The reaction that takes place can be done utilizing high
kinetic energy of particle beams, chemical reaction or a
combination of both.

Physical dry etching:
Physical dry etching requires high energy kinetic energy (ion, electron, or
photon) beams to etch off the substrate atoms. When the high energy particles
knock out the atoms from the substrate surface, the material evaporates after
leaving the substrate. There is no chemical reaction taking place and therefore
only the material that is unmasked will be removed. The physical reaction
taking place is illustrated in Figure 3.

Chemical dry etching:
Chemical dry etching (also called vapor phase etching) does not use liquid
chemicals or etchants. This process involves a chemical reaction between
etchant gases to attack the silicon surface.
The chemical dry etching process is usually isotropic and exhibits high
selectively. Anisotropic dry etching has the ability to etch with finer resolution
and higher aspect ratio than isotropic
etching. Due to the directional nature of dry etching, undercutting can be
avoided. shows a rendition of the reaction that takes place in chemical dry
etching. Some of the ions that are used in chemical dry etching is
tetrafluoromethane (CH4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3),
chlorine gas (Cl2), or fluorine (F2).[3]

Reactive Ion Etching:
Reactive ion etching (RIE) uses both physical and chemical mechanisms to
achieve high levels of resolution. The process is one of the most diverse and
most widely used processes in industry and research. Since the process
combines both physical and chemical interactions, the process is much faster.
The high energy collision from the ionization helps to dissociate the etchant
molecules into more reactive species.

In the RIE-process, cations are produced from reactive gases which are
accelerated with high energy to the substrate and chemically react with the
silicon. The typical RIE gasses for Si are CF4, SF6 and BCl2 + Cl2. As seen in
Figure 5, both physical and chemical reaction is taking place. Figure 6 depicts
some micro/nano structures with high aspect ration etched using RIE

CHAPTER-5
Metallization
1) Ohmic contacts

A metal-semiconductor junction results in an Ohmic contact (i.e. a contact with
voltage independent resistance) if the Schottky barrier height, B, is zero or
negative. In such case, the carriers are free to flow in or out of the
semiconductor so that there is a minimal resistance across the contact. For an n-
type semiconductor, this means that the workfunction of the metal must be close
to or smaller than the electron affinity of the semiconductor. For a p-type
semiconductor, it requires that the workfunction of the metal must be close to or
larger than the sum of the electron affinity and the bandgap energy. Since the
workfunction of most metals is less than 5 V and a typical electron affinity is
about 4 V, it can be problematic to find a metal that provides an Ohmic contact
to p-type semiconductors with a large bandgap such as GaN or SiC.

2) Schottky Contact
A Schottky barrier refers to a metal-semiconductor contact having a large
barrier height (i.e. and low doping concentration that is less than the
density of states in the conduction band or valence band. The potential barrier
between the metal and the semiconductor can be identified on an energy band
diagram. To construct such a diagram we first consider the energy band diagram
of the metal and the semiconductor, and align them using the same vacuum
level as shown in Fig. 3.2 (a). As the metal and semiconductor are brought
together, the Fermi energies of the two materials must be equal at thermal
equilibrium Fig. 3.2 (b).

The barrier height is defined as the potential difference between the Fermi
energy of the metal and the band edge where the majority carrier reside.
From Fig. 3.2 one finds that for n-type semiconductors the barrier height is
obtained from

Techniques of metallization

Physical vapor deposition
Physical vapor deposition (PVD) is a variety of vacuum deposition and is a
general term used to describe any of a variety of methods to deposit thin
films by the condensation of a vaporized form of the material onto various
surfaces (e.g., onto semiconductor wafers). The coating method involves purely
physical processes such as high temperature vacuum evaporation or plasma
sputter bombardment rather than involving a chemical reaction at the surface to
be coated as inchemical vapor deposition. The term physical vapor deposition
appears originally in the 1966 bookVapor Deposition by CF Powell, JH Oxley
and JM Blocher Jr, but Michael Faraday was using PVD to deposit coatings as
far back as 1838.
Variants of PVD include, in order of increasing novelty:

 Cathodic Arc Deposition: In which a high power arc discharged at the target
material blasts away some into highly ionized vapor.
 Electron beam physical vapor deposition: In which the material to be
deposited is heated to a high vapor pressure by electron bombardment in
"high" vacuum.
 Evaporative deposition: In which the material to be deposited is heated to a
high vapor pressure by electrically resistive heating in "low" vacuum.
 Pulsed laser deposition: In which a high power laser ablates material from
the target into a vapor.
 Sputter deposition: In which a glow plasma discharge (usually localized
around the "target" by a magnet) bombards the material sputtering some
away as a vapor. Here is an animation of a generic PVD sputter tool: PVD
Animation
PVD is used in the manufacture of items including semiconductor
devices, aluminized PET film for balloons and snack bags, and coated cutting
tools for metalworking. Besides PVD tools for fabrication special smaller tools
mainly for scientific purposes have been developed. They mainly serve the
purpose of extreme thin films like atomic layers and are used mostly for small
substrates. A good example are mini e-beam evaporators which can deposit
monolayers of virtually all materials with melting points up to 3500°C.

sputtering

Sputter deposition is a physical vapor deposition process for depositing
thin films, sputtering means ejecting material from a target and depositing it on
a substrate such as a silicon wafer.

The target is the source material. Substrates are placed in a vacuum chamber
and are pumped down to a prescribed process pressure. Sputtering starts when a
negative charge is applied to the target material causing a plasma or glow
discharge. Positive charged gas ions generated in the plasma region are
attracted to the negatively biased target plate at a very high speed. This collision
creates a momentum transfer and ejects atomic size particles form the target.
These particles are deposited as a thin film into the surface of the substrates.

Sputtering is extensively used in the semiconductor industry to deposit thin
films of various materials in integrated circuits processing. Thin anti
reflection coatings on glass, which are useful for optical applications are also
deposited by sputtering. Because of the low substrate temperatures used,
sputtering is an ideal method to deposit contact metals for thin- film transistors.
This technique is also used to fabricate thin film sensors, photovoltaic thin films
(solar cells), metal cantilevers and interconnects etc.

sputtering can be done either in DC or RF modes. DC
sputtering is done with conducting materials. If the target is a non conducting
material the positive charge will build up on the material and it will stop
sputtering. RF sputtering can be done both conducting and non conducting
materials. Here, magnets are used to increase the percentage of electrons that
take part in ionization of events and thereby increase the probability of electrons
striking the Argon atoms, increase the length of the electron path, and hence
increase the ionization efficiency significantly.

sputtering can be done in either DC or RF modes

DC sputtering:
DC sputtering is done with conducting materials.
If target is non-conducting material, the positive charge will built up on
target material and stops sputtering

RF sputtering:
Both conducting and non-conducting materials can be sputtered.
Higher sputter rate at lower pressure.

Advantages of vacuum deposition:

Reducing the particle density so that the mean free path for collision is
long.

Reducing the contaminants

Low pressure plasma environment

Comparision of Thermal Evaporation and Sputtering:

Evaporation Sputtering

Low energy atoms High energy atoms

High vacuum path Low vacuum path

Few collision Many collision

Larger grain size Smaller grain size

Poorer adhesion Better adhesion

CONCLUSION

The industrial training at DEFENCE RESEARCH AND DEVELOPMENT
ORGANISATION (DRDO), Delhi has given me an exposure to the activities
at a large public sector – undertaking unit . This being a large organization deals
with wide spectrum of technologies . The exposure on LITHOGRAPHY has
given me great confidence and knowledge.

BIBLIOGRAPHY

Books Referred
a) Vlsi Technology By S.M.SZE
b) Vlsi Fabrication Principles by Ralph Williams

Web Section
a) www.google.com
b) www.wikipedia.com
c) www.pdf.com
d) http://www.ece.gatech.edu/research/labs/vc/theory/PosNegRes.html
e) http://dspace.library.iitb.ac.in

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