Microprocessor Architecture 4
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The document provides an overview of interrupts in microprocessor architecture, specifically focusing on the 8085 microprocessor. It describes two types of interrupts: hardware and software, detailing their generation and functions. Additionally, it explains different types of interrupts, their priorities, and associated instructions for enabling and disabling them.
Microprocessor Architecture 4
- 2. What is an Interrupt? • An interrupt is a signal, when applied ,the CPU suspends its normal course of executions and the control will go to a program called ISR(Interrupt Service Sub routine ). • After executing this subroutine program, the control will come back to the next instruction where it has suspended before the interrupt call. • After returning from the ISR the CPU will continue its normal execution process.
- 3. contd • This interrupt signal can be either external to the microprocessor or an internal instruction. • Based on this the interrupts are divided into two types. One is the hardware interrupt and the other is the software interrupt. • A hardware interrupt is generated when the signal at one of the interrupt pins of 8085 processor (RST7.5, 6.5, 5.5 ,TRAP or INTR) goes high. • A software interrupt is generated when the processor encounters an instruction like CALL or Jump etc during the normal execution process.
- 4. Software Interrupts • There are 8 software interrupts supported by 8085 processor. • They are RST0, RST1, RST2, RST3, RST4, RST5 , RST6 & RST7. • The corresponding vector addresses are RST 0 ----00H RST 6 ----30 H RST 1-----08H RST 7 -----38 H RST 2---- 10H RST 3 ----18H RST 4-----20H RST 5 ------28H
- 6. Sub-Routine Program • The below is the assembly language program for sub-routine and its diagrammatic representation..
- 7. Ex: Hardware Interrupts • Lets now understand the hardware interrupt concept. • Assume that ADC(Analog to Digital Conversion) chip is interfaced to 8085 microprocessor. • When compared to speed of the 8085 the ADC is a very low speed device. • So, ADC can be interfaced to 8085 such that ,when the conversion process is complete ,it will send EOC(End of Conversion) signal to 8085 through the pin INTR or RST7.5 ,6.5,Trap etc. • This external signal is known as hardware Interrupt .
- 8. contd • Similarly ,when press a key board connected to 8085 it creates an external interrupt. • A serial communication devices like UART /USART can generate an external (hardware) interrupt when the data transmission is complete.
- 9. Interrupt control • This block of the microprocessor ,actually controls the operation of interrupts. • This block is linked to the CPU through the 8-bit internal data bus. • This interrupt control has five interrupt signals. They are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. • The control block will take care of enabling and disabling of these interrupts etc. • Let us consider now these 8085 interrupts in detail.
- 10. 8085 Interrupts • The 8085 Microprocessor supports five interrupts. • They are TRAP, RST 7.5, RST 6.5, RST5.5 and INTR. • Among all these interrupts TRAP has the highest priority and INTR (Interrupt ) has the lowest priority. • The TRAP is also a non maskable interrupt. The numbers succeeding the RST (7.5, 6.5, and 5.5) are related to the call locations in the IVT. • Here RST means RESTART. Among these interrupts INTR is the only non-vectored interrupt whereas the other interrupts are vectored interrupts.
- 11. Interrupt Instructions • These interrupts are associated with some special instructions like EI ,DI,SIM,RIM . • EI instruction will enable the Interrupts. • DI instruction will disable Interrupts. • SIM instruction sets the mask on the Interrupts. • RIM Instruction read the status of the interrupts. • Actually, upon reset all the interrupts are disabled. • So, to enable all the interrupts the instruction EI is executed.(i.e the Flip-Flop is set to 1) • But this will not work on TRAP interrupt as it is non- maskable .
- 12. contd • The execution of DI instruction disables the interrupts of 8085, except TRAP interrupt. • SIM Set Interrupt Mask is a 1 byte multi-purpose instruction which masks the Interrupts. • RIM instruction reads the status of interrupts i.e it checks whether the interrupts are enabled or not. • It also checks whether RST 7.5,6.5 and 5.5 are masked or not. • This instruction is also used for serial input of data.
- 13. TRAP • It is a non maskable interrupt with highest priority. • It means that whenever the pin is activated, the 8085 will always get interrupted even if the 8085 is in DI (Disable Interrupt) state. • Trap input is both edge and level sensitive. So, the microprocessor is interrupted when the input is both edge and level sensitive. • The microprocessor is interrupted when the input pulse goes from low to high or when it remains high. • When interrupted, the microprocessor loads the program counter with 0024H.
- 14. RST 7.5 • It is an edge sensitive pin. In 8085,internally a flip- flop connected to RST 7.5 interrupt pin . • This flip flop is set 1, when a positive going edge occurs on RST 7.5 input. RST 7.5 interrupt has a higher priority than RST 6.5, RST 5.5 and INTR. • This RST 7.5 is a maskable interrupt known as MI. This interrupt is enabled under program control with two instructions EI (Enable Interrupt) and SIM (Set Interrupt Mask).
- 15. RST 6.5 & RST 5.5 • These interrupts are level sensitive, it means the triggering level should be ON until the microprocessor completes the execution of the current instruction. • If the microprocessor is not able to respond to the requests immediately, they should be stored or held by external hardware. • These two interrupts are also maskable interrupts. RST 6.5 and RST 5.5 have higher priority than INTR interrupt.
- 16. INTR • It is the only non-vectored interrupt in 8085 which has the lowest priority among all the interrupts. • This is also a maskable interrupt and can be disabled using the instruction DI (Disable Interrupt). • The mask on INTR can be removed by executing EI (Enable Interrupt) instruction. When EI instruction is executed, the flip flop associated with this is SET and the mask is removed.
- 17. Priority of Interrupts • The order of priority of Interrupts is given in the below table. From the table it is clear hat the Interrupt TRAP has the highest priority and INTR has the lowest priority.