VLSI D PPT.pdf
- 1. 2 Topics Unit I Introduction to ICtechnology • MOS,PMOS,NMOS,CMOSandBiCMOS Technologies: • Basic Electrical Properties of MOS and BiCMOS Circuits • Current – Voltage relationships • MOS transistor thresholdvoltage • Figure of Merit, PassTransistor • NMOS, CMOS and BiCMOS Inverter • Various Pul ups 4 5 6 7 REGIONOFOPERATION Creating achannel • When sufficient electrons are accumulated under the gate an n-region is created, connecting the drainand the source • Thiscausesthe current to flow from the drain to source • The channel is formed by inverting the substrate surfacefrom p to n, thus induced channelis alsocalled asthe inversionlayer. • The voltage between gate and source called vgs at which there aresufficient electron under the gateto form aconducting channel is called thresholdvoltage Vth. 23 Formation of Channel • First, the holes are repelled by the positive gate voltage, leaving behind negative ions and forming a depletion region. Next, electrons areattracted to the interface, creating a channel (“inversionlayer”). 24 MOSTransistor Current direction • The source terminal of an n-channel(p-channel) transistor is defined aswhichever of the twoterminals hasalower(higher) voltage. • When a transistor is turned ON,current flows from the drain to source in an n-channeldevice and from source to drain in ap-channel transistor. • In both cases,the actual carriers travel from the source to drain. • Thecurrent directions are different becausen-channel carriers are negative, whereas p-channel carriers are positive. 25 26 27 50 51 Basicprocesses involved in fabricating Monolithic ICs 1. Silicon wafer (substrate)preparation 2. Epitaxialgrowth 3. Oxidation 4. Photolithography 5. Diffusion 6. Ion implantation 7. Metallization 8. Testing 9. Assembly processing &packaging Oxidation 52 Formation of silicon dioxide layer on the surfaceofSiwafer 1. protects surface fromcontaminants 2. forms insulating layer betweenconductors 3. form barrier to dopants during diffusion or ion implantation 4. grows aboveand into siliconsurface Dry oxidation: lower rate andhigherquality Wet oxidation: higher rate andlowerquality 1. SiO2 is an extremely hard protective coating & is unaffected by almost all reagents except by hydrochloric acid. Thus it stands against anycontamination. 2. By selective etching of SiO2, diffusion of impurities through carefully defined through windows in the SiO2 can be accomplishedto fabricate variouscomponents. Oxidation 53 The silicon wafers are stacked up in a quartz boat & then inserted into quartz furnace tube. The Si wafers are raised to a high temperature in the range of 950 to 1150oC & at the same time, exposed to a gascontaining O2 or H2O or both. The chemical actionis Si+2H2O----------->Si O2+2H2 (Wet) Si+ O2 -------------> SiO2 (Dry) Photolithography 54 • Coat wafer withphotoresist (PR) • ShineUVlight through mask to selectively exposePR • Useacid to dissolveexposed PR • Nowuseexposedareasfor – Selectivedoping – Selective removal ofmaterial under exposedPR UV Light Mask Photoresist Wafer AddingMaterials 55 Silicon • Addmaterials on topof silicon – Polysilicon – Metal – Oxide (SiO2)-Insulator • Methods – Chemicaldeposition – Sputtering (Metal ions) – Oxidation Added Material (e.g. Polysilicon)
- 2. 56 Oxide(Si02)- TheKeyInsulator • ThinOxide – Addusingchemicaldeposition – Usedto form gate insulator &block active areas • Field Oxide(FOX)- formed byoxidation – Wet (H20at 900oC- 1000oC)or Dry (O2at1200oC) – Usedto insulate non-activeareas SiO2 Thin Oxide FOX SiN / SiO2 FOX Silicon Wafer Silicon Wafer 57 Silicon Patterning Materialsusing Photolithography • Add material towafer • Coat with photoresist • Selectivelyremove photoresist • Removeexposedmaterial • RemoveremainingPR Added Material (e.g. Polysilicon) 58 Diffusion Silicon Diffusion • Introduce dopant viaepitaxyor ion implant e.g. Arsenic (N), Boron(P) • Allow dopants to diffuse athigh temperature • Blockdiffusion in selectiveareas using oxide orPR • Diffusion spreads bothvertically, horizontally Blocking Material (Oxide) Ion Implantation Process Conditions Flow Rate: 5 sccm Pressure: 10-5 Torr Accelerating Voltage: 5 Focus Beam trap and gate plate Neutral beam and beam path gated to 200 keV Gases Ar AsH3 B11F3 * Solids Ga In Sb Neutral beam trap Y - axis and beam gate scanner Resolving Aperture X - axis scanner Wafer in wafer process chamber Equipment Ground 180 kV Acceleration Tube He N2 PH3 SiH4 SiF 4 Slide 5 G 9 eH Liquids Al(CH3)3 Ion Source 90° Analyzing Magnet Terminal Ground 20 kV Metallization • Sputter on aluminum overwholewafer • Pattern to removeexcessmetal, leavingwires M etal Metal Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate 76 drive Low power dissipation High packing density High speed High output (gm) High Noise Margin High transconductance High input impedance Features The objective of the Bi-CMOS is to combine bipolar and CMOS so asto exploit the advantages of both the technologies. Today Bi-CMOS has become one of the dominant technologies used for high speed, low power and highly functional VLSI circuits. The process step required for both CMOS and bipolar are almost similar The primary approach to realize high performance Bi-CMOS devices isthe addition of bipolar process steps to a baseline CMOSprocess. The Bi-CMOS gates could be used as an effective way of speeding upthe VLSI circuits. The applications of Bi-CMOS are vast. Advantages of bipolar and CMOS circuits can be retained in Bi-CMOS chips. BiCOMSStechnology enables high performance integrated circuits IC’s b77ut increases process complexity. 78 Characteristics of Bipolar Technology Higher switching speed Higher current drive per unit area, highergain Generally better noise performance and better highfrequency characteristics Improved I/O speed (particularly significant with the growingimportance of package limitations in high speed systems). high power dissipation lower input impedance (high drive current) low packing density low delay sensitivity to load 79 Characteristics of CMOS Lower static power dissipation Higher noise margins Higher packing density High yield with large integrated complex functions High input impedance (low drive current) Scalable threshold voltage High delay load sensitivity Low output drive current (issue when driving large capacitiveloads) Bi-directional capability (drain & source are interchangeable) A near ideal switching device, Low gain BASICELECTRICALPROPERTIES Topics • Basicelectrical properties of MOSandBiCMOS circuits: Ids-Vds relationships • MOStransistor threshold voltage,gm,gds,figure of meritwo • passtransistor • NMOSinverter • Variouspull-ups • CMOSinverter analysisanddesign • BiCMOSinverter Pass-TransistorLogic Circuits(1) iguratio CMOS transmission gate A simple approach for implementing logic functions utilizes series and parallel combinations of switches that are controlled by input variables to connect the input and output nodes. Each of the switches can be implemented either by a single NMOS transistor or by a pair of CMOS transistors connected in CMOS transmission gate conf Y=AC . 136 Pass-TransistorLogic Circuits(2) An essential requirement in the design of pass-transistor logic is ensuring that every circuit node has at all times a low-resistance path to VDD or toground. A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It isprovided in (b) through switch S2. 137 If B is high, S1 closes and Y=A. Y will be VDD if Ais high or ground ifA is low. If B is low, S1 opens and Y becomes a high-impedance node. If voltage of Y is initially zero, it will remain so. If voltage of Y is initially high at VDD, then the inevitable leakage current will discharge the C and can no longer be considered a static circuit. Pass-TransistorLogic Circuits( 138 Another switch, S2, controlled by B is connected between Y and ground. When B goes low, S2 closes and establishes a low-resistance path between Y and ground. The problem can be easily solved by establishing for node Y alow- resistance path that is activated when B goes low. A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is providedin (b) through switch S2. 139 MOSFET Ids-Vds 2 F 171 2 F VSB 2 F Threshold Voltage Components(Cont.) • Thefinal expression for VT0andVT are 2q N A Si Cox QB0 Qox • and VT 0 GC 2 F C C ox ox – The threshold voltage depends on the source-to-bulk voltage which is clearly separated out. The component is referred to asbody effect. If the source to bodyvoltage VSBisnon-zero, the corrective term must be applied toVT0. VT VT 0 173 R 0 1 •Inverter : basicrequirement for producing a complete range of Logiccircuits 1 Vo 0 Vss R
- 3. 174 Vdd Vo BasicInverter: Transistor with source connected to ground and aload resistor connected from the drain tothe positive Supply rail Output is taken from the drain andcontrol input connected between gate and ground Resistors are not easily formed in silicon - they occupy too much area Transistors can be used as the pull-up device Vss R Pull-Up Vin PullDown 175 D Vo Vin Vss NMOSDepletion Mode Transistor Pull - Up • Pull-Upisalways on – Vgs=0; depletion • Pull-Down turns on when Vin>Vt Vdd •With no current drawn from outputs,Ids for both transistorsisequal S V0 Vt Vdd D Non-zerooutput S Vi 176 Ids Vgs=0.2VDD Vgs=0 Vgs=-0.2 VDD Vgs=-0.4 VDD Vgs=-0.6VDD Vds Vgs=VDD Ids V Vin VDD–Vds Ids DD Vgs=0.8VDD VDD Vgs=0.6 VDD Vgs=0.4VDD Vgs=0.2VDD Vds V VDD o 177 Increasing Zpu/Zpd Vin VDD Decreasing Zpu/Zpd Vinv V VDD • Point where Vo=Vin iscalled Vinv • TransferCharacteristics and Vinv canbe shifted by altering ratio of pull-up to Pulldownimpedances o NMOSInverter 191 5 V When VIN is logic1, VOUT 5 V R I = 5/R D VOUT logic 0. Constant nonzero current R Power is used even though D V D VIN 5 V + 0 V VDS _ no new computation is being performed. VIN 0 V ID =0 + VDS _ OUT 5 V PMOSInverter 192 0 V + ID =-5/R R OUT 5 V When VIN is logic 0, VOUT is logic 1. Constant nonzero current flows through transistor. Power is used even though no new computation is being performed. 5 V ID =0 R - VDS + VOUT 0 V 194 VDD (Logic 1) S VDD 207 Topics Unit II VLSICIRCUITDESIGNPROCESSES • VLSI design flow • MOSlayers • Stickdiagrams • DesignRulesand Layout • 2 um CMOS designrulesforwires • Contacts andTransistors • Layoutdiagramsfor NMOSand • CMOSinverters andgates,Scalingof MOScircuits VLSIDesignof approach ofIC 2 6/ 03 8/2015 209 LayerTypes • p-substrate • n-well • n+ • p+ • Gate oxide (thinoxide) • Gate(polycilicon) • FieldOxide – Insulated glass – Provide electricalisolation 210 NOT APPLICABLE NB N D NP N M N C N G NI Buried contact Contact cut Overglass Implant Metal 1 n- diffusion n+active Thniox Polysilicon GRAY nMOS ONLY YELLO nWMOS ONLY BROWN BLUE BLACK RED GREEN CIF LAYER MASK LAYOUT ENCODING MONOCROME LAYERS STICK ENCODING MONOCROME COLOR Stick diagram Encodings for a simple single metal nMOS process 211 Stick Diagrams Metal poly ndiff pdiff Buried Contact Can also draw in shades of gray/line style. Contact Cut 212 StickDiagrams • VLSIdesignaims to translate circuitconcepts onto silicon. • Stick diagrams are a means of capturing topography and layerinformation usingsimple diagrams. • Stickdiagramsconveylayer information through colour codes(or monochromeencoding). • Actsasaninterface between symboliccircuit and the actuallayout. Stick Diagrams 213 • Does show all components/vias. • It shows relative placement of components. • Goes one step closer to the layout • Helps plan the layout and routing Stick Diagrams 214 • Does not show – Exact placement of components – Transistor sizes – Wire lengths, wire widths, tub boundaries. – Any other low level details such as parasitics.. Stick Diagrams StickDiagrams– Somerules 215 • Rule1. • Whentwo or more ‘sticks’of the sametype crossor touch each other that represents electricalcontact.
- 4. Stick Diagrams StickDiagrams– Somerules 216 • Rule2. • When two or more ‘sticks’of different type crossor touch each other there is no electrical contact. (If electrical contact is neededwe haveto show the connectionexplicitly). Stick Diagrams StickDiagrams– Somerules 217 • Rule3. • Whenapoly crossesdiffusion it represents atransistor. Note: If a contact is shown then it is not a transistor. Stick Diagrams StickDiagrams– Somerules 218 • Rule4. • In CMOSademarcation line is drawn to avoid touching of p-diff withn-diff. All pMOS must lie on one sideof the line and all nMOS will haveto be on the other side. 219 220 5 V Dep Vout Enh 0V NMOS INVERTER 5 v 0 V Vin NMOS-NAND 221 NMOS-NOR 222 NMOSEX-OR 223 NMOSEX-NOR 224 PMOS-INVERTER 225 PMOSNAND 226 PMOS-NOR 227 SticksdesignCMOSNAND: 228 • Start with NANDgate: 229 NANDsticks VDD a VSS out b 230 Stick Diagram - Example A B NOR Gate OUT 231 Out Stick Diagram - Example Power A C B Ground
- 5. 232 2 I/PORGATE 233 2 I/PAND 234 235 Y=(AB+CD)’ 236 Y=(AB+CD)’“TICK 237 238 DesignRules • Design rules are a set of geometrical specificationsthat dictate the designof the layout masks • A designrule set provides numericalvalues – For minimumdimensions – For minimum linespacings • Design rules must be followed to insure functional structures on the fabricated chip • Designrules changewith technologicaladvances (www.mosis.org) 248 Design Rules Minimum length or width of a feature on a layer is 2 Why? To allow for shape contraction Minimum separation of features on a layer is 2 Why? To ensure adequate continuity of theintervening materials. DesignRules 249 Minimum width of PolySi and diffusion line 2 Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their continuity Metal Diffusion Polysilicon DesignRules 250 PolySi – PolySi space 2 Metal - Metal space 2 Diffusion – Diffusion 3 To avoid the possibility of their associated regions overlapping and conducting current Metal Diffusion Polysilicon DesignRules 251 Diffusion – PolySi To prevent the lines overlapping to form unwanted capacitor Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metallines can overlap or cross Metal Diffusion Polysilicon 252 Metal VsPolySi/Diffusion • Metal lines canpassover both diffusionand polySi without electricaleffect • It is recommended practice to leave between a metal edge and a polySi or diffusion line to which it is not electrically connected Metal Polysilicon Review: 253 poly-poly spacing 2 diff-diff spacing 3 (depletion regions tend to spread outward) metal-metal spacing 2 diff-poly spacing 254 • TwoFeatureson different masklayerscanbe misaligned by amaximum of 2l on thewafer. • If the overlap of these two different mask layerscanbe catastrophic to the design,they must be separatedby at least2l • If the overlap is just undesirable,theymust be separatedby at leastl ContactCut 264 etal connects to polySi/diffusion by contact cut. Contact area: 2 2 Metal and polySi or diffusion must overlap this contact area by so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole 4 ContactCut 265 2 4 Contact cut – any gate: 2 apart Why? No contact to any part of the gate.
- 6. ContactCut 266 2 Contact cut – contact cut: 2 apart Why? Toprevent holes from merging. Rules for CMOS layout 267 Similar to those for NMOS exceptNo 1. Depletion implant 2. Buried contact Additional rules 1. Definition of n-well area 2. Threshold implant of two types of transistor 3. Definition of source and drains regions for the NMOS and PMOS. Rules for CMOS layout 268 To ensure the separation of the PMOS and NMOS devices, n-well supporting PMOS is 6 away from the active area of NMOS transistor. Why? Avoids overlap of the associated regions 6 n+ n-well Rules for CMOS layout 269 N-well must completely surround the PMOS device’s active area by 2 2 2 Rules for CMOS layout 270 The threshold implant mask covers all n-well and surrounds the n-well by 2 2 Rules for CMOS layout 271 The p+ diffusion mask defines the areas to receive a p+ diffusion. It is coincident with the threshold mask surrounding the PMOS transistor but excludes the n-well region to be connected to the supply. 2 2 Rules for CMOS layout 272 A p+ diffusion is required to effect the ground connection to the substrate. Thus mask also defines this substrate region. It surrounds the conducting material of this contact by 4 Rules for CMOS layout 273 Total contact area = 2 4 Neither NMOS nor CMOS usually allow contactcuts to the gate of a transistor, because of the danger of etching away part of the gate 6/3/2015 274 Topics UNIT-III GATELEVELDESIGN • Logicgatesandother complexgates • Switchlogic • Alternate gatecircuits • Timedelays • Driving large capacitiveloads • Wiring capacitances • Fan-inand fan-out, Choiceof layers NMOSGateconstruction •NMOS devices in series implement a NAND function A •B A B •NMOS devices in parallel implement a NOR function A +B A B A B F 0 0 1 0 1 1 1 0 1 1 1 0 A B F 0 0 1 0 1 0 1 0 0 1 1 0 275 PMOS Gate construction •PMOS devices in parallel implement a NAND function A A •B •PMOS devices in series implement a NOR function B A A +B B A B F 0 0 1 0 1 1 1 0 1 1 1 0 A B F 0 0 1 0 1 0 1 0 0 1 1 0 276 283 Alternatives to StaticCMOS • SwitchLogic • nmos • Pseudo-nmos • DynamicLogic • Low-PowerGates 284 SwitchLogic • Keyidea: usetransistorsasswitches • Concern: switches arebidirectional A B AND OR 285 Switch Logic- PassTransistors • Usen-transistor as“switches” • “Threshold problem” IN: VDD OUT: VDD-Vtn – Transistorswitchesoff when Vgs<Vt – VDDinput ->VDD-Vt output A: VDD • “pecial gateneededto “restore”values Switch Logic- TransmissionGates 286 • Complementarytransistors - n andp • No thresholdproblem • Cost:extra transistor, extra controlinput • Not aperfectconductor! A’ A’ A A Switch LogicExample- 2-1MUX 287 IN
- 7. 291 Pseudo-nmosLogic • Sameidea, asnmos, but usep- transistor for pullup • "ratioed logic" required for proper design (moreabout this next) • Tradeoffs: – Fewer transistors -> smaller gates, esp. for largenumber of inputs – lesscapacitativeload on gates that drive inputs – larger powerconsumption – lessnoisemargin (VOL>0) – additional design considerations due to ratioed logic Pulldown Network Passive Pullup Device: P-Transistor OUT 292 Rationed Logic forPseudo-nmos • Approach: – AssumeVOUT=VOL=0.25*VDD – Assume1 pulldown transistor ison – Equate currents in p,ntransistors – Solvefor ratio between sizesof p, n transistors OUT Idp Pulldown Network Idn DCVSLogic 293 – Further calculations seriesconnections • DCVS-Differential CascodeVoltageSwitch • Differential inputs, outputs • Twopulldownnetworks • Tradeoffs – Lower capacitativeloading than staticCMOS – Noratioed logicneeded – Low staticpower consumption – More transistors – More signals toroute between gates OUT A B C OUT’ A’ B’ C’ OUT’ Pulldown Network OUT Pulldown Network DynamicLogic 294 Precharg • Keyidea: Two-stepoperation – precharge - charge CStologichigh – evaluate - conditionally dischargeCS Storage Node C • Control - precharge clockSf ignal Pulldown Network B C S Storage Capacitance A Precharge Evaluate Precharge Domino Logic 295 • Keyidea: dynamic gate+ inverter • Cascadedgates - “monotonically increasing” in4 x1 x2 x3 CS Pulldown Network B C Domino LogicTradeoffs 296 • Fewertransistors ->smaller gates • Lowerpower consumption thanpseudo-nmos • Clockingrequired • Logicnot complete (AND,OR,but noNOT) 297