IC_Lectures_Updated.pdf

Chapter (1)
Introduction
Prepared by
Assist. Prof. Mohamed Ismail
Assist. Professor at Delta Higher Institute for Engineering &
Technology

Outlines
Why build Integrated Circuits (Ics)?
History of ICs.
Properties of VLSI.
Moore’s Law.
Components of IC.
VLSI MOS Transistors.
Scaling.
VLSI Design Considerations (Problems).
Mixed Signal VLSI.
Digital Design of VLSI.
Trends in VLSI.
Summary of Technology Trend.
MOSFET as a Capacitor.
References

Why Build Integrated Circuits?
Much smaller and consume less
power than the discrete component
needed to build electronic systems.
Much easier to design and
manufacture.
More reliable than discrete
components.
Improved performance because of
low cost more than complex circuitry.

History of ICs
1958 : First IC ( Flip-Flop using 2
transistors built by J.Kilby).
1960 : SSI (Small Scale Integration)
less than 100 components/chip.
1966 : MSI ( Medium Scale
Integration) more than 100
components/chip.
1969 : LSI (Large Scale Integration)
more than 1000 components/chip.

History of ICs Cont’d
1975 : VLSI (Very Large Scale
components/chip.
1989 :ULSI(Ultra Large Scale
components/chip.
2003 : GLSI (Giant Large Scale
components/chip

Properties of VLSI
Compact.
Reliable.
Not expensive.

Moore’s Law
No. of components (transistors)
per chip doubles every [year, 18
months, or 2 years].

Components of IC
VLSI components may be included 4
inputs and 2 outputs.
Its Inputs are:
– Material research
– Device modeling
– Circuits and systems design
– Computer-aided design CAD
Simulation.
Its Outputs are:
– Technology Development.
– Applications as mobiles, robotics, etc.

Scaling
Assume all geometric dimensions
(horizontal & vertical) and voltage and
current are reduced by factor α.
Scaling Advantages:
– Reduced Si area.
– Reduced power dissipation.
– Increased the speed.
– Increased battery lifetime.
Scaling Disadvantages:
– Parasitic resistance.
– Parasitic capacitance.
– Short channel effect.

Scaling Cont’d
Scaling Process Summary:
Effect
After Scaling
Before
Scaling
Amount
Reduced
L / α
L
Length
Reduced
W / α
W
Width
Reduced
ID / α
ID
Drain
Current
Reduced
VDD / α
VDD
Power
Supply
Reduced
VDD ID / α2
VDD ID
Gate Power
Reduced
LW / α2
LW
Area
Increased
α J
J = ID / LW
Current
Density
The Same
EDS = VDS / L
EDS = VDS / L
Electric Field

VLSI Design Considerations
Si Area.
Power Dissipation.
Delay Time.
Speed.
Testability.
Cost: [Die area, Packaging, Testing, …]
Time to Market.
Performance: [Optimization requirements
for high performance].
Design Complexity.

Mixed Signal VLSI
Mixed A/D VLSI:
– As ISDN (Integrated Service Digital Network).
– The analog part provides the I/O interface to
the core of the chip which is digital.
Mixed D/A VLSI :
– As ANN (Artificial Neural Network).
– The digital part provides the I/O interface to
the core of the chip which is analog.

Trends in VLSI
Transistor:
– Smaller, faster, less power.
Interconnect:
– Less resistance, faster, longer.
Yield:
- Smaller die size, higher yield.

Summary of Technology Trend
Processor:
– Logic capacity increases by about 30% per
year.
– Clock frequency increases by about 20% per
year.
– Cost / function decreases by about 20% per
year.
Memory:
– DRAM capacity increases by about 60% per
year (4x every 3 years).
– Speed increases by about 10% per year.
– Cost / bit decreases by about 25% per year.

MSFET as a Capacitor Cont’d
10-12

References
N.West and D.Harris, CMOS VLSI Design.
S.Kang and Y.Leblebici, CMOS Digital
Integrated Circuits.
E.D.Fabricius, Introduction To VLSI
Design.
Wayne Wolf, FPGA- Based system
Design.

Chapter (2)
Digital MOSFET Switches
Prepared by
Technology

Outlines
NMOS Review.
PMOS Review.
MOS Switch.
Digital MOS Switch.
MOSFET as a Switch.
Switch Networks.
Single Pass Transistor Switch.
CMOS Transmission Gate (TG) Switch.
Solved Examples.

The function of a switch network is true
when the two terminals of the network are
connected together.
Since for parallel switches the terminals
are connected if either switch is on, the
function is OR.
For series switches the network is
conducting only if both switches are on,
hence an AND gate.

Limitations of Pass Transistor
Switches
The input of the gate of a pass transistor
mustn’t come from the output of pass
transistor of the same type.
If we need more than 4 stages; then a
buffer must be used after every 4 stages.

Advantages of CMOS TG
Switches
Strong one, strong zero.
Low nonlinearity (RoN linear in Parallel
Combination).
Low Resistance (RoN = Rn // Rp).
Cancellation of Noise.

2 x 1 Mux using CMOS TG
F
s
P0
0
P1
1
Important Notes:
No. of inputs =
No. of switches.
Only one output.
No. of inputs =
2No. of Sel.

2-i/p XOR Gate
F
B
A
0
0
0
1
1
0
1
0
1
0
1
1
If A = 0, F = B.
If A = 1, F = ത
𝐵
F

Analysis Example
F
A
B
0
X
0
0
X
0
0
0
1
VB - VTn
1
1
Find the o/p F for the following circuit.
Solution

Chapter (3)
MOSFET Inverters
Prepared by
Technology

Outlines
Introduction to Digital Inverter.
The Main Types of MOS Inverters.
Resistive Load Inverter.
EMD Inverter.
DMD Inverter.
CMOS Inverter.
Pseudo CMOS Inverter.
BiCMOS Inverter.
Dynamic MOS Inverter.
Realization Problems Rules.
Solved Examples.

Introduction to Digital
Inverter

Digital Inverter
A Fundamental logic gate that performs
invert Boolean operation.
Single input logic gate.
Logic ‘1’ and ‘0’ are represented by
node voltages referring to ground
potential.
According to “Positive logic
convention”: Logic ‘1’ is VDD (Highest
Supply Voltage) and logic ‘0’ is GND
(0V).

Digital Inverter Symbol & Truth Table

Ideal VTC
Voltage Transfer Characteristics
(VTC): is a plot of Vin versus Vout for
any inverter.

The Main Types of MOS
Inverters

MOS Inverters Types
There are 7 types of MOS Inverters:
Resistive Load.
Enhancement Mode Device (EMD).
Depletion Mode Device (DMD).
Complementary MOSFET (CMOS).
Pseudo CMOS Inverter.
BiCMOS Inverter.
Dynamic MOS Inverter.

Resistive Load Inverter
The Pull down is an enhancement
NMOS transistor.
The pull up is a resistive element.
NMOS is the driver.
The resistance is the passive load.
The main disadvantages of this type
are:
Large Si area.
High power dissipation (passive load).

Resistive Load Inverter Symbol & Operation
Vout
NMOS
Vin
VDD
(Through R)
Off (O.C.)
0V (Logic 0)
0V (Through
NMOS)
ON (S.C.)
VDD (Logic 1)

Enhancement Mode Device (EMD)
NMOS transistor.
The pull up is an enhancement
NMOS transistor in which the gate is
always connected to drain (VG = VD).
The pull down NMOS is the driver.
The pull up NMOS is the active load.
Due to the connection between G &
D in pull up transistor; it can’t be
operate in linear region.

EMD Symbol & Operation
Vout
Pull down
NMOS
Vin
VDD (Through pull up
NMOS)
Off (O.C.)
0V (Logic 0)
0V (Through pull
down NMOS)
ON (S.C.)
VDD (Logic 1)

Depletion Mode Device (DMD)
NMOS transistor.
The pull up is a depletion NMOS (VTu
is negative) transistor in which the
gate is always connected to source
(VG = VS).
The pull down NMOS is the driver.
The pull up NMOS is the active load.
Due to the connection between G &
S in pull up transistor; it can’t be
operate in cut off region (VGS > VTu)

DMD Symbol & Operation
Vout
Pull down
NMOS
Vin
VDD (Through pull up
NMOS)
Off (O.C.)
0V (Logic 0)
0V (Through pull
down NMOS)
ON (S.C.)
VDD (Logic 1)

Complementary MOSFET (CMOS)
Inverter
The Pull down is an enhancement NMOS
transistor.
The Pull up is an enhancement PMOS
transistor.
Both pull down & pull up transistors are
drivers (Vin connected to Gn & Gp).
The main advantages of this type are:
It is full logic swing inverter.
No static power dissipation.
Large noise margin.
Symmetrical VTC.

CMOS Inverter Symbol & Operation
Vout
Pull up
PMOS
Pull down
NMOS
Vin
VDD (Through
pull up PMOS)
ON (S.C.)
Off (O.C.)
0V (Logic 0)
0V (Through pull
down NMOS)
Off (O.C.)
ON (S.C.)
VDD (Logic 1)

Pseudo CMOS Inverter
The Pull down is an enhancement NMOS
transistor (Driver).
The Pull up is an enhancement PMOS
transistor in which the gate is always
connected to GND (Active Load).
The main advantages of this type are:
Replace large PMOS stacks with sing
device (in realization problems).
Reduces overall gate size.
Useful for wide-NOR structures.

Pseudo CMOS Symbol & Operation
Vout
Pull down
NMOS
Vin
VDD (Through
pull up PMOS)
Off (O.C.)
0V (Logic 0)
0V (Through pull
down NMOS)
ON (S.C.)
VDD (Logic 1)

Bi-CMOS Inverter
Introduced in early 1980s.
Combines CMOS logic (as a first stage) and
Bipolar logic (BJT as a second stage).
The main advantages of using BJT:
High speed.
High output drive current.
The main advantages of using CMOS:
Low power dissipation.
Large input impedance.
Large noise margin.
Bi-directional capability (D&S are
interchangeable).
Near ideal switching device.

Bi-CMOS Inverter Disadvantages
The main disadvantages of Bi-CMOS
are:
Greater complexity than CMOS.
Delay due to minority carriers
stored on base.
So a discharge path for these
minority carriers must be provided
(Z1, Z2 in basic circuit & M3, M4 in
modified circuit).

Basic Bi-CMOS Inverter Circuit
Vout
M2, Q2
M1, Q1
Vin
VDD – VBE2
ON
Off
0V (Logic 0)
VBE1
Off
ON
VDD (Logic 1)

Modified Bi-CMOS Inverter Circuit
Vout
M2, M3,Q2
M1,M4, Q1
Vin
VDD – VBE2
ON
M1,M4 Off
Q1Fast Off
0V (Logic 0)
VBE1
M2,M3 Off
Q2Fast Off
ON
VDD (Logic 1)

Dynamic MOS Inverter
A basic method to store (memorize) the
logic values is to use the input
capacitances of the MOS transistors
A capacitance with no stored charge
(discharged) is said to represent a logic
‘0’, respectively a charged capacitance is
said to represent a logic "1”.
Signals are applied in the gate circuit,
from one capacitor to the other, using
transistors driven in conduction by special
driving signals (command pulses).
Operate in a small dissipation power
regime.

Dynamic MOS Inverter Cont’d
Dynamic MOS circuits offer a better
integration density than the static ones.
Transistors performance doesn’t depend
on their geometry.
Power consumption is on demand
(through clk signal (Φ)).
Drawbacks:
More driving (command) signals, more logic.
Very difficult layout due to routing of clk.

Basic Circuit & Operation Cont’d
Actions
Time Interval
Vin
Apply Vp1; Q1 OFF, Q2 ON
then C1 charges with VDD
t = t0
0V (Logic 0) Apply Vp2; Q3 goes ON and
hence charge transmits from
C1 to C2 then Vout = VDD
t = t1
Q1 ON and C1 discharges
through Q1
t2 < t < t3
VDD (Logic 1)
Apply Vp2; Q3 will open, so
the charge on C1 transfers to
C2 and hence Vout = 0V
t = t4

Basic Circuit & Operation Cont’d
For this inverter the output response
is delayed with t1 – t0 or t4 – t2. Clock
pulses (Vp1 & VP2) are needed to be
applied periodically, achieving the
refresh of the information stored on
parasitic capacitances.
A minimum refresh frequency must
be designed to keep right information
on capacitances, which otherwise
discharge through existing open
junctions.

NMOS Dynamic Shift Register Cont’d
If Vin = VDD, and Φ1 = VDD; then Vo1 = VDD –
VTN (Logic '1'). So, CL charges through MN1.
As Vo1 goes high, Vo2 goes low.
If Φ2 is high, the low level will be transmitted
through MN2 and Vo4 would be logic '1'. Thus
logic '1' shifted from input to output.
The main drawbacks of this type are:
The use of single pass transistor switch.
The use of DMD inverter in which full logic
swing couldn't be achieved.
The synchronization between the two different
clock signals has been very complex.

CMOS Dynamic Shift Register Cont’d
If Vin = VDD, and Φ1 = Φ = VDD; then Vo1
= (Logic '1').
As Vo1 goes high, Vo2 goes low.
If Φ2 = ഥ
Φ is high, the low level will be
transmitted through the switch of the
second stage and Vo4 would be VDD
(logic '1’).
Thus logic '1' shifted from input to
output during one clock cycle.

Domino Circuit
Domino circuit is used for implementation
of logic functions based of dynamic
behavior.

Domino Pre-charge and Evaluate

Demorgan Law
• 𝐴 + 𝐵 = ҧ
𝐴. ത
𝐵
• 𝐴. 𝐵 = ҧ
𝐴+ ത
𝐵
➢ More generally, the complement of a function
is the dual of the function with inverted
inputs.
➢ Dual operation means exchanging the AND &
OR operations.
➢ It can be applied to arbitrarily complex
expressions.

Realization using EMD, DMD, Pseudo
CMOS Inverters
For the pull down:
And relation means series connection.
OR relation means parallel connection.
For the pull up:
Not affected.
You must make sure that there is a
complement over the logic function to be
implemented.
If there isn’t a complement take 2-
complements using Demorgan theorem.

Realization using CMOS Inverter
For the pull down:
For the pull up:
Series connection in pull down will be
parallel in pull up & vice versa.
NMOS will be replaced by PMOS.
implemented.
If there isn’t a complement take 2-
complements using Demorgan theorem.

Realization using Modified Bi-CMOS
Inverter
For M1, M4:
For M2:
Series connection in M1, M4 will be
parallel in M2 & vice versa.
NMOS will be replaced by PMOS.
For M3, Q1, Q2:
Not affected.
You must make sure that there is a complement
over the logic function to be implemented.
If there isn’t a complement take 2-complements
using Demorgan theorem.

Realization using Domino Circuit
For Pull Down (evaluate network):
implemented.
If there isn’t a complement we need to add
static inverter (CMOS Inverter) stage after
the output.

2-i/p NOR Gate using DMD
Vo = 𝐴 + 𝐵 .

2-i/p NOR Gate using CMOS
Vo = 𝐴 + 𝐵 .
A B
A
B

2-i/p NAND Gate using Bi-CMOS
Vo = 𝐴. 𝐵

2-i/p NOR Gate using Domino
Vo = 𝐴 + 𝐵

Realize the Following using CMOS
F = 𝐴. (𝐵 + 𝐶)

2-i/p XOR Gate using CMOS
F = 𝑎⨁𝑏 = ത
𝑎 . b + a . ത
𝑏

Chapter (4)
Noise Margin
Prepared by
Technology

Outlines
Actual VTC.
Inverting Voltage & Inverting Ratio.
Noise Margins.
Noise Margin versus Noise Immunity.
CMOS VTC.
Beta Ratio.
Noise in Digital ICs.
Noise Margins in DMD.

Actual VTC
As stated before, VTC or Voltage Transfer
Characteristics is a plot of Vin versus Vout for
any inverter.
Actual inverter VTC deviates from the Ideal
characteristics.
How can we evaluate the performance of
the inverter?
There are five parameters that defines the
inverter’s VTC as shown in the following table.
Definition
Parameter
The minimum output voltage when the output level is logic
'1'
VOH
The maximum output voltage when the output level is logic
'0'
VOL
The maximum input voltage when the input level is logic '0'
VIL
The minimum input voltage when the input level is logic '1'
VIH
The inverter threshold voltage at which Vin = Vout
Vth

Inverting Voltage &
Inverting Ratio

Inverting Voltage (Vinv)
It is also called threshold inverter voltage
(Vinv = Vth).
It is defined as the voltage at which the
input voltage of an inverter equals to the
output voltage of this inverter.
So; at Vinv we get (Vin = Vout = Vinv).
VOL

Inverting Ratio (Rinv)
The inverting ratio (Rinv) for any inverter is
defined as the ratio between the aspect ratio
of the pull up transistor to that of the pull
down transistor.
The aspect ratio (Z) is defined as the ratio
between the length of transistor channel to
its width (L / W).
So; Rinv = Zu / Zd =
(
𝐿
𝑊
)𝑢
(
𝐿
𝑊
)𝑑
.

Noise Margins
The noise margin is defined as the amount
of noise that can be added to the input
voltage without disturbing the logical state
of the output of the interconnect.

Evaluating Noise Margins
NML = VIL - VOL.
NMH = VOH – VIH.

Noise Margin versus Noise
Immunity

Noise Margin vs Noise Immunity
Noise margin is a local property of the
gate – gate communication.
Noise Immunity:
Property of the system (power supply
noise, crosstalk, reflections, can eat up
your noise margins).
Just making the swings bigger usually
doesn’t help noise immunity much
(because self induced noise grows too).
Good noise control – not only reliability,
but performance!!

Beta Ratio
Beta (β) is defined as the multiplication of k`
= μ cox (μA/V2) by the aspect ratio (W / L) of
the pull up or pull down transistor.
For CMOS inverter; the pull up is PMOS (βp
= μp cox (W / L)p) and the pull down is NMOS
(βn = μn cox (W / L)n).
If βp / βn ≠ 1, switching point will move from
VDD / 2 as shown in the following figure.
Called skewed gate.
Other gates collapse into equivalent
inverter.

Transistor Sizing & Noise Margin
Change beta (size) ratio, changes VIH,
VIL.
To balance Noise Margin (NM):
Make βn = βp (i.e. Wp = 3.5 Wn).
Actually Wp = 2 Wn is good enough.

VTC for DMD Inverter
Function
Mu (Q2)
Md (Q1)
Region
-
Linear (Triode)
Cutoff
I
Evaluate VIL, VOH
Linear
Saturation
II
Evaluate Vinv
Saturation
Saturation
III
Evaluate VIH, VOL
Saturation
Linear
IV

Evaluating VIL & VOH for DMD
Choose region II to evaluate VIL & VOH.
The main 4 steps in this region:
Check Md & Mu regions of operation .
IDSdsat = IDSuLin.
𝐾`𝑑
2
(W/L)d(VGSd – VTd)2 = Ku`(W/L)u(VGSu – VTu -
𝑉𝐷𝑆𝑢
2
) VDSu
Differentiate Eqn. (1) w.r.t. VIL and use
𝜕𝑉𝑂𝐻
𝜕𝑉𝐼𝐿
= -1
then we get Eqn. (2).
Solve (1) & (2) to get VIL & VOH
(1)

Evaluating VIH & VOL for DMD
Choose region IV to evaluate VIH &
VOL.
The main 4 steps in this region:
Check Md & Mu regions of operation .
IDSdLin = IDSusat.
Kd`(W/L)d(VGSd – VTd -
𝑽𝑫𝑺𝒅
𝟐
) VDSd =
𝑲`𝒖
𝟐
(W/L)u(VGSu – VTu)2
Differentiate Eqn. (3) w.r.t. VIH and use
𝜕𝑉𝑂𝐿
𝜕𝑉𝐼𝐻
= -1
then we get Eqn. (4).
Solve (3) & (4) to get VIH & VOL
(3)

Evaluating NMs for DMD
Finally NMs can be evaluated as
follows:
NML = VIL - VOL.
NMH = VOH – VIH.

Solved Example
For a DMD inverter with VTd = 1V, VTu
= - 3V, (W/L)d = 2, (W/L)u = ½, Ku` =
Kd` = 20 μA/V2. Determine:
NML, VIL.
NMH, VOH.
Solution
➢VIL = 1.67 V
➢VOH = 4.68 V
➢VOL = 0.86 V
➢VIH = 2.73 V
➢NML = VIL – VOL = 0.81V
➢NMH = VOH – VIH = 1.95V

Chapter (5)
Rise Time & Fall Time
Prepared by
Technology

Outlines
Dynamic Behavior of Inverters.
Switching Frequency & Propagation Delay
Time.
Dynamic Power Dissipation.
Evaluating tr & tf for CMOS Inverter.

Dynamic Response
Rise Time (tr or tLH): It is the time required for
the output voltage to change from 10% of VDD
to 90% of VDD.
Fall Time (tf or tHL): It is the time required for
the output voltage to change from 90% of VDD
to 10% of VDD.

Switching Frequency &
Propagation Delay Time

Switching Frequency
Switching Frequency (f or fs): For any inverter
the switching frequency could be evaluated as
follows:
f =
1
𝑡𝑟+𝑡𝑓
If tr = tf; then:
f =
1
2𝑡𝑟
=
1
2𝑡𝑓

Propagation Delay Time
Propagation Delay Time (tp): For any inverter
the propagation delay time is a measure of
average rate through the gate or the difference
time between the input & output signals
reaching V50%:
V50% = (VOH + VOL)/2
Then:
tp=
1
2
(tr + tf)

Dynamic Power Dissipation
Thus, every time a logic gate goes
through a complete switching cycle, the
transistors within the gate dissipate an
energy equal to ETD. Logic gates
normally switch states at some relatively
high frequency (switching events/second),
and the dynamic power PD dissipated by
the logic gate is then:
PD = CL VLogic
2 f
Where: CL is the Load capacitance.
VLogic= (V90% - V10%) ~ VDD

Evaluating tr & tf for CMOS
Inverter

Method(1): Charging/Discharging Method
For Mn (off) & Mp (saturation) CL charges
through Mp:
tr =
3𝐶𝐿
𝛽𝑝𝑉𝐷𝐷
For Mp (off) & Mn (saturation) CL
discharges through Mn:
tf =
3𝐶𝐿
𝛽𝑛𝑉𝐷𝐷
tr = 2.5 tf

Method(2): Average Current Method
Put Vi = VDD (Mn on & Mp off):
IDS = - CL
𝑑𝑉𝑜
𝑑𝑡
Iavg = CL
𝑉90%−𝑉10%
𝑡𝑓
Then; tf = CL
𝑉90%−𝑉10%
𝐼𝑎𝑣𝑔
Iavg =
1
2
[IDS(Vi = VDD, Vo = 0.9VDD) + IDS(Vi =
VDD, Vo = 0.1VDD)
Assume tr = tf.

Solved Example
For a CMOS inverter with VDD = 5V, CL =
1pF, VTn = 1V, (W/L)n = 10, Kn` = 20μA/V2.
Determine:
The fall time.
The maximum switching frequency.
Solution
Using average current method, we get that:
Iavg = 0.9875 mA.
tf = 4.05 nSec.
fmax = 1/(2*4.05*10-9) = 0.123 GHz.

Chapter (6)
Design Rules
Prepared by
Technology

Outlines
Electrical Design Rules.
Mandatory ‫إلزامية‬
) )Design Rules.
Geometrical Design Rules.
Layout.
Stick Diagram.

Electrical Design Rules (EDRs)
A set of guidelines that specifies the
electrical properties of transistor (as
α, β, VDD, VT, gm, etc).

Mandatory Design Rules (MDRs)
A set of guidelines that specifies the distance
between the mask & the substrate of transistor
in fabrication process.

Geometrical Design Rules (GDRs)
A set of guidelines that specifies the
minimum feature size as well as the
minimum distance between any 2
features.
The feature may be; Gate, Source,
Drain, Contact, or Metal.

How to determine the dimensions?
Method (1): Using Specific Values:
Dimensions are expressed in m, mm, μm,
or nm.
Method (2): Using Scalable Quantities:
Dimensions are expressed in terms of λ (1/2
minimum allowable channel length or ½
CMOS Technology).

GDRs to sketch Layout
Min poly (Gate) size = 2λ.
Min distance between poly & poly = 2 λ.
Contact size = 2 λ x 2 λ (Fixed Size).
Min distance between 2 contacts = 2 λ.
Min distance between poly & contact = 2 λ.
Min distance between contact & diffusion layer (Source or
Drain) edge = 1 λ.
For 2 diffusion layers serial or parallel + No outline connection +
the same transistor type; No need for contact or metal in this
case.
Colors Rule:
Poly → red (NMOS or PMOS)
S, D (NMOS) → green
S, D (PMOS) → brown
Contact → black
Metal → blue
Via → white

Contact versus Via
Contact: is a connection between metal
and any other feature.
Via: is a connection between metal &
metal.
X

Single NMOS Layout
Schematic Diagram:
Layout:
G
D s
i/p o/p
i/p o/p

CMOS TG Switch Layout
Schematic Diagram:
Layout:
IN OUT
N-Well

CMOS Inverter Layout
Schematic Diagram:
Layout:
Vout
Vin
VDD
GND
N-Well

DMD Inverter Layout
Schematic Diagram:
Layout:
Vout
Vin
VDD
GND

EMD Inverter Layout
Schematic Diagram:
Layout:
Vout
Vin
VDD
GND

What is Stick Diagram
Dimensionless layout entities.
Abstract version of layout.
Only final topology is important.
Final layout could be produced using
compaction program.

GDRs to sketch Stick Diagram
Lines drawn in colors to determine
particular layers.
Lines drawn without thickness.
We must use colored pencils.
Applied dimensions are relative.
Lines of the same color mustn’t be
crossed.
Colors rule is the same as that of layout.

Stick Diagram for CMOS Inverter
Schematic Diagram:
Stick Diagram:

Stick Diagram for 3-i/p NAND Gate using CMOS
Inverter
Schematic Diagram:
Stick Diagram:
n1
n2
Y =
n1 n2

Stick Diagram for Y = 𝐴𝐵 + 𝐶
Schematic Diagram: Stick Diagram:

Stick Diagram for Y = 𝐴 + 𝐵 + 𝐶 . 𝐷
Schematic Diagram: Stick Diagram:
n1 n1
n2 n3
Y Y
Y
VDD
GND
A B C D

Stick Diagram for
Y = 𝐴 + 𝐵). 𝐶 + 𝐹 + (𝐷. 𝐸
Schematic Diagram:

Stick Diagram for
Y = 𝐴 + 𝐵). 𝐶 + 𝐹 + (𝐷. 𝐸
Stick Diagram:
n1 n1
n4 n3 Y
Y
VDD
GND
A B C F E D
n4 n5 n5
Y
n2

IC_Lectures_Updated.pdf

More Related Content

Similar to IC_Lectures_Updated.pdf (20)

Recently uploaded (20)

IC_Lectures_Updated.pdf