MOSFET: METAL–OXIDE–SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
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The document discusses the metal-oxide-semiconductor field-effect transistor (MOSFET). It covers MOSFET operation as capacitors, energy band diagrams under different biases, depletion layer thickness, surface charge density, flat-band and threshold voltages, ideal C-V characteristics, and the effects of frequency and oxide/interface charges. The key concepts covered include accumulation, depletion, and inversion layers in MOS capacitors and how they affect the capacitance.
MOSFET: METAL–OXIDE–SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
- 1. MOSFET: METAL–OXIDE–SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 15th June 2020 Manmohan Dash
- 2. ❖ MOSFET as Capacitors ❖ Energy-Band Diagrams ❖ Depletion Layer Thickness ❖ Surface Charge Density ❖ Flat-Band Voltage ❖ Threshold Voltage Ideal C–V Characteristics ❖ Frequency Effects ❖ Fixed Oxide Charge Effects ❖ Interface Charge Effects ❖ MOSFET Structures ❖ Current–Voltage Relationship Concepts We will discuss
- 3. Introduction ❖ Transistor: multijunction semiconductor device, capable of current gain, voltage gain, and signal power gain ❖ Basic transistor action: control of current at one terminal by voltage applied across other two terminals
- 4. Introduction ❖ Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET): one of the two major types of transistors ❖ MOSFET: used extensively in digital circuit applications ❖ Small size: millions of devices can be fabricated in a single integrated circuit
- 5. CMOS ❖ n-channel and p-channel MOSFET: complementary configurations of MOS transistors. ❖ Versatile electronic circuit design: when the 2 types of devices are used in the same circuit. ❖ CMOS circuits: uses complimentary MOS configurations in a device
- 6. Two terminal MOS structure ❖ MOS capacitor: is the heart of MOSFET ❖ Metal may be Al, some other metal, or high- conductivity polycrystalline Si can be deposited on oxide; the term metal is still used Parameter tox is thickness, ox is permittivity of oxide
- 7. ❖ Physics of the MOS structure: explained by parallel- plate capacitor ❖ top plate at –ve voltage wrt bottom plate, separated by insulator material ❖ -ve charge exists on top plate, +ve charge on bottom plate, electric field induced between plates Two terminal MOS structure
- 8. Simple parallel plate capacitor ❖ Capacitance per unit area: C’=/d ❖ Magnitude of charge per unit area on either plate: Q’=C’V ❖ Magnitude of electric field: E=V/d
- 9. MOS structure as capacitor ❖ Top metal gate is at –ve voltage wrt semicon substrate ❖ –ve charge on top of metal plate, E-field induced in the direction shown ❖ If E-field penetrates into semicon, majority carrier holes experience force toward ox–semicon interface MOS capacitor with p-type semicon substrate
- 10. Accumulation layer of holes ❖ Accumulation layer of holes at ox–semicon junction ❖ Corresponds to +ve charge on bottom “plate” of MOS capacitor Equilibrium distribution of charge in p-type MOS capacitor with –ve Gate voltage
- 11. Negative space-charge or depletion layer ❖ +ve charge on top metal plate, induced E-field in opposite direction to that of –ve Gate voltage ❖ If E-field penetrates semicon, majority carrier holes experience force away from ox–semicon interface MOS capacitor with +ve Gate voltage
- 12. Negative space-charge or depletion layer ❖ -ve space charge region is created due to fixed ionized acceptor atoms ❖ -ve charge in induced depletion region corresponds to –ve charge on bottom “plate” of MOS capacitor equilibrium distribution of charge in MOS capacitor with +ve Gate voltage
- 13. Ideal Energy-Band (EB) Diagrams MOS capacitor (p-type substrate) for zero Gate bias ❖ flat EB, as no net charge in semicon, condition known as flat band
- 14. ❖ Valence Band (VB) edge closer to Fermi Level (FL: EF) at ox–semicon interface than in bulk material, hence an accumulation of holes ❖ Surface appears more p- type than bulk material ❖ FL (EF) is constant in semicon as MOS system is in thermal equilibrium and no current through the oxide Ideal Energy-Band (EB) Diagrams MOS capacitor (p-type substrate) for -ve Gate Bias
- 15. ❖ CB and VB edges bend, indicating space charge region similar to that in p-n junction ❖ CB and intrinsic FL (EFi) move closer to FL (EF) ❖ Induced space charge width xd Ideal Energy-Band (EB) Diagrams MOS capacitor (p-type substrate) for +ve Gate Bias
- 16. ❖ Induced E-field increases induced charges, larger -ve charge means larger induced space charge region and more band bending ❖ At surface intrinsic FL (EFi) is below FL, CB close to FL, VB close to FL in bulk semicon ❖ interface: surface in semicon is now n type, p- type surface of semicon has been inverted to n-type Ideal Energy-Band (EB) Diagrams So, inversion layer of e- created MOS capacitor (p-type substrate) for large +ve Gate Bias
- 17. MOS capacitor (n-type substrate) for +ve and -ve Gate Bias MOS capacitor with n- type semicon substrate develops accumulation layer and space charge layer in the same manner as p-type substrate MOS MOS structure with n type substrate
- 18. Same type of EB diagrams can be constructed for MOS capacitor with n- type semicon substrate Ideal Energy-Band (EB) Diagrams
- 19. ❖ fp; difference (in V) b/w EFi and EF, Na is acceptor doping concn, ni is intrinsic carrier concn ❖ s; surface potential, difference (in V) b/w EFi in bulk semicon and EFi at surface, i.e. potential difference across space charge layer Depletion Layer Thickness space charge width (xd) similar to 1- sided p-n junction width space charge region in p-type semicon substrate
- 20. ❖ EF at surface far above EFi, also EF below EFi in bulk semicon, e- concn at surface same as hole concn in bulk material. Known as threshold inversion point ❖ Applied gate voltage (VG) creating this condition is known as threshold voltage (VT). When VG > VT, CB bends slightly closer to EF, change in CB at surface is slight fn of VG ❖ But e- concn at surface is expon fn of surface potential (s). Few (kT/e) volts increase in s, changes e- concn by orders of magnitude Energy Bands at Threshold Inversion xd changes only slightly, space charge region has reached maximum width xdT When s = 2fp
- 21. Threshold inversion point space charge region in n-type semicon substrate Maxm induced space charge region width versus semicon doping
- 22. ❖ e- concn in CB can be written ❖ For p-type semicon substrate, e- inversion charge density (ns) can be written ❖ ∆s is excess surface potential over threshold inversion value s=2p, nst is e- charge density at threshold inversion Surface Charge Density
- 23. e- inversion charge density ns as a function of surface potential s when threshold inversion charge density nst is 1016 cm-3 ❖ ns increased by factor of 10 with 60-mV increase in surface potential s ❖ ns increases rapidly with small increases in s ❖ This means space charge width reached a maxm value Sensitivity of Surface Charge Density
- 24. ❖ energy levels in the metal, SiO2, and Si relative to vacuum level ❖ metal work function is m and e- affinity is , oxide e- affinity is i, for SiO2, i = 0.9 V Work Function Differences in MOS, before contact
- 25. ❖ FL (EF) is constant in the entire system at thermal equilibrium ❖ ’ m is modified metal work function i.e. potential required to inject an e- from metal into CB of oxide. ’ is defined as modified e- affinity ❖ Voltage Vox0 is potential drop across oxide for VG = 0 and not necessarily zero because of the difference b/w m and ❖ The potential s0 is surface potential for VG = 0 EB diagram of entire MOS structure with zero gate voltage (VG) Work Function Differences in MOS, after contact
- 26. By summing energies from FL (EF) on metal side to FL (EF) on semicon side, we have Work Function Differences in MOS We define metal–semicon work function difference
- 27. Degenerately doped polysilicon; n+ case, we assume EF = Ec EB diagram; MOS capacitor with n+ polysilicon gate and p-type substrate Work Function Differences in MOS Experimental value will be slightly different as EF will be 0.1 to 0.2 V above Ec
- 28. Degenerately doped polysilicon; p+ case, we assume EF = Ev EB diagram; MOS capacitor with p+ polysilicon gate and p-type substrate Work Function Differences in MOS Experimental value will be slightly different as EF will be 0.1 to 0.2 V below Ev
- 29. EB diagram and work function difference; n-type substrate, –ve gate bias Work Function Differences in MOS
- 30. ❖ VFB; applied gate voltage such that there is no band bending in semicon ❖ There is zero net space charge in this region. ❖ Because of work function difference and possible trapped charge in oxide, voltage across oxide for this case is not necessarily zero FLAT BAND (FB) VOLTAGE a net fixed charge density usually +ve, may exist in the insulator fairly close to the ox–semicon interface
- 31. trapped charge per unit area Q’ss, is located in oxide directly adjacent to ox–semicon interface, given in terms of # of electronic charges per unit area FLAT BAND (FB) VOLTAGE For 0 applied gate voltage (VG = 0): When (VG) is applied, the potential drop across oxide and surface potential will change
- 32. There is zero net charge in the semicon, we assume an equivalent fixed surface charge density in oxide Charge density on metal is Q’m, related by voltage across oxide Vox and capacitance Cox also from charge neutrality we have FLAT BAND (FB) VOLTAGE charge distribution in the MOS structure for the flatband condition In flat-band condition, surface potential s is zero
- 33. ❖ Threshold voltage VT; defined as applied gate voltage (VG) required to achieve threshold inversion point ❖ Threshold inversion point; defined as the condition when surface potential is s = 2fp (p-type semicon) and s = 2fn (n-type semicon ) ❖ VT is expressed in terms of electrical and geometrical properties of MOS capacitor THRESHOLD VOLTAGE
- 34. Space charge width has reached its maximum value We assume an equivalent oxide charge; Q’ss and +ve charge on the metal gate at threshold; Q’mT We neglect the inversion layer charge We apply conservation of charge THRESHOLD VOLTAGE Charge distribution in a MOS capacitor (p-type substrate at threshold inversion point) Q’SD(max) is magnitude of maxm space charge density per unit area of depletion region
- 35. At threshold, VG = VTN, where VTN is threshold voltage, that creates e- inversion layer charge THRESHOLD VOLTAGE EB diagram of the MOS system with applied +ve gate voltage For a given semicon and oxide material, and gate metal, VT is a function of semicon doping, oxide charge and oxide thickness
- 36. ❖ -ve threshold voltage for p-type substrate implies a depletion mode device, –ve voltage must be applied to gate in order to make inversion layer charge equal to zero ❖ +ve gate voltage will induce larger inversion layer charge ❖p-type semicon must be somewhat heavily doped in order to obtain enhancement mode device THRESHOLD VOLTAGE Threshold voltage VTN as a function of the acceptor doping concn for various +ve oxide charge values
- 37. ❖ For n-type semicon substrate, –ve gate voltage induces inversion layer of holes at ox–semicon interface, VT for this case is given by ❖ always an enhancement mode device, for all values of +ve oxide charge ❖ As Q’ss charge increases, VT becomes more -ve, it takes a larger applied VG to create inversion layer of holes at ox– semicon interface THRESHOLD VOLTAGE VT of p-channel MOSFET vs n- type substrate doping concn for various values of oxide trapped charge (tox = 500 Å, Al gate
- 38. ❖ Capacitance: C=dQ/dV, dQ is magnitude of differential change in charge on one plate, as a function of differential change in voltage dV across the capacitor ❖ C is small-signal or ac parameter; measured by superimposing a small ac voltage on an applied dc gate voltage. C is measured as a fn of applied dc gate voltage ❖ We will discuss ideal C–V characteristics then discuss some deviations ❖ We will assume zero charge trapped in oxide and no charge trapped at ox–semicon interface (initially) ❖ We will discuss 3 operating conditions: accumulation, depletion, inversion C-V CHARACTERISTICS
- 39. ❖ Fig 1; EB diagram of MOS capacitor with a p-type substrate with a -ve gate voltage, inducing an accumulation layer of holes in semicon at ox–semicon interface ❖ Fig 2; small differential change in V across MOS structure >> differential change in charge on metal gate and hole accumulation charge, at edges of oxide, as in a ||-plate capacitor ❖ C’; capacitance per unit area for accumulation mode, same as oxide capacitance, C’(acc) = Cox = ox/tox CAPACITANCE AT ACCUMULATION
- 40. ❖ Fig 1: EB diagram when a small +ve V is applied to gate, inducing a space charge region in semicon ❖ Fig 2; charge distribution, oxide C and C of depletion region are in series. A small differential change in V across the capacitor makes a differential change in space charge width ❖ As space charge width increases, the total capacitance C’(depl) decreases CAPACITANCE AT DEPLETION
- 41. ❖ Threshold inversion point; maxm depletion width reached, essentially zero inversion charge density, yields a minm capacitance ❖ Fig 1; EB diagram for inversion, in ideal case, small incremental change in V across MOS capacitor causes differential change in inversion charge density, xd does not change ❖ Fig 2; If inversion charge can respond to the change in capacitor V as indicated, then capacitance is just the oxide capacitance CAPACITANCE AT INVERSION
- 42. ❖ 3 dashed segments correspond to 3 components Cox, C’SD, and C’min, solid curve is ideal net capacitance ❖ Moderate inversion; transition region b/w point when only space charge density changes with VG and when only inversion charge density changes with VG ❖ FB occurs b/w accumulation and depletion, capacitance at FB is given below, FB capacitance is function of oxide thickness and semicon doping IDEAL CV CHARACTERISTICS P type substrate N type substrate
- 43. ❖ There are 2 sources of e- that produce a change in inversion charge density ❖ 1st source; diffusion of minority carrier e- from p-type substrate, 2nd source; thermal generation of EHP, both within space charge region, both like a p-n junction generating reverse-biased saturation current ❖ e- are generated at a particular rate, so e- concn in inversion layer can’t change instantaneously. If ac V across MOS capacitor changes rapidly, inversion charge can’t respond, C–V characteristics will be a fn of frequency of ac signal used CV CHARACTERISTICS; FREQUENCY EFFECTS
- 44. ❖ In very high frequency limit, inversion layer charge won’t respond to differential change in capacitor V ❖ differential change in charge occurs at the metal and in space charge width in the semicon CV CHARACTERISTICS; FREQUENCY EFFECTS charge distribution in MOS capacitor with a p-type substrate
- 45. ❖ Fixed oxide charge and ox–semicon interface charges change C–V characteristics ❖ Fixed oxide charge affects VT, and FB voltage ❖ FB voltage shifts to more -ve voltages for a +ve fixed oxide charge, oxide charge is not a fn of VG, so curves show a || shift with oxide charge, and ideal characteristics shape of C–V curves remains same FIXED OXIDE CHARGE AND INTERFACE CHARGE EFFECTS Q’ss is equivalent fixed oxide charge and ms is metal–semicon work function difference high-frequency characteristics of a MOS capacitor with p-type substrate for several values of fixed +ve oxide charge
- 46. ❖ C–V characteristics can be used to determine equivalent fixed oxide charge. For a given MOS structure ms and Cox are known, ideal FB voltage and capacitance can be calculated. ❖ The experimental value of FB voltage can be measured from C–V curve, value of fixed oxide charge can be determined ❖ C–V measurements are a valuable diagnostic tool to characterize a MOS device. This characterization is especially useful in study of radiation effects on MOS devices APPLICATION OF CV CHARACTERISTICS
- 47. ❖ Periodic nature of semicon is abruptly terminated at interface, so electronic energy levels are allowed in the forbidden bandgap, these allowed states are known as interface states ❖ Charge can flow between semicon and interface states, in contrast to the fixed oxide charge, net charge in interface states is a fn of position of Fermi Level in the bandgap INTERFACE STATES EB diagram of a semicon at ox–semicon interface
- 48. ❖ Acceptor states in upper half and donor states in lower half of bandgap ❖ Acceptor state; neutral if FL is below the state, -ve charged if FL is above the state ❖ Donor state; neutral if FL is above the state, +ve charged if FL is below the state ❖ So charge of interface states is a fn of VG applied across MOS capacitor INTERFACE STATES
- 49. ❖ top fig; EB diagram in p-type semicon of MOS capacitor in accumulation condition, net +ve charge trapped in donor states ❖ mid fig; FL corresponds to intrinsic FL at surface; all interface states are neutral, bias condition known as midgap ❖ bottom fig; condition at inversion, net -ve charge in acceptor states INTERFACE STATES
- 50. ❖ Net charge in interface states changes from +ve to -ve as VG goes from accumulation, depletion, to inversion condition ❖ For fixed oxide charge; C–V curves shift in -ve VG direction ❖ For interface states; amount and direction of shift change, as we go through VG, amount and sign of interface trapped charge change. C– V curves are “smeared out” INTERFACE STATES amount of smearing out can be used to determine the density of interface states
- 51. ❖ Current in a MOSFET; due to flow of charge in inversion layer or channel region adjacent to ox–semicon interface ❖ We’ve discussed creation of inversion layer charge in enhancement-type MOS capacitors. In depletion-type devices a channel already exists at zero gate voltage ❖ There are 4 basic MOSFET device types BASIC MOSFET OPERATION 1. n-channel enhancement mode MOSFET 2. n-channel depletion mode MOSFET 3. p-channel enhancement mode MOSFET 4. p-channel depletion mode MOSFET
- 52. ❖ A +ve VG induces e- inversion layer, this “connects” n-type Source (S) and n-type Drain (D) regions ❖ S terminal is source of carriers that flow through channel to D terminal, e- flow from source to drain, conventional current enters D and leaves S MOSFET STRUCTURE n-channel enhancement mode MOSFET Circuit symbol
- 53. ❖ n-channel region exists under oxide with 0 V applied to Gate (G), VT of MOS device with p- type substrate may be - ve; so an e- inversion layer already exists with VT = 0 ❖ n-channel shown can be e- inversion layer or an doped n region MOSFET STRUCTURE n-channel depletion mode MOSFET
- 54. ❖ p-channel enhancement mode; -ve VG must be applied to create an inversion layer of holes this “connects” p-type S and D regions ❖ holes flow from S to D, conventional current enters S and leaves D ❖ A p-channel region exists in depletion mode device even with zero VG MOSFET STRUCTURE p-channel depletion p-channel enhancement
- 55. ❖ G to S voltage less than VT and very small D to S voltage, S and substrate/body (B) terminals are held at ground potential ❖ With this configuration, there is no e- inversion layer, D to B p- n junction is reverse biased, and D current is zero (disregarding p-n junction leakage currents) C-V RELATIONSHIP n-channel enhancement mode MOSFET (VGS<VT)
- 56. ❖ With applied gate voltage (VGS > VT) e- inversion layer is created so when a small D voltage is applied, the e- in inversion layer flows from S to +ve D terminal ❖ Conventional current enters D terminal and leaves S terminal ❖ In this ideal case, there is no current through oxide to G terminal C-V RELATIONSHIP n-channel enhancement mode MOSFET (VGS>VT)
- 57. ❖ For small VDS values, channel region has characteristics of a resistor, so we can write ID = gd VDS, gd is defined as channel conductance when VDS → 0, it is given by gd = (W/L)n|Q’n| where n is mobility of e- in inversion layer and |Q’n| is magnitude of inversion layer charge per unit area ❖ inversion layer charge; fn of G voltage, so basic MOS transistor action is modulation of channel conductance by G voltage, which in turn, determines D current C-V RELATIONSHIP We assume here mobility is constant
- 58. ❖ When VGS < VT, D current is zero. As VGS becomes larger than VT, channel inversion charge density increases, which increases channel conductance ❖ Larger value of gd produces larger initial slope of ID versus VDS characteristic C-V RELATIONSHIP The ID versus VDS characteristics, for small values of VDS
- 59. ❖ Thickness of inversion channel layer qualitatively indicates relative charge density ❖ This is essentially constant along entire channel length for this case C-V RELATIONSHIP Basic MOS structure when VGS > VT and VDS voltage is small and corresponding ID vs VDS curve
- 60. As D voltage increases, voltage drop across oxide near D terminal decreases, so induced inversion charge density near D decreases, incremental conductance of channel at D decreases, so slope of ID vs VDS curve decreases C-V RELATIONSHIP When VDS increases slope of curve decreases
- 61. When VDS increases until potential drop across oxide at D terminal is equal to VT, induced inversion charge density is zero at D terminal At this point, incremental conductance at D is zero, so slope of ID vs VDS curve is zero C-V RELATIONSHIP VGS -VDS(sat) = VT VDS(sat) is the D to S voltage producing zero inversion charge density at the D terminal VDS(sat) = VGS -VT
- 62. When VDS becomes larger than VDS(sat), the point in channel at which inversion charge is zero moves toward S terminal In this case, e- enter channel at S, travel through channel toward D, and at the point where charge goes to zero, e- are injected into space charge region where they are swept by E-field to D contact C-V RELATIONSHIP If change in channel length L is small compared to original length L, D current is constant for VDS > VDS(sat). Region of ID vs VDS characteristic is known as saturation region
- 63. When VGS changes, ID vs VDS curve changes We saw if VGS increases, initial slope of ID vs VDS increases We also saw that VDS(sat) is a function of VGS We can generate the family of curves seen C-V RELATIONSHIP Family of ID vs VDS curves for n- channel enhancement mode MOSFET VDS(sat) = VGS -VT
- 64. If n-channel region is an induced e- inversion layer created by metal– semicon work fn difference and fixed charge in oxide, I-V characteristics are exactly same as what we discussed, except VT is a -ve quantity C-V RELATIONSHIP n-channel depletion mode MOSFET
- 65. C-V RELATIONSHIP n-channel depletion mode MOSFET ID vs VDS curves A -ve G voltage induces space charge region under oxide, reduces thickness of n-channel region, reduced thickness decreases channel conductance, this reduces D current A +ve G voltage creates e- accumulation layer, this increases D current. Basic requirement for this device: channel thickness tc must be < maxm induced space charge width, in order to be able to turn the device off n-channel = n-type semicon