Session 08 v.3
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This document provides an outline of topics covered in a session on digital design using VHDL, including: 1) Introduction of arithmetic circuits like adders and multipliers using operators like + and *. 2) Discussion of projects involving arithmetic functions like addition and multiplication. 3) An evaluation test at the end with 50 questions to be completed in 30 minutes.
Session 08 v.3
- 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Eight » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
- 2. about Start Group • Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Eight 2
- 3. Outline • Click to edit Master Evaluation Test – Second level • Third level text styles Arithmetic circuits Projects Discussion 8 – Fourth level » Fifth level Session Eight 3
- 4. Outline • Click to edit Master Evaluation Test text styles – Second level Arithmetic circuits • Third level Projects Discussion – Fourth level » Fifth level Session Eight 4
- 5. Evaluation Test • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Answer all questions in the following paper Questions : 50 Question Time : 30 minute Full Mark : 100 degree Session Eight 5
- 6. Outline • Click to edit Master Evaluation Test text styles – Second level Arithmetic circuits • Third level Projects Discussion – Fourth level » Fifth level Session Eight 6
- 7. Unsigned and Signed Types • Click toDefinition Masterexactly likestyles vector should be treated as a edit Behave STD_LOGIC_VECTOR textwhether a given They determine signed or unsigned number. – Second level • Third level Package ieee.numeric_std.all – Fourth level Unsigned 0 to 2N - 1 » Fifth level Signed - 2(N-1) to 2(N-1) – 1 2's Complement number Example signal A : unsigned(3 downto 0) ; signal B : signed(3 downto 0) ; A <= "1111" ; -- 15 B <= "1111" ; -- -1 Session Eight 7
- 8. Unsigned and Signed Types • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Ambiguous Expressions Ambiguous Z_signed <= A_signed + "1010"; Error -6 or 10 Solution Z_signed <= A_signed + signed("1010“); Session Eight 8
- 9. Adders with Carry In • Click to Result MasterB(3:0) + Carry-In edit A(3:0) + text styles – Second level Algorithm A(3:0) , ‘1’ 011 1 011 1 B(3:0) , Carry-In 001 1 001 0 • Third level -------------------- ------- cin =1 ------- cin =0 Result(4:1) 101 0 100 0 – Fourth level CodeFifth level » Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal cin : std_logic; ..... Z <= (A & ’1’) + (B & cin); Y <= Z(4 downto 1 ); Session Eight 9
- 10. Adders with Carry Out • Click to Result MasterCarry-Out styles edit Result + text – Second level Algorithm ‘0’ A(3:0) 0 111 ‘0’ B(3:0) 0 100 • Third level --------------------- ------- Cout Result(3:0) 1 011 – Fourth level CodeFifth level » Signal A,B,Y : unsigned (3 downto 0); Signal Z : unsigned (4 downto 0); Signal co : std_logic; ….. Z <= (’0’ & A) + (’0’ & B); Y <= Z(3 downto 0 ); Co <= Y(4); Session Eight 10
- 11. Type Conversions • Click to edit Master Unsignedstyles Conversion Signed & text (elements) Std_Logic Signed & Unsigned Std_Logic_Vector – Second level Signed & Unsigned Std_Logic_vector Integer Integer • Third level – Fourth level Conversion functions located in Numeric_Std » Fifth level Session Eight 11
- 12. Unsigned.Signed Std_Logic • Click to edit Master text styles Conversions Converted automatically. – Second A_std <= J_unsigned(0); Example level • Third B_std <= K_signed(7); level --not preferred – Fourth level L_unsigned(0) <= C_std; » Fifth level M_signed(2) <= N_std(2); Session Eight 12
- 13. Unsigned.Signed Std_Logic_vector • Click to edit Master text styles Conversions Use type casting to convert equal sized arrays – Second level Example A_std <= std_logic_vector( B_unsigned ) ; • Third level C_std <= std_logic_vector( D_signed ) ; – Fourth level<= unsigned( H_std ) ; G_unsigned » Fifth level J_signed <= signed( K_std ) ; Session Eight 13
- 14. Unsigned.Signed Integer • Click to edit Master text styles Conversions Use conversion functions – Second level Example Signal A,B : integer; • Third level Signal A_unsigned : unsigned(7 downto 0); Signal B_signed : signed(7 downto 0); – Fourth level … A <= TO_INTEGER ( A_unsigned ) ; » Fifth level B <= TO_INTEGER ( B_signed ) ; A_unsigned <= TO_UNSIGNED ( A, 8) ; B_signed <= TO_SIGNED ( B, 8) ; Data <= ROM(( TO_INTEGER( Addr_uv)); Session Eight 14
- 15. Std_logic_vector Integer • Click to edit Master text stylesNeeds 2 steps. Conversions Use conversion functions + type casting i.e. – Second Signal A,B Example level : integer; Signal A_std : std_logic_vector (7 downto 0); • Third level Signal B_std : std_logic_vector (7 downto 0); …. – Fourth level unsigned( A_std )); A <= to_integer( B <= to_integer( signed( B_std )); » Fifth level A_std <= std_logic_vector( to_unsigned( A, 8 )); B_std <= std_logic_vector( to_signed( B, 8 )); Session Eight 15
- 16. • Click to edit Master text styles Less Errors ; VHDL is Strongly typed <= – Second level • Third level – Fourth level Strong Typing Strong Error Checking Built into the Compiler » Fifth level Less debugging. Without VHDL, you must have a good Testbench+ lots of time to catch your errors. You may notice that Verilog is much more easier than VHDL. Session Eight 16
- 17. Multiplication and Division • Click to edit Master text styles Operators / mod rem ** – SecondConstant Signal * level Z_unsigned <= A_unsigned * 2 ; • Third level Size of result = 2 * size of input signal – Fourth level Signal* » Fifth level A_unsigned : unsigned (7 downto 0); Signal Signal Signal B_unsigned : unsigned (7 downto 0); Signal Z_unsigned : unsigned (15 downto 0); Z_unsigned <= A_unsigned * B_unsigned ; Size of result = size of 1st signal + size of 2nd signal Synthesis / mod rem are not synthesis Session Eight 17
- 18. Example 31 Signed Adder • Click to edit Master text styles LIBRARY ieee ; USE ieee.std_logic_1164.all ; – Second level USE ieee.numeric_std.all ; --------------------------------------- • Third level ENTITY adder IS PORT ( Cin : – Fourth level; IN STD_LOGIC X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); » Fifth level S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS SIGNAL Xs,Ys : SIGNED(15 DOWNTO 0); SIGNAL Sum : SIGNED(15 DOWNTO 0); BEGIN Xs <= signed(X); Ys <= signed(Y); Sum <= Xs + Ys + Cin ; S <= std_logic_vector(Sum); END Behavior ; Session Eight 18
- 19. Not Recommended Signed Adder • Click to edit Master text styles LIBRARY ieee ; USE ieee.std_logic_1164.all ; – Second level USE ieee.std_logic_signed.all ; --------------------------------------- • Third level ENTITY adder IS PORT ( Cin : IN STD_LOGIC ; X, Y – Fourth level : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)) ; END adder ; » Fifth level --------------------------------------- ARCHITECTURE Behavior OF adder IS BEGIN S <= X + Y + Cin ; END Behavior ; Session Eight 19
- 20. Not Recommended Signed Adder • Click to edit Master text styles ENTITY adder16 IS – Second level PORT (X,Y: IN S : OUT INTEGER RANGE -32768 TO 32767 ; INTEGER RANGE -32768 TO 32767 ) ; • Third level END adder16 ; --------------------------------------- – Fourth level ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y»;Fifth level END Behavior ; Session Eight 20
- 21. Example 32 UnSigned Adder • Click to edit Master text styles LIBRARY ieee ; USE ieee.std_logic_1164.all ; – Second level USE ieee.numeric_std.all ; --------------------------------------- • Third level ENTITY adder IS PORT ( Cin : – Fourth level; IN STD_LOGIC X,Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); » Fifth level S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END adder ; --------------------------------------- ARCHITECTURE Behavior OF adder IS SIGNAL Xus,Yus : UnsIGNED(15 DOWNTO 0); SIGNAL Sum : UnSIGNED(15 DOWNTO 0); BEGIN Xus <= Unsigned(X); Yus <= Unsigned(Y); Sum <= Xus + Yus + Cin ; S <= std_logic_vector(Sum); END Behavior ; Session Eight 21
- 22. Example 33 Multiplier • Click to edit Master text styles LIBRARY ieee; USE ieee.std_logic_1164.all; – Second level USE ieee.numeric_std.all ; --------------------------------------- begin entity multiply is -- signed multiplication port( • Third level sa <= SIGNED(a); a : in STD_LOGIC_VECTOR(7 downto 0); sb <= SIGNED(b); – Fourth level b : in STD_LOGIC_VECTOR(7 downto 0); sc <= sa * sb; cu : out STD_LOGIC_VECTOR(15 downto 0); » Fifth level cs <= cs : out STD_LOGIC_VECTOR(15 downto 0)); STD_LOGIC_VECTOR(sc); end multiply; --------------------------------------- -- unsigned multiplication architecture rtl of multiply is ua <= UNSIGNED(a); ub <= UNSIGNED(b); SIGNAL sa: SIGNED(7 downto 0); uc <= ua * ub; SIGNAL sb: SIGNED(7 downto 0); cu <= SIGNAL sc: SIGNED(15 downto 0); STD_LOGIC_VECTOR(uc); SIGNAL ua: UNSIGNED(7 downto 0); end rtl; SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL uc: UNSIGNED(15 downto 0); Session Eight 22
- 23. Example 34 Half Adder • Click to edit Master text styles – Second level LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; • Third level --------------------------------------- ENTITY HALF_ADDER IS Generic (WIDTH – Fourth level 8 ); : INTEGER := PORT( A : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); » Fifth level B : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); P : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 ); G : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0 )); END HALF_ADDER; --------------------------------------- ARCHITECTURE RTL OF HALF_ADDER IS BEGIN P <= A XOR B; G <= A AND B; END; Session Eight 23
- 24. Example 35 Full Adder • Click to edit Master text styles LIBRARY ieee; – Second level USE ieee.std_logic_1164.all; --------------------------------------- ENTITY fullAdder IS • Third level PORT( In1, In2, CarryIn : IN std_logic; Sum : OUT std_logic; – Fourth level : OUT std_logic); CarryOut END fullAdder; » Fifth level --------------------------------------- ARCHITECTURE expr OF fullAdder IS signal temp : std_logic; BEGIN temp <= In1 XOR In2; Sum <= temp XOR CarryIn; CarryOut <= (In1 AND In2) OR (CarryIn AND temp); END expr; Session Eight 24
- 25. Lab 10 • Click to edit Master text styles Title: Goal: – Second level Using Arithmetic operators • Third level Multipliers Adders – Fourth level » Fifth level Session Eight 25
- 26. Lab 10 • Click to edit Master text styles – Second level Describe code performing this function • Third level C = A + B*2 – are of width = A,B and C Fourth level 16 signed bits » Fifth level C = B*A A,B and C are of width = 16 signed bits Session Eight 26
- 27. Outline • Click to edit Master Evaluation Test text styles – Second level Arithmetic circuits • Third level Projects Discussion – Fourth level » Fifth level Session Eight 27
- 28. Time for Your Questions • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Examples Exercises Labs 31-35 - 10 Session Eight 28
- 29. Take Your Notes Print the slides and take your notes here -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Second level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Third level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Fourth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- » Fifth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- Session Eight 29
- 30. See You Next Session .. Don’t miss • Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level Session Eight 30