Session 06 v.3
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The notes discuss modeling finite state machines (FSMs) in VHDL using different process styles: - One process describes the state register, state transitions, and output logic. It is easily described but has verbose syntax and one clock latency for outputs. - Two processes where the first describes the state register and the second describes the combinational logic. It is easier to debug and has more readable code but outputs are not registered and requires assigning next states and outputs for all cases. FSMs can be easily described with processes if certain synthesis rules are followed like describing state transitions in a process sensitive to clock and asynchronous reset.
![FSM in VHDL [Three Processes]
• Click to edit Master text styles
The “3 Processes, 1 Clocked + separate transitions/actions” style
– Second “Next State Logic”
1-Process modeling level
Next
State
Logic
• Third level State
2-Process modeling "Current State Registers"
– Fourth level Registers
Output
3-Process modeling» Fifth level
“Output Logic” Logic
Mealy machines
Inputs Next Present
Next Machine state Output Outputs
state
State State Logic
Logic Registers
Session Six 10](https://image.slidesharecdn.com/session06v-3-120802183727-phpapp01/85/Session-06-v-3-10-320.jpg)
![Start Notes [Synthesis Notes]
• Click to edit Master text styles
– Second level One process
Modeling FSM describes state register. state transaction and output logic.
• Third level Advantage : registered outputs
-FSMs Can Be Easily
– Fourth Disadvantage
Described With Processes. level
: verbose syntax.
poorly debugging
Synthesis Tools understand
» Fifth level one clock latency for outputs
FSMs if Certain Rules Are Two process
Followed. State transitions the first describes state register.
should be described in a the second combinatorial logic.
process sensitive to clock Advantage : easy to debugging.
and asynchronous reset simply and readable code.
signals only. Output Disadvantage : non registered outputs.
function described using needs assignment to next state and
rules for comb. outputs for all possible cases.
logic, concurrent
statements or a process
with all inputs in the
sensitivity list. Session Six 28](https://image.slidesharecdn.com/session06v-3-120802183727-phpapp01/85/Session-06-v-3-28-320.jpg)
![Start Notes [Synthesis Notes]
• Click to edit Master text styles
Three processes
– Second level one for state register.
one for next state logic
• Third level one for outputs
Advantage : easy to debugging.
– Fourth level simply and readable code.
» Fifth level
Disadvantage : non registered outputs.
redundant code.
Three processes
first for state register.
second for next state logic
third for synchronous outputs.
Advantage : fully synchronous.
readable code
easy for debugging.
• Disadvantage :one clock cycle latency for output assertion
Session Six 29](https://image.slidesharecdn.com/session06v-3-120802183727-phpapp01/85/Session-06-v-3-29-320.jpg)
Session 06 v.3
- 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Six » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
- 2. about Start Group • Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Six 2
- 3. Outline • Click to edit Master What is styles – Second level • Third level text FSM Vending Machine Example String Detector 6 – Fourth level » Fifth level Session Six 3
- 4. What is FSM • Click to edit Master text styles Any digital system consists of two part: Data – Second level part Data Part • for the processing of data. The ResponsibleThird level processing is done through some blocks Inputs Outputs – Fourth level such as (full adder, digital filter, decoder,…) » Fifth level Control part Controls Describes how and when these blocks will communicate with each other. The control part is generally described using a finite state machine. Control Part Session Six 4
- 5. What is FSM • Click to edit Master text styles Finite State Machine S1 – Second level FSM is simply a finite number of states that each state describes a certain set of control • are connected outputs thatThird level to the data part S3 S2 blocks. – Fourth level » Fifth level The transition between these states depends mainly on the inputs of the FSM. There are two main types of FSM: Moore FSM Mealy FSM S4 Session Six 5
- 6. What is FSM Assigning Moore Outputs • Click to edit Master text styles Use a combinational ‘process’ to model Output Logic Outputs are only dependent on the current state Output Inputs – SecondNext level Present Logic Next Machine state Output Outputs • Third level state State State Logic Logic Registers Outputs = f(State) – Fourth level » Fifth level Assigning Mealy Outputs Use a combinatorial ‘process’ to model Output Logic Outputs are dependent on the current state as well as the input Output Logic Next Present Outputs = f(Inputs, State) Inputs Next Machine state Output Outputs state State State Logic Logic Registers Session Six 6
- 7. What is FSM Moore FSM transition • Click to edit Master text condition 1 styles – Second level state 2 state 1 • Third level transition – Fourth level condition 2 » Fifth level Mealy FSM transition condition 1 / output 1 state 1 state 2 transition condition 2 / output 2 Session Six 7
- 8. What is FSM Example Detecting 10 sequence • Click to editS0: No Master text S1: “1” styles S2: “10” 0 1 – Second level elements observed observed Meaning of the of states: 1 sequence 0 • Third level S0 / 0 observed S1 / 0 S2 / 1 – Fourth level » Fifth level reset 0/0 1/0 1/0 S0: No S1: “1” elements observed Meaning S0 of the S1 of states: sequence observed reset 0/1 Session Six 8
- 9. What is FSM Example Detecting 10 sequence • Click to edit Master text styles – Second level clock • Third level 0 Fourth level – 1 0 0 0 input » Fifth level S0 S1 S2 S0 S0 Moore S0 S1 S0 S0 S0 Mealy Session Six 9
- 10. FSM in VHDL [Three Processes] • Click to edit Master text styles The “3 Processes, 1 Clocked + separate transitions/actions” style – Second “Next State Logic” 1-Process modeling level Next State Logic • Third level State 2-Process modeling "Current State Registers" – Fourth level Registers Output 3-Process modeling» Fifth level “Output Logic” Logic Mealy machines Inputs Next Present Next Machine state Output Outputs state State State Logic Logic Registers Session Six 10
- 11. Example 24 • Click to edit Master text styles Vending Machine Using Moore Machine (3 Processes) – Second level Specifications -Deliver package of gum after 0.75 LE deposited • Third level -Single coin slot for 0.25 LE and 0.50 LE – Fourth level » Fifth level Session Six 11
- 12. Example 24 • Click to edit Master text styles STEP I Understand the problem – Second levelLE Draw a block diagram N = 0.25 LE D = 0.50 • Third level – Fourth level N » Fifth level Coin Vending Open D Sensor Machine FSM reset Clk Session Six 12
- 13. Example 24 STEP II • Click to edit Master text styles Draw State Diagram Reset – Second level D S0 N • Third N = 0.25 LE D = 0.5 LE level – Fourth level S1 S6 D » Fifth level N D N S8 S7 S3 S2 D N open open open S5 S4 N Coin D Vending Open open open Sensor Machine FSM reset Clk Session Six 13
- 14. Example 24 • Click to edit Master text styles STEP III State Diagram Minimization Reset – Second level S0 • Third level N – Fourth level S1 D » Fifth level N D S2 N,D N S3 Coin Vending Open D Machine Sensor FSM open reset Clk Session Six 14
- 15. Example 24 STEP IV • Click to edit Master text styles VHDL CODE 1- FSM INTERFACE – Second level library • Third level IEEE; use IEEE.STD_LOGIC_1164.ALL; – Fourth level use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; » Fifth level entity vend_machine_moore is Port ( N : in STD_LOGIC; D : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; tank_open : out STD_LOGIC ); end vend_machine_moore; Session Six 15
- 16. Example 24 • Click to edit Master text styles STEP IV VHDL CODE Reset S0 – SecondSTATES 2- DEFINE level • Third level N architecture Behavioral of vend_machine_moore is type–states level Fourth is (s0,s1,s2,s3); S1 D signal n_state,p_state :states; Begin » Fifth level N .. D S2 N,D S3 open Session Six 16
- 17. Example 24 STEP IV • Click to edit Master text styles VHDL CODE Reset 3- Transition Process S0 – Second level • Third level transition :process(clk,reset) N begin – Fourth level S1 D if reset='1' then » Fifth level p_state <=s0 ; N elsif rising_edge(clk) then p_state <= n_state ; D S2 end if; end process transition; N,D S3 Inputs Next Present Next Machine state Output Outputs state State Logic State Logic open Registers Session Six 17
- 18. Example 24 next_state :process(N,D,p_state) • Click to edit Master text styles STEP IV VHDL CODE --p_state in list to trigger 4- Next State Logic --process if inputs are constants Reset – Second level begin S0 Responsible for case p_state is N • Third level generating the next when s0 => S1 D – Fourth level state logic. if N='1' then n_state <= s1; N » Fifth level elsif D='1' then D S2 n_state <= s2; N,D else n_state <= s0; S3 end if; .. open Inputs Next Present Next Machine state Output Outputs state State State Logic Logic Registers Session Six 18
- 19. Example 24 when s1 => if N='1' then STEP IV • Click to edit Master text styles VHDL CODE n_state <= s2; elsif D='1' then - Next State Logic n_state <= s3; Reset – Second level else S0 n_state <= s1; N • Third level end if; S1 D – Fourth level when s2 => if N='1' then N » Fifth level n_state <= s3; D S2 elsif D='1' then N,D n_state <= s3; S3 else open n_state <= s2; end if; when s3 => n_state <= s0; end case; end process next_state; Session Six 19
- 20. Example 24 output_logic :process(p_state) begin • Click to edit Master text styles STEP IV VHDL CODE case p_state is 5- Output Logic when s0 => Reset – Second level tank_open <='0'; S0 Responsible for when s1 => N • Third level generating Output tank_open <='0'; S1 D – Fourth level logic. when s2 => tank_open <='0'; N » Fifth level when s3 => D S2 tank_open <='1'; N,D end case; S3 end process output_logic ; end Behavioral; open Inputs Next Present Next Machine state Output Outputs state State State Logic Logic Registers Session Six 20
- 21. Lab 07 • Click to edit Master text styles Title: – Second level Machine Mealy Machine Vending Goal: • Third level Dealing with FSMs – Fourth level » Fifth level Session Six 21
- 22. Lab 07 Reset • Click to edit Master text styles String Detector – Second level S0 library IEEE; • Third level use IEEE.STD_LOGIC_1164.ALL; N, 0 use IEEE.STD_LOGIC_ARITH.ALL; – Fourth level use IEEE.STD_LOGIC_UNSIGNED.ALL; N/D, 1 » Fifth level D, 1 S1 D, 0 entity vend_machine_moore is Port ( N : in STD_LOGIC; N, 0 D : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; S2 tank_open : out STD_LOGIC ); end vend_machine_moore; Session Six 22
- 23. Lab 07 • Click to edit Master text styles String Detector – Second level architecture Behavioral of vend_machine_moore is type states is (s0,s1,s2); • Third level signal n_state,p_state :states; Reset Begin .. – Fourth level S0 transition » Fifth level :process(clk,reset) begin if reset='1' then N, 0 p_state <=s0 ; elsif rising_edge(clk) then N/D, 1 p_state <= n_state ; D, 1 S1 D, 0 end if; end process transition; N, 0 S2 Session Six 23
- 24. Lab 07 • Click to edit Master text styles String Detector next_state :process(N,D,p_state) begin – Second level case p_state is when s0 => • Third level if N='1' then tank_open <='0'; – Fourth level n_state <= s1; elsif D='1' then » Fifth level n_state <= s2; tank_open <='0'; else n_state <= s0; tank_open <='0'; end if; when s1 => if N='1' then n_state <= s2; tank_open <='0'; elsif D='1' then … Session Six 24
- 25. Lab 07 • Click to edit Master text styles String Detector n_state <= s0; – Second level tank_open <='1'; else n_state <= s1; • Third level tank_open <='0'; end if; when – Fourth level s2 => if N='1' level » Fifth then n_state <= s0; tank_open <='1'; elsif D='1' then n_state <= s0; tank_open <='1'; else n_state <= s2; tank_open <='0'; end if; end case; end process next_state; end Behavioral; Session Six 25
- 26. Exercise 08 Draw Moore and Mealy State diagram for string detector that detect 1110 sequence • Click to edit Master text styles – Second level • Third level 1 1 1 – Fourth level 0 » Fifth level Session Six 26
- 27. Lab 08 • Click to edit Master text styles Title: – Second level Machine String Detector State Goal: • Third level Dealing with FSMs – Fourth level » Fifth level Session Six 27
- 28. Start Notes [Synthesis Notes] • Click to edit Master text styles – Second level One process Modeling FSM describes state register. state transaction and output logic. • Third level Advantage : registered outputs -FSMs Can Be Easily – Fourth Disadvantage Described With Processes. level : verbose syntax. poorly debugging Synthesis Tools understand » Fifth level one clock latency for outputs FSMs if Certain Rules Are Two process Followed. State transitions the first describes state register. should be described in a the second combinatorial logic. process sensitive to clock Advantage : easy to debugging. and asynchronous reset simply and readable code. signals only. Output Disadvantage : non registered outputs. function described using needs assignment to next state and rules for comb. outputs for all possible cases. logic, concurrent statements or a process with all inputs in the sensitivity list. Session Six 28
- 29. Start Notes [Synthesis Notes] • Click to edit Master text styles Three processes – Second level one for state register. one for next state logic • Third level one for outputs Advantage : easy to debugging. – Fourth level simply and readable code. » Fifth level Disadvantage : non registered outputs. redundant code. Three processes first for state register. second for next state logic third for synchronous outputs. Advantage : fully synchronous. readable code easy for debugging. • Disadvantage :one clock cycle latency for output assertion Session Six 29
- 30. Summary • Click to edit Master text styles - – Second level FSM is simply a finite number of states that each state describes a certain set of control outputs • Third level that are connected to the data part blocks. Mealy machines – Fourth level Inputs » Fifth level Next Present Next Machine state Output Outputs state State State Logic Logic Registers Examples Exercises Labs 24 8 7-8 Session Six 30
- 31. Time for Your Questions • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session Six 31
- 32. Take Your Notes Print the slides and take your notes here -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Second level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Third level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Fourth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- » Fifth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------
- 33. See You Next Session .. Don’t miss • Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level