chap8 synchronous sequential circuit design.ppt

Synchronous Sequential
circuit Design
Dr.Abdul-Halim Jallad
Digital Logic Design
ELEC 335

Summary
• Introduction to Finite State Machines
• Procedure for Synchronous Sequential
Design
• Practical Real-Life Examples
• Example Design: Sequence Detector
• Group Work: Sequence Detection
Example

ELEC 335, Digital Logic Design, UAE University
CLOs Covered
1. Manipulate number system, binary codes, and computer arithmetic.
[PLO-1]
2. Apply Boolean algebra and Karnaugh map minimization techniques
to simplify Boolean expressions. [PLO-1]
3. Design binary adders, decoders, encoders, multiplexers, and de-
multiplexers to implement combinational logic circuits. [PLO-1, 2]
4. Design with flip-flops, synchronous and asynchronous sequential
circuits, state diagrams, and state tables. [PLO-1, 2]
5. Design registers (serial, parallel, and shift) ripple counters, and
synchronous counters. [PLO-1, 2]
6. Design digital circuits with memory devices of ROMs, PLAs, &
PALs. [PLO-2, 4]

What is a Finite State Machine?
• A Finite State Machine
(FSM) is based on the idea
of there being finite number
of states for a given
system.
• For instance, when an
application turns an LED on
and off, two states exist;
one state is when the LED
is on and the other is when
it is off.

The Design Procedure
Given a Description (or Specification) of the Problem
1.Obtain a state diagram for the sequential circuit
2.Assign binary codes to the states and fill the state table
3.Select the type of Flip-Flops and derive the FF input equations
4.Derive the output equations
5.Draw the circuit diagram
6.Verify the correctness of the final design (verification)

6
Intelligent Traffic Controller
• We want to use a finite state
machine to control the traffic
lights at an intersection of a
north-south route and an
east-west route
– We consider only the green
and red lights
– We want the lights to change
no faster than 30 seconds in
each direction
• So we use a 0.033 Hz clock

11/10/2007 11:54:14 AM week12-3.ppt 7
• There are two output signals
– NSlite: When the signal is asserted, the light
on the north-south route is green; otherwise, it
should be red
– EWlite: When the signal is asserted, the light
on the east-west route is green; otherwise, it
should be red

11/10/2007 11:54:22 AM week12-3.ppt 8
• There are two inputs
– NScar: Indicates that there is at least one car
that is over the detectors placed in the
roadbed in the north-south road
– EWcar: Indicates that there is at least one car
that is over the detectors placed in the
roadbed in the east-west road

11/10/2007 11:54:32 AM week12-3.ppt 9
• The traffic lights should only change from
one direction to the other only if there is a
car waiting in the other direction
– Otherwise, the light should continue to show
green in the same direction

11/10/2007 11:54:40 AM week12-3.ppt 10
• Here we need two states
– NSgreen: The traffic light is green in the
north-south direction
– EWgreen: The traffic light is green in the east-
west direction

11/10/2007 11:55:01 AM week12-3.ppt 11
Graphical Representation
NSgreen EWgreen
EWCar=1, NSCar=0 or 1
NSCar=1, EWCar=0 or 1
EWCar=0, NSCar=0 or 1 NSCar=0, EWCar=0 or 1

State Diagrams
• A state is an abstraction of memory
• A state remembers a history of inputs applied to the circuit
• State diagram is a graphical representation of a state table
– The circles are the states
– Two state variable --> Four states (ALL values of and )
𝑨 𝑩
• Arcs are the state transitions
• Labeled with: Input / Output
𝒙 𝒚

State Table
State Table
● Sequences of inputs, flip flop states, and outputs are
enumerated in state table
● Present state indicates current value of flip flops
● Next state occurs after next rising clock edge
● Output is the current output value
0 0
0 1
1 0
1 1
Present
State
Next State
x=0 x=1
00 10 0 0
10 10 0 0
00 11 0 0
10 11 0 1
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
x=0 x=1
Output
State Table

State Table - II
State Table - II
● All possible input combinations
● All possible state combinations
● Separate columns for each output value
● Sometimes it is easier to designate a symbol for each
state
Present
State
Next State
x=0 x=1
s0 s2 0 0
s2 s2 0 0
s0 s3 0 0
s2 s3 0 1
x=0 x=1
Output
s0
s1
s2
s3
Let:
s0 = 00
s1 = 01
s2 = 10
s3 = 11

ELEC 335, Digital Logic Design, UAE University
A system with one input x and one output z such that z = 1 at a clock time
if x is currently 1 and was also 1 at the previous two clock times.
State: what is stored in memory. It is stored in binary devices, but the
information to be stored is not always naturally binary.
Timing trace: a set of values for the input and output (and sometimes
the state or other variables of the system, as well) at consecutive clock
times.
Example: a Sequence Detector

● Specify the problem with words
● e.g. Design a circuit that detects three consecutive
1 inputs
● Assign binary values to states
● Develop a state table
● Use K-maps to simplify expressions
● Flip flop input equations and output equations
● Create appropriate logic diagram
● Should include combinational logic and flip flops

S3
1
Got 111
S2
1
Got 11
S1
1
Got 1
State Diagram for a Sequence Detector
S0
0

Example: Detect 3 Consecutive 1 inputs
Example: Detect 3 Consecutive 1 inputs
State S0: zero 1s detected
State S1: one 1 detected
State S2: two 1s detected
State S3: three 1s detected
0
● Note that each state has 2 output arrows
● Two bits needed to encode state

State Table for Sequence Detector
State Table for Sequence Detector
● Sequence of inputs, outputs, and flip flop
states in state table
● Present state indicates current value of flip
flops
● Next state indicates state after next rising
clock edge
● Output is current output value
Present
State
Next
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
Output
Input
S0 = 00
S1 = 01
S2 = 10
S3 = 11

Finding Expressions for Next State and
Finding Expressions for Next State and
Output Value
Output Value
● Create K-map directly from state table (3
columns = 3 K-maps)
● Minimize K-maps to find SOP representations
● Separate circuit for each next state and output
value

Moore Sequence Detector Circuit
Output
Logic
Next State Logic

Mealy Type Sequence Detector
S0
0 / 0
1 / 0 S1
1 / 0 S2

0 / 0
0 / 0
Complete the Mealy State Diagram
• State S2 is reached after detecting the input sequence "11"
• At S2, if the next input is 1 then the output should be 1
Make a transition from S2 back to itself labeled 1 / 1
No need for state S3, because output is on the arc
• Now complete the state diagram
Add transitions from S1 and S2 back to S0 when input is 0
S0
0 / 0
1 / 0 S1
1 / 0 S2
1 / 1 Mealy Machines
typically use
less states than
Moore Machines

chap8 synchronous sequential circuit design.ppt

REAL LIFE EXAMPLES OF
FSM APPLICATIONS

Example – Elevator Controller
ELEC 335, Digital Logic Design, UAE
University
In this example, we’ll be designing a controller for an elevator.
•The elevator can be at one of two floors: Ground or First.
•There is one button that controls the elevator, and it has two values: Up or Down.
•Also, there are two lights in the elevator that indicate the current floor: Red for
Ground, and Green for First.
•At each time step, the controller checks the current floor and current input, changes
floors and lights in the obvious way.

GROUP WORK – PRACTICAL
EXAMPLE

Sequence Detector Example
Sequence detector: The machine has to generate 𝑧 = 1 when it detects
the sequence 1011. Once the sequence is detected, the circuit looks for
a new sequence.
The signal 𝐸 is an input enable: It validates the input 𝑥, i.e., if 𝐸 = 1, 𝑥
is valid, otherwise 𝑥 is not valid.
Draw the State Diagram (any representation), and the State Table of this
circuit with inputs 𝐸 and 𝑥 and output 𝑧. Is this a Mealy or a Moore
machine? Why?

Example 2 – Elevator Controller
ELEC 335, Digital Logic Design, UAE
University
In this example, we’ll be designing a controller for an elevator. The elevator can be
at one of two floors: Ground or First. There is one button that controls the elevator,
and it has two values: Up or Down. Also, there are two lights in the elevator that
indicate the current floor: Red for Ground, and Green for First. At each time step,
the controller checks the current floor and current input, changes floors and lights in
the obvious way.

Recap Questions
The sequence detected by the state diagram shown below is:
1. 1110
2. 0111
3. 1101
4. 0101

Recap Questions - 2
Is this a Mealy or Moore Machine? Why?
How many inputs does this machine have?
How many flip flops is required for this machine?

Recap - Summary
• Finite State Machines is an abstract machine
that can be in exactly one of a finite number
of states at any given time.
• The design procedure involves state diagram,
state table, K-maps and circuit design
• An FSM can be either Moore or Mealy.

ELEC 335, Digital Logic
Design, UAE University
Design Example using D Flip Flops
1
1
1
1
AB
X
0
1
00 01 11 10
A = B X + A B
1
1
1
1
AB
X
0
1
00 01 11 10
B = A X + B X + A B X
Present
State
A B
Input
X
Next
State
A B
Output
Z
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0

Design Example using D Flip Flops
1
1
AB
X
0
1
00 01 11 10
Z = B X
Now, you can draw the final circuit with clock, set and reset
inputs

Designing with JK Flip Flops
• The design of a sequential circuit with flip flops other
than D type is complicated because the flip flop input
equations for the circuit must be derived indirectly from
the state table
• When D type FF’s are employed, the input equations are
obtained directly from the next state. This is not the case
for JK flip flops and other types of flip flops
• In order to determine the input equations for these FF’s, it
is necessary to derive a functional relationship between
the state table and input equations (Excitation table)

Excitation Tables
Q(t) Q(t+1) J K Q(t) Q(t+1) S R
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
0
0
1
1
0
1
0
1
0
1
0
X
X
0
1
0
Q(t) Q(t+1) D Q(t) Q(t+1) T
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
1
0
JK Flip Flop SR Flip Flop
D Flip Flop T Flip Flop

Design Example using JK Flip Flops
Present
state
A B
Input
X
Next
state
A B
Flip Flop
inputs
JA KA JB KB
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0
1
0
1
0
1
0
1
0 0
0 1
1 0
0 1
1 0
1 1
1 1
0 0
0 X 0 X
0 X 1 X
1 X X 1
0 X X 0
X 0 0 X
X 0 1 X
X 0 X 0
X 1 X 1
Q(t) Q(t+1) J K
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
The output equation is
the same as before
Now you can draw the
final circuit

00 01 11 10
0
1
AB
X
1 X
X X
X
00 01 11 10
0
1
AB
X
1 X
X X
X
AB
00 01 11 10
0
1
X
1
X
X X
X
AB
00 01 11 10
0
1
X
1
X
X X
X
AB
00 01 11 10
0
1
X
1
X
X
X
X
1
AB
00 01 11 10
0
1
X
1
X
X
X
X
1
AB
00 01 11 10
0
1
X
1
X
X
X
X 1
AB
00 01 11 10
0
1
X
1
X
X
X
X 1
J = BX’
A K = BX
A
J = X
B K = A’X’ + AX
B

Clock
JKFF
J = BX’
A J = X
B
K = BX
A K = A’X’ + AX
B
JA
KA
A
>
A’
JKFF
JB
KB
B
>
B’
X

chap8 synchronous sequential circuit design.ppt

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