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ENGIN 112
                 Intro to Electrical and Computer
                            Engineering
                                                      Lecture 23
              Finite State Machine Design Procedure




ENGIN112 L23: Finite State Machine Design Procedure                October 27, 2003
Overvie
       w
  ° Design of systems that input flip flops and
    combinational logic
  ° Specifications start with a word description
  ° Create a state table to indicate next states
  ° Convert next states and outputs to output and flip flop
    input equations
          • Reduce logic expressions using truth tables

  ° Draw resulting circuits.


                Lots of opportunities for interesting design



ENGIN112 L23: Finite State Machine Design Procedure   October 27, 2003
Concept of the State
       Machine
      Computer Hardware = Datapath + Control

                                                      Qualifiers
       Registers                                                   FSM generating sequences
       Combinational Functional                                        of control signals
          Units (e.g., ALU)                                        Instructs datapath what to
       Busses                                                          do next
                                                       Control



                                                      Control

                                                        State

                               Qualifiers                          Control
                               and                                 Signal
                               Inputs                              Outputs


                                                      Datapath



ENGIN112 L23: Finite State Machine Design Procedure                 October 27, 2003
Designing Finite State Machines

      ° Specify the problem with words
             ° (e.g. Design a circuit that detects three
               consecutive 1 inputs)
      ° Assign binary values to states
      ° Develop a state table
      ° Use K-maps to simplify expressions
             ° Flip flop input equations and output equations
      ° Create appropriate logic diagram
             ° Should include combinational logic and flip
               flops



ENGIN112 L23: Finite State Machine Design Procedure   October 27, 2003
Example: Detect 3 Consecutive 1 inputs


            0
                                                      ° State S0 : zero 1s detected
                                                      ° State S1 : one 1 detected
                                                      ° State S2 : two 1s detected
                                                      ° State S3 : three 1s detected




         ° Note that each state has 2 output arrows
         ° Two bits needed to encode state

ENGIN112 L23: Finite State Machine Design Procedure                  October 27, 2003
State Table for Sequence Detector

Present                     Next
                                                 ° Sequence of outputs, inputs,
 State        Input         State         Output   and flip flop states enumerated
  A B           x         A B                y     in state table
  0 0           0         0 0                0 ° Present state indicates current
                                                   value of flip flops
  0    0         1         0     1            0
  0    1         0         0     0            0 ° Next state indicates state after
  0    1         1         1     0            0   next rising clock edge
  1    0         0         0     0            0
                                                ° Output is output value on
  1 0            1         1     1            0   current clock edge
  1 1            0         0     0            1
  1 1            1         1     1            1
      ° S0 = 00                      ° S2 = 10

      ° S1 = 01                      ° S3 = 11


ENGIN112 L23: Finite State Machine Design Procedure            October 27, 2003
Finding Expressions for Next State and Output
       Value
     ° Create K-map directly from state table (3 columns = 3 K-maps)
     ° Minimize K-maps to find SOP representations
     ° Separate circuit for each next state and output value




ENGIN112 L23: Finite State Machine Design Procedure   October 27, 2003
Circuit for Consecutive 1s
       Detector




° Note location of state
  flip flops
° Output value (y) is
  function of state
° This is a Moore
  machine.




ENGIN112 L23: Finite State Machine Design Procedure   October 27, 2003
Concept of the State
       Machine
         Example: Odd Parity Checker
                Assert output whenever input bit stream has odd # of 1's

                Reset                                  Present State   Input       Next State     Output
                                                           Even          0           Even           0
                                  0                        Even          1           Odd            0
                  Even
                                                           Odd           0           Odd            1
                   [0]
                                                           Odd           1           Even           1
            1                 1                           Symbolic State Transition Table
                   Odd
                   [1]                                Present State    Input      Next State      Output
       0                                                   0             0            0             0
                                                           0             1            1             0
                                                           1             0            1             1
                 State                                     1             1            0             1
                Diagram
                                                           Encoded State Transition Table

        °       Note: Present state and output are the same value
                 ° Moore machine

ENGIN112 L23: Finite State Machine Design Procedure                            October 27, 2003
Concept of the State
       Machine
                                                 Example: Odd Parity Checker
                                                  Next State/Output Functions
                                                        NS = PS xor PI; OUT = PS

                                                                NS
                                         Input
                                                                     D       Q
                                                       CLK                       PS/Output
                                                                             Q
                                                                         R
                                                       Reset
            D FF Implementation


              Input        1     0       0        1     1       0    1       0     1       1         1       0


                 Clk


           Output           1        1    1        0        1   1    0       0         1       0         1   1

                               Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
ENGIN112 L23: Finite State Machine Design Procedure                               October 27, 2003
Mealy and Moore Machines


      Solution 1: (Mealy)                                         Solution 2: (Moore)
                                      0/0                                                      0
                                                         Reset             Even
                      Even             Input                                 [0]                   Output
                                           O/P is dependent
           1/0                    1/1
                                           on current state and    1                       1
                                                                                                   Input
                                    Output input in Mealy
 Transition           Odd                                                   Odd
                                                                              [1]
                                                                                                   Output is
 Arc                                                                                               dependent only
                                                                                       0           on current state
                 0/1
Mealy Machine: Output is associated with
the state transition                                        Moore Machine: Output is associated
- Appears before the state transition is                    with the state
completed (by the next clock pulse).                        -Appears after the state transition
                                                             takes place.


ENGIN112 L23: Finite State Machine Design Procedure                 October 27, 2003
Vending Machine FSM

         Step 1. Specify the problem
  Deliver package of gum after 15 cents deposited

  Single coin slot for dimes, nickels

  No change

  Design the FSM using combinational logic and flip flops



                                      N
                         Coin                         V e nding O pe n    G um
                        S e nsor D
                                                      Ma chine          Re le a se
                                      Re se t           FS M           Me cha nism

                                      Clk




ENGIN112 L23: Finite State Machine Design Procedure                    October 27, 2003
Vending Machine FSM

         State Diagram

            Rese t                                    Present    Inputs        Next     Output
                         0¢
                                                       State     D N           State    Open
                                                        0¢       0   0          0¢        0
                        N
                                                                 0   1          5¢        0
                         5¢
                                    D
                                                                 1   0          10¢       0
                                                                 1   1           X        X
                        N                               5¢       0   0          5¢        0
                         10¢                                     0   1          10¢       0
                D                                                1   0          15¢       0
                     N, D
                                                                 1   1           X        X
                                                       10¢       0   0          10¢       0
                         15¢
                                                                 0   1          15¢       0
                       [o p e n ]
                                                                 1   0          15¢       0
                                                                 1   1           X        X
       Reuse states                                    15¢       X   X          15¢       1

     whenever possible
                                                             Symbolic State Table

ENGIN112 L23: Finite State Machine Design Procedure                  October 27, 2003
Vending Machine FSM

         State Encoding                                   How many flip-flops are needed?


                          Present State        Inputs     Next State       Output
                             Q1 Q0              D N        D1 D0            Open
                               0     0          0     0    0   0               0
                                                0     1    0   1               0
                                                1     0    1   0               0
                                                1     1    X   X               X
                               0     1          0     0    0   1               0
                                                0     1    1   0               0
                                                1     0    1   1               0
                                                1     1    X   X               X
                               1     0          0     0    1   0               0
                                                0     1    1   1               0
                                                1     0    1   1               0
                                                1     1    X   X               X
                               1     1          0     0    1   1               1
                                                0     1    1   1               1
                                                1     0    1   1               1
                                                1     1    X   X               X

ENGIN112 L23: Finite State Machine Design Procedure                    October 27, 2003
Vending Machine FSM

         Determine F/F implementation




                           Q1                                 Q1                            Q1
   Q1 Q0                                       Q1 Q0                       Q1 Q0
 D N                                         D N                         D N



                                      N                              N                               N
  D                                           D                           D


                Q0                                        Q0                            Q0
           K-map for D1                               K-map for D0                  K-map for Open




ENGIN112 L23: Finite State Machine Design Procedure                  October 27, 2003
Minimized Implementation

                                    Q1
                            D                            D1                Q1
                                                              D       Q
                 Q0                                    CLK                     Q1
                                                                  R   Q
                 N                               Reset                                                 OPEN
                 N
                 Q0
                 Q0
                                                       D0                 Q0
                 N                                            D       Q
                                                      CLK
                Q1                                                R   Q   Q0
                N
                                               Reset
                Q1
                D

                   Vending machine FSM implementation based on D flip-flops(Moore).

ENGIN112 L23: Finite State Machine Design Procedure                                 October 27, 2003
Summary


° Finite state machines form the basis of many digital
  systems
° Designs often start from clear specifications
° Develop state diagram and state table
° Optimize using combinational design techniques
° Mealy or Moore implementations possible
        • Can model approach using HDL.




ENGIN112 L23: Finite State Machine Design Procedure   October 27, 2003

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Lect23 Engin112

  • 1. ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine Design Procedure ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 2. Overvie w ° Design of systems that input flip flops and combinational logic ° Specifications start with a word description ° Create a state table to indicate next states ° Convert next states and outputs to output and flip flop input equations • Reduce logic expressions using truth tables ° Draw resulting circuits. Lots of opportunities for interesting design ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 3. Concept of the State Machine Computer Hardware = Datapath + Control Qualifiers Registers FSM generating sequences Combinational Functional of control signals Units (e.g., ALU) Instructs datapath what to Busses do next Control Control State Qualifiers Control and Signal Inputs Outputs Datapath ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 4. Designing Finite State Machines ° Specify the problem with words ° (e.g. Design a circuit that detects three consecutive 1 inputs) ° Assign binary values to states ° Develop a state table ° Use K-maps to simplify expressions ° Flip flop input equations and output equations ° Create appropriate logic diagram ° Should include combinational logic and flip flops ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 5. Example: Detect 3 Consecutive 1 inputs 0 ° State S0 : zero 1s detected ° State S1 : one 1 detected ° State S2 : two 1s detected ° State S3 : three 1s detected ° Note that each state has 2 output arrows ° Two bits needed to encode state ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 6. State Table for Sequence Detector Present Next ° Sequence of outputs, inputs, State Input State Output and flip flop states enumerated A B x A B y in state table 0 0 0 0 0 0 ° Present state indicates current value of flip flops 0 0 1 0 1 0 0 1 0 0 0 0 ° Next state indicates state after 0 1 1 1 0 0 next rising clock edge 1 0 0 0 0 0 ° Output is output value on 1 0 1 1 1 0 current clock edge 1 1 0 0 0 1 1 1 1 1 1 1 ° S0 = 00 ° S2 = 10 ° S1 = 01 ° S3 = 11 ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 7. Finding Expressions for Next State and Output Value ° Create K-map directly from state table (3 columns = 3 K-maps) ° Minimize K-maps to find SOP representations ° Separate circuit for each next state and output value ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 8. Circuit for Consecutive 1s Detector ° Note location of state flip flops ° Output value (y) is function of state ° This is a Moore machine. ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 9. Concept of the State Machine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 1's Reset Present State Input Next State Output Even 0 Even 0 0 Even 1 Odd 0 Even Odd 0 Odd 1 [0] Odd 1 Even 1 1 1 Symbolic State Transition Table Odd [1] Present State Input Next State Output 0 0 0 0 0 0 1 1 0 1 0 1 1 State 1 1 0 1 Diagram Encoded State Transition Table ° Note: Present state and output are the same value ° Moore machine ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 10. Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS NS Input D Q CLK PS/Output Q R Reset D FF Implementation Input 1 0 0 1 1 0 1 0 1 1 1 0 Clk Output 1 1 1 0 1 1 0 0 1 0 1 1 Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0 ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 11. Mealy and Moore Machines Solution 1: (Mealy) Solution 2: (Moore) 0/0 0 Reset Even Even Input [0] Output O/P is dependent 1/0 1/1 on current state and 1 1 Input Output input in Mealy Transition Odd Odd [1] Output is Arc dependent only 0 on current state 0/1 Mealy Machine: Output is associated with the state transition Moore Machine: Output is associated - Appears before the state transition is with the state completed (by the next clock pulse). -Appears after the state transition takes place. ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 12. Vending Machine FSM Step 1. Specify the problem Deliver package of gum after 15 cents deposited Single coin slot for dimes, nickels No change Design the FSM using combinational logic and flip flops N Coin V e nding O pe n G um S e nsor D Ma chine Re le a se Re se t FS M Me cha nism Clk ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 13. Vending Machine FSM State Diagram Rese t Present Inputs Next Output 0¢ State D N State Open 0¢ 0 0 0¢ 0 N 0 1 5¢ 0 5¢ D 1 0 10¢ 0 1 1 X X N 5¢ 0 0 5¢ 0 10¢ 0 1 10¢ 0 D 1 0 15¢ 0 N, D 1 1 X X 10¢ 0 0 10¢ 0 15¢ 0 1 15¢ 0 [o p e n ] 1 0 15¢ 0 1 1 X X Reuse states 15¢ X X 15¢ 1 whenever possible Symbolic State Table ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 14. Vending Machine FSM State Encoding How many flip-flops are needed? Present State Inputs Next State Output Q1 Q0 D N D1 D0 Open 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 X X X 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 X X X 1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 X X X 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 X X X ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 15. Vending Machine FSM Determine F/F implementation Q1 Q1 Q1 Q1 Q0 Q1 Q0 Q1 Q0 D N D N D N N N N D D D Q0 Q0 Q0 K-map for D1 K-map for D0 K-map for Open ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 16. Minimized Implementation Q1 D D1 Q1 D Q Q0 CLK Q1 R Q N Reset OPEN N Q0 Q0 D0 Q0 N D Q CLK Q1 R Q Q0 N Reset Q1 D Vending machine FSM implementation based on D flip-flops(Moore). ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003
  • 17. Summary ° Finite state machines form the basis of many digital systems ° Designs often start from clear specifications ° Develop state diagram and state table ° Optimize using combinational design techniques ° Mealy or Moore implementations possible • Can model approach using HDL. ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003

Editor's Notes

  • #2: Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall
  • #3: credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
  • #18: credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.