This document discusses the design procedure for finite state machines (FSMs). It describes how to start with a word problem description, create a state table to define the next states and outputs, minimize logic expressions using K-maps, and draw the resulting circuit diagram incorporating flip-flops and combinational logic. An example of detecting three consecutive 1 inputs is used to illustrate the full procedure. The document also distinguishes between Mealy and Moore machine implementations and provides additional examples of odd parity checking and a vending machine FSM.