Basics Counters
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This document discusses different types of counters, including asynchronous and synchronous counters. Asynchronous counters use flip-flops that are not connected to a common clock, resulting in a "ripple" effect. Synchronous counters connect all flip-flops to the same clock and use combinational logic to generate the next state. Counters can be cascaded to achieve higher modulus by connecting the output of one counter to the input of the next. The document also provides an example of designing a synchronous BCD counter and cascading a mod-10 and mod-8 counter.
Basics Counters
- 2. Mirza Danial Masood BS-IT(B), Roll No. 85, UOS M.B.Din
- 3. Overview • Counters are a specific type of sequential circuit. • Like registers, the state, or the flip-flop values themselves, serves as the “output.” • The output value increases by one on each clock cycle. • After the largest value, the output “wraps around” back to 0. • Counters can act as simple clocks to keep track of “time.” • You may need to record how many times something has happened. • All processors contain a program counter, or PC.
- 4. D flip-flop inputs • If we use D flip-flops, then the D inputs will just be the same as the desired next states. • Equations for the D flip-flop inputs are shown at the right. • Why does D0 = Q0’ make sense? Present State Inputs Next State Q1 Q0 X Q1 Q0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 Q0 1 1 0 0 Q1 1 1 0 0 X Q0 0 1 0 1 Q1 1 0 1 0 X D1 = Q1 Q0 X D0 = Q0’
- 5. Asynchronous Counters • This counter is called asynchronous because not all flip flops are hooked to the same clock. • Look at the waveform of the output, Q, in the timing diagram. It resembles a clock as well. If the period of the clock is T, then what is the period of Q, the output of the flip flop? It's 2T! • We have a way to create a clock that runs twice as slow. We feed the clock into a T flip flop, where T is hardwired to 1. The output will be a clock who's period is twice as long.
- 6. Asynchronous counters • If the clock has period T. Q0 has period 2T. Q1 period is 4T • With n flip flops the period is 2n.
- 8. 3 bit asynchronous “ripple” counter using T flip flops • This is called as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect.
- 9. Synchronous Counters • To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. • For an up-counter, use an incrementer =>
- 10. Synchronous Counters • Internal details => • Internal Logic Incrementer – XOR complements each bit – AND chain causes complement of a bit if all bits toward LSB from it equal 1 • Count Enable – Forces all outputs of AND chain to 0 to “hold” the state • Carry Out – Added as part of incrementer – Connect to Count Enable of additional 4-bit counters to form larger counters
- 12. Design Example: Synchronous BCD • Use the sequential logic model to design a synchronous BCD counter with D flip-flops • State Table => • Input combinations 1010 through 1111 are don’t cares Current State Q8 Q4 Q2 Q1 Next State Q8 Q4 Q2 Q1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0
- 13. Synchronous BCD (continued) • Use K-Maps to two-level optimize the next state equations and manipulate into forms containing XOR gates: D1 = Q1’ • D2 = Q2 + Q1Q8’ D4 = Q4 + Q1Q2 D8 = Q8 + (Q1Q8 + Q1Q2Q4) • Y = Q1Q8 • The logic diagram can be drawn from these equations • An asynchronous or synchronous reset should be added • What happens if the counter is perturbed by a power disturbance or other interference and it enters a state other than 0000 through 1001?
- 14. Synchronous BCD (continued) • Find the actual values of the six next states for the don’t care combinations from the equations • Find the overall state diagram to assess behavior for the don’t care states (states in decimal). Present State Next State Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0
- 15. Synchronous BCD (continued) • For the BCD counter design, if an invalid state is entered, return to a valid state occurs within two clock cycles • Is this adequate?!
- 16. Cascaded Counters • Counters can be connected to achieve higher modulus operation. • Cascading means that the last stage output of one counter drives the input of the next counter. • A mod-M and a mod-N counter in cascade give a mod-MN counter. • 2 types of cascading: Asynchronous cascading and synchronous cascading .
- 17. Cascaded Counters (continue) Asynchronous cascading : Two asynchronous counters connected in cascade for a 2 bit and a 3 bit ripple counter. The overall modulus of the two cascaded counters is 4 x 8 = 32; that is they act as a divide-by-32 counter.
- 18. Cascaded Counters (continue) Synchronous cascading : In synchronous cascaded counter, it is necessary to use the count enable (CTEN) and the terminal count (TC) functions to achieve higher modulus operation. Terminal count (TC) is analogous to ripple clock or ripple carry out (RCO) on some IC counters.
- 19. Cascaded Counters: Example The figure below shows a mod-10 counter and mod-8 counter connected in cascade. What is the overall modulus of these two cascaded counter? Determine the frequency at B if f in is 20kHz. Answer: Overall modulus = 10 x 8 =80 = mod-80 counter Frequency at B = fin /80 = 250Hz