9920Lec12 FSM.ppt

ECE C03 Lecture 12 1
Lecture 12
Finite State Machine Design
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998

Outline
• Review of sequential machine design
• Moore/Mealy Machines
• FSM Word Problems
– Finite string recognizer
– Traffic light controller
• READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2

Concept of the State Machine
Computer Hardware = Datapath + Control
Registers
Combinational Functional
Units (e.g., ALU)
Busses
FSM generating sequences
of control signals
Instructs datapath what to
do next
"Puppet"
"Puppeteer who pulls the
strings"
Qualifiers
Control
Control
Datapath
State
Control
Signal
Outputs
Qualifiers
and
Inputs

Example: Odd Parity Checker
Even
[0]
Odd
[1]
Reset
0
0
1 1
Assert output whenever input bit stream has odd # of 1's
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next State
Even
Odd
Odd
Even
Output
0
0
1
1
Symbolic State Transition Table
Output
0
0
1
1
Next State
0
1
1
0
Input
0
1
0
1
Present State
0
0
1
1
Encoded State Transition Table

Odd Parity Checker Design
Next State/Output Functions
NS = PS xor PI; OUT = PS
D
R
Q
Q
Input
CLK PS/Output
Reset
NS
D FF Implementation
T
R
Q
Q
Input
CLK
Output
Reset
T FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk
Output
Input 1 0 0 1 1 0 1 0 1 1 1 0
1
1
0
1
0
0
1
1
0
1
1
1

Timing of State Machines
When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
• Clocking event causes state/outputs to transition, based on inputs
• For set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event

Timing of State Machine
Example: Positive Edge Triggered Synchronous System
On rising edge, inputs sampled
outputs, next state computed
After propagation delay, outputs and
next state are stable
Immediate Outputs:
affect datapath immediately
could cause inputs from datapath to change
Delayed Outputs:
take effect on next clock edge
propagation delays must exceed hold times
Outputs
State Time
Clock
Inputs

Communicating State Machines
Machines advance in lock step
Initial inputs/outputs: X = 0, Y = 0
One machine's output is another machine's input
CLK
FSM1
X
FSM2
Y
A A B
C D D
FSM 1 FSM 2
X
Y
A
[1]
B
[0]
Y=0
Y=1
Y=0,1
Y=0
C
[0]
D
[1]
X=0
X=1
X=0
X=0
X=1

Basic Design Approach
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state mininimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure

Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Block Diagram
Step 1. Understand the problem:
Vending
Machine
FSM
N
D
Reset
Clk
Open
Coin
Sensor
Gum
Release
Mechanism
Draw a picture!

Vending Machine Example
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open
Step 2. Map into more suitable abstract representation
Reset
N
N
N
D
D
N
D
[open]
[open] [open] [open]
S0
S1 S2
S3 S4 S5 S6
S8
[open]
S7
D

Step 3: State Minimization
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
reuse states
whenever
possible
Symbolic State Table
Present
State
0¢
5¢
10¢
15¢
D
0
0
1
1
0
0
1
1
0
0
1
1
X
N
0
1
0
1
0
1
0
1
0
1
0
1
X
Inputs Next
State
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1

Step 4: State Encoding
Next State
D1
D0
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
Present State
Q1
Q0
0 0
0 1
1 0
1 1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Inputs Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X

Step 5. Choose FFs for implementation D FF easiest to use
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
CLK
OPEN
CLK
Q0
D
R
Q
Q
D
R
Q
Q
Q1
reset
reset
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
D
D
N
N
N
N
D1
D0
K-map for Open
K-map for D0
K-map for D1
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N
0 0 1 1
0 1 1 1
X X X X
1 1 1 1
0 1 1 0
1 0 1 1
X X X X
0 1 1 1
0 0 1 0
0 0 1 0
X X X X
0 0 1 0

Alternative State Machine
Representations
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified
sequence of actions based on input data
algorithm = sequencing + data manipulation
separation of control and data
Gradual shift towards program-like representations:
• Algorithmic State Machine (ASM) Notation
• Hardware Description Languages (e.g., VHDL)

Alternative State Machine
Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
• State Box
• Decision Box
• Output Box
State Machine in one state
block per state time
Single Entry Point
Unambiguous Exit Path
for each combination
of inputs
Outputs asserted high (.H)
or low (.L); Immediate (I)
or delayed til next clock
State
Entry Path
State
Name
State Code
State Box
ASM
Block
State
Output List
Condition
Box
Conditional
Output List
Output
Box
Exits to
other ASM Blocks
Condition
* ***
T F

ASM Notation
Condition Boxes:
Ordering has no effect on final outcome
Equivalent ASM charts:
A exits to B on (I0 • I1) else exit to C
A 010
I0
I1
T
T
F
F
B C
A 010
I0
T
T
F
F
B C
I1

ASM Example: Parity Checker
Nothing in output list implies Z not asserted
Z asserted in State Odd
Input X, Output Z
Input
F
T
F
T
Present
State
Even
Even
Odd
Odd
Next
State
Even
Odd
Odd
Even
Output
—
—
A
A
Symbolic State Table:
Input
0
1
0
1
Present
State
0
0
1
1
Next
State
0
1
1
0
Output
0
0
1
1
Encoded State Table:
Trace paths to derive
state transition tables
Even
Odd
H.Z
X
X
0
1
F
T
T
F

ASM Chart: Vending Machine
0¢
15¢
H.Open
D
Reset
00
11
T
T
F
N
F
T
F
10¢
D
10
T
N
F
T
F
5¢
D
01
T
N
F T
F
0¢

Moore and Mealy Machine Design
Procedure Moore Machine
Outputs are function
solely of the current
state
Outputs change
synchronously with
state changes
Mealy Machine
Outputs depend on
state AND inputs
Input change causes
an immediate output
change
Asynchronous signals
State Register Clock
State
Feedback
Combinational
Logic for
Outputs and
Next State
X
Inputs
i
Z
Outputs
k
Clock
state
feedback
Combinational
Logic for
Next State
(Flip-flop
Inputs)
State
Register
Comb.
Logic for
Outputs
Z
Outputs
k
X
Inputs
i

Equivalence of Moore and Mealy
Machines
Outputs are associated
with State
Outputs are associated
with Transitions
Reset/0
N/0
N/0
N+D/1
15¢
0¢
5¢
10¢
D/0
D/1
(N D + Reset)/0
Reset/0
Reset/1
N D/0
N D/0
Moore
Machine Reset
N
N
N+D
[1]
15¢
0¢
5¢
10¢
D
[0]
[0]
[0]
D
N D + Reset
Reset
Reset
N D
N D
Mealy
Machine

States vs Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
Equivalent
ASM Charts
Same I/O behavior
Different # of states
1
1
0
1
2
0
0
[0]
[0]
[1]
1/0
0
1
0/0
0/0
1/1
1
0
S0
S1
IN
IN
S2
IN
10
01
00
H.OUT
S0
S1
IN
IN
1
0
H.OUT

Analyze Behavior of Moore Machines
Reverse engineer the following:
Input X
Output Z
State A, B = Z
Two Techniques for Reverse Engineering:
• Ad Hoc: Try input combinations to derive transition table
• Formal: Derive transition by analyzing the circuit
J
C
K R
Q
Q
FFa
J
C
K R
Q
Q
FFb
X
X
X
X
Reset
Reset
A
Z
A
A
B
B
Clk

Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
Partially Derived
State Transition
Table
A
0
0
1
1
B
0
1
0
1
X
0
1
0
1
0
1
0
1
A+
?
1
0
?
1
0
1
1
B+
?
1
0
?
0
1
1
0
Z
0
0
1
1
0
0
1
1
X = 1
AB = 00
X = 0
AB = 11
X = 1
AB = 11
X = 0
AB = 10
X = 1
AB = 10
X = 0
AB = 01
X = 0
AB = 00
Reset
AB = 00
100
X
Clk
A
Z
Reset

Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!
Ja = X
Jb = X
Ka = X • B
Kb = X xor A
Z = B
FF excitation equations for J-K flipflop:
A+ = Ja • A + Ka • A = X • A + (X + B) • A
B+ = Jb • B + Kb • B = X • B + (X • A + X • A) • B
Next State K-Maps:
State 00, Input 0 -> State 00
State 01, Input 1 -> State 01
A+
B+

Complete ASM Chart of Moore Machine
Note: All Outputs Associated With State Boxes
No Separate Output Boxes — Intrinsic in Moore Machines
S0
00
X
H.Z
S1
01
X
S3
11
S2
10
H.Z
X
X
0 1
1
0
0
1
0
1

Behavior of Mealy Machines
Input X, Output Z, State A, B
State register consists of D FF and J-K FF
D
C
R
Q
Q
J
C
K
R
Q
Q
X
X
X
Clk
A
A
A
B
B
B
Z
Reset
Reset
A
A
X
X
X
B
DA
DA

Ad Hoc Reverse Engineering
Signal Trace of Input Sequence 101011:
Note glitches
in Z!
Outputs valid at
following falling
clock edge
Partially completed
state transition table
based on the signal
trace
A
0
0
1
1
B
0
1
0
1
X
0
1
0
1
0
1
0
1
A+
0
0
?
1
?
0
1
?
B+
1
0
?
1
?
1
0
?
Z
0
0
?
0
?
1
1
?
Reset
AB=00
Z=0
X=1
AB=00
Z=0
X=0
AB=00
Z=0
X=1
AB=01
Z=0
X=1
AB=10
Z=1
X=0
AB=11
Z=1
X=1
AB=01
Z=0
X
Clk
A
B
Z
Reset
100

Formal Reverse Engineering
A+ = B • (A + X) = A • B + B • X
B+ = Jb • B + Kb • B = (A xor X) • B + X • B
= A • B • X + A • B • X + B • X
Z = A • X + B • X
Missing Transitions and Outputs:
State 01, Input 0 -> State 01, Output 1
A+
B+
Z

ASM Chart of Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11
NOTE: Some Outputs in Output Boxes as well as State Boxes
This is intrinsic in Mealy Machine implementation
S0
00
X
H.Z S1 01
S2
10
X
H.Z
H.Z
S3
11
X
X
0
1
0
0 1
1
0 1

Synchronous Mealy Machines
latched state AND outputs
avoids glitchy outputs!
State Register Clock
Clock
Combinational
Logic for
Outputs and
Next State
state
feedback
X
Inputs
i Z
Outputs
k

Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Case Studies:
• Finite String Pattern Recognizer
• • Traffic Light Controller
We will use state diagrams and ASM Charts

Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010…
Z: 00010101000…
X: 11011010010…
Z: 00000001000…

Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
Moore State Diagram
Reset signal places
FSM in S0
Outputs 1 Loops in State
S0
[0]
S1
[0]
S2
[0]
S3
[1]
S4
[0]
S5
[0]
S6
[0]
Reset

Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = …01 (state S2)
S0
[0]
S1
[0]
S2
[0]
S3
[1]
S4
[0]
S5
[0]
S6
[0]
Reset

Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
S0
[0]
S1
[0]
S2
[0]
S3
[1]
S4
[0]
S5
[0]
S6
[0]
Reset

S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram
S0
[0]
S1
[0]
S2
[0]
S3
[1]
S4
[0]
S5
[0]
S6
[0]
Reset

Review of Design Process
• Write down sample inputs and outputs to understand specification
• Write down sequences of states and transitions for the sequences
to be recognized
• Add missing transitions; reuse states as much as possible
• Verify I/O behavior of your state diagram to insure it functions
like the specification

Traffic Light Controller
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

Picture of Highway/Farmroad Intersection:
Highway
Highway
Farmroad
Farmroad
HL
HL
FL
FL
C
C

• Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
• Tabulation of Unique States: Some light configuration imply others
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)

Refinement of ASM Chart:
Start with basic sequencing and outputs:
S0
S3
S1
S2
H.HG
H.FR
H.HR
H.FY
H.HR
H.FG
H.HY
H.FR

Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C • TL
Equivalent ASM Chart Fragments
S0 S0
H.HG
H.FR
H.HG
H.FR
TL TL • C
H.ST
C
H.ST S1
H.HY
H.FR
S1
H.HY
H.FR
0
0
1
1
0
1

S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
S1
H.HY
H.FR
TS
H.ST
S2
H.HR
H.FG
0 1

S2 Exit Condition: no car waiting OR long time interval expired
Complete ASM Chart for Traffic Light Controller
S0 S3
H.HG
H.FR H.ST
H.HR
H.FY
TS
TL • C
H.ST H.ST
S1 S2
H.HY
H.FR
H.ST H.HR
H.FG
TS TL + C
0 0
1
1
1
0
1
0

Compare with state diagram:
Advantages of State Charts:
• Concentrates on paths and conditions for exiting a state
• Exit conditions built up incrementally, later combined into
single Boolean condition for exit
• Easier to understand the design as an algorithm
S0: HG
S1: HY
S2: FG
S3: FY
Reset
TL + C
S0
TL•C/ST
TS
S1 S3
S2
TS/ST
TS/ST
TL + C/ST
TS
TL • C

Summary
• Review of sequential machine design
• Moore/Mealy Machines
• FSM Word Problems
– Finite string recognizer
– Traffic light controller
• NEXT LECTURE: Finite State Machine
Optimization
• READING: Katz 9.1, 2.2.1, 9.2.2, Dewey 9.3

9920Lec12 FSM.ppt

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9920Lec12 FSM.ppt