lec25_algorithmic_state_machines1233.ppt
- 1. Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) ECE/CS 352: Digital Systems Fundamentals Lecture 25 – Algorithmic State Machines
- 2. Chapter 8 2 Overview Datapath and Control Algorithmic State Machines (ASM) • ASM chart • Timing considerations ASM chart example • Binary multiplier
- 3. Chapter 8 3 Datapath and Control Datapath - performs data transfer and processing operations Control Unit - Determines the enabling and sequencing of the operations The control unit receives: • External control inputs • Status signals The control unit sends: • Control signals • Control outputs Control inputs Data inputs Data outputs Datapath Control outputs Control signals Status signals Control unit Describe properties of the state of the datapath
- 4. Chapter 8 4 Control Unit Types Two distinct classes: • Programmable • Non-programmable (hard-wired) A programmable control unit has: • A program counter (PC) or other sequencing register with contents that points to the next instruction to be executed • An external ROM or RAM array for storing instructions and control information • Decision logic for determining the sequence of operations and logic to interpret the instructions A non-programmable control unit does not fetch or sequence instructions from a memory • We’ll focus on hard-wired control in this lecture
- 5. Chapter 8 5 Algorithmic State Machines A flowchart is a way of showing actions and control flow in an algorithm. An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify state diagrams for sequential logic and, optionally, actions performed in a datapath. While flowcharts typically do not specify “time”, an ASM explicitly specifies a sequence of actions and their timing relationships. IDLE AVAIL START R← R + 1 R ← 0 Q0 0 1 MUL0 MUL1 ASM BLOCK Entry Exit Exit Exit
- 6. Chapter 8 6 A rectangle with: • The symbolic name for the state marked outside the upper left top • Containing register transfer operations and outputs activated within or while leaving the state • An optional state code, if assigned, outside the upper right top (Symbolic Name) IDLE (Register transfers or outputs) R ← 0 RUN (Optional state code) 0000 State Box
- 7. Chapter 8 7 A diamond with: • One input path (entry point). • One input condition, placed in the center of the box, that is tested. • A TRUE exit path taken if the condition is true (logic 1). • A FALSE exit path taken if the condition is false (logic 0). (Input) START (True Condition) (False Condition) 0 1 Scalar Decision Box
- 8. Chapter 8 8 Vector Decision Box A hexagon with: • One Input Path (entry point). • A vector of input conditions, placed in the center of the box, that is tested. • Up to 2n output paths. The path taken has a binary vector value that matches the vector input condition (Vector of Input Conditions) (Binary Vector Values) 00 01 (Binary Vector Values) 10 Z, Q0
- 9. Chapter 8 9 Conditional Output Box An oval with: • One input path from a decision box or decision boxes. • One output path • Register transfers or outputs that occur only if the conditional path to the box is taken. Transfers and outputs in a state box are Moore type - dependent only on state Transfers and outputs in a conditional output box are Mealy type - dependent on both state and inputs (Register transfers or outputs) R ← 0 RUN From Decision Box(es)
- 10. Chapter 8 10 By connecting boxes together, we begin to see the power of expression. What are the: • Inputs? • Outputs? • Conditional Outputs? • Transfers? • Conditional Transfers? Connecting Boxes Together IDLE R← 0 START 0 1 PC ← 0 AVAIL INIT
- 11. Chapter 8 11 ASM Blocks One state box along with all decision and conditional output boxes connected to it is called an ASM Block. The ASM Block includes all items on the path from the current state to the same or other states. IDLE AVAIL START R← R + 1 R ← 0 Q0 0 1 MUL0 MUL1 ASM BLOCK Entry Exit Exit Exit
- 12. Chapter 8 12 ASM Timing Outputs appear while in the state Register transfers occur at the clock while exiting the state - New values occur in the next state! Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock START Q1 AVAIL IDLE MUL 1 0034 0000 State A Q0
- 13. Chapter 8 13 Multiplier Example Example: (101 x 011) Base 2 Note that the partial product summation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column. Note also n x m digit multiply generates up to an m + n digit result (same as decimal). 1 0 1 x 0 1 1 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1 Partial products are: 101 x 0, 101 x 1, and 101 x 1
- 14. Chapter 8 14 Example (1 0 1) x (0 1 1) Again Reorganizing example to follow hardware algorithm: 1 0 1 x 0 1 1 0 0 0 0 + 1 0 1 0 1 0 1 0 0 1 0 1 + 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 Clear C || A Multipler0 = 1 => Add B Addition Shift Right (Zero-fill C) Multipler1 = 1 => Add B Addition Shift Right Multipler2 = 0 => No Add, Shift Right
- 15. Chapter 8 15 Multiplier Example: Block Diagram C out n n n21 Counter P Zero detect Control unit G (Go) log2n Qo Z Parallel adder Multiplicand Register B Shift register A 0 C Shift register Q Multiplier Product OUT IN Control signals n n n 4
- 16. Chapter 8 16 Multiplier Example: Operation 1. The multiplicand (top operand) is loaded into register B. 2. The multiplier (bottom operand) is loaded into register Q. 3. Register C||A is initialized to 0 when G becomes 1. 4. The partial products are summed iteratively in register C||A||Q. 5. Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use adder to add B to partial product; if bit is 0, do nothing) 6. C||A||Q is shifted right using the shift register • Partial product bits fill vacant locations in Q as multiplier is shifted out • If overflow during addition, the outgoing carry is recovered from C during the right shift 7. Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect. • Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier
- 17. Chapter 8 17 Multiplier Example: ASM Chart 0 1 G IDLE MUL0 0 1 Z MUL1 0 1 0 C ← 0, A ← P ←n – 1 A ← A + B, C ← Cout P ← P – 1 C ← 0, C || A || Q ← sr C || A || Q, Q0
- 18. Chapter 8 18 Multiplier Example: ASM Chart (continued) Three states are employed using a combined Mealy - Moore output model: • IDLE - state in which: input G is used as the condition for starting the multiplication, and C, A, and P are initialized • MUL0 - state in which conditional addition is performed based on the value of Q0. • MUL1 - state in which: right shift is performed to capture the partial product and position the next bit of the multiplier in Q0 the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.
- 19. Chapter 8 19 Multiplier Example: Control Signal Table Control Signals for BinaryMultiplier Block Diagram Module Microope ration Control Sign al Name Control Expression Register A: A ← 0 Initialize G A ← A + B Load MUL0 · Q C || A || Q sr C || A || Q Shift_dec MUL1 Register B: B ← IN Load_B LOADB Flip-Flop C: C ← 0 Clear_C IDLE · G + MUL1 C ← Cout Load — Register Q: Q ← IN Load_Q LOADQ C || A || Q ← sr C || A || Q Shift_dec — Counter P: P ← n – 1 Initialize — P ← P – 1 Shift_dec — IDLE · ←
- 20. Chapter 8 20 Signals are defined on a register basis LOADQ and LOADB are external signals controlled from the system using the multiplier and will not be considered a part of this design Note that many of the control signals are “reused” for different registers. These control signals are the “outputs” of the control unit With the outputs represented by the table, they can be removed from the ASM giving an ASM that represents only the sequencing (next state) behavior Multiplier Example: Control Table (continued)
- 21. Chapter 8 21 Multiplier Example - Sequencing Part of ASM 0 1 IDLE MUL0 0 1 01 MUL1 10 00 G Z
- 22. Chapter 8 22 This method uses one flip-flop per state and a simple set of transformation rules to implement the circuit. The design starts with the ASM chart, and replaces 1. State Boxes with flip-flops, 2. Scalar Decision Boxes with a demultiplexer with 2 outputs, 3. Vector Decision Boxes with a (partial) demultiplexer 4. Junctions with an OR gate, and 5. Conditional Outputs with AND gates. Each is discussed detail below. • Figure 8-11 is the end result. One Flip-Flop per State
- 23. Chapter 8 23 State Box Transformation Rules Each state box transforms to a D Flip-Flop Entry point is connected to the input. Exit point is connected to the Q output. STATE Entry Exit D Q Entry Exit STATE
- 24. Chapter 8 24 Scalar Decision Box Transformation Rules Each Decision box transforms to a Demultiplexer Entry points are "Enable" inputs. The Condition is the "Select" input. Decoded Outputs are the Exit points. X 0 1 Entry Exit 0 Exit 1 X Entry Exit 0 Exit 1
- 25. Chapter 8 25 Vector Decision Box Transformation Rules Each Decision box transforms to a Demultiplexer Entry point is Enable inputs. The Conditions are the Select inputs. Demultiplexer Outputs are the Exit points. (Vector of Input Conditions) (Binary Vector Values) 00 01 (Binary Vector Values) 10 X1, X0 X1 Entry Exit 0 Exit 1 X0 DEMUX EN A1 A0 D0 D2 D1 D3 Exit2 Exit 3
- 26. Chapter 8 26 Junction Transformation Rules Entry 1 Exit Entry 2 Entry 1 Exit Entry 2 Where two or more entry points join, connect the entry variables to an OR gate The Exit is the output of the OR gate
- 27. Chapter 8 27 Conditional Output Box Rules X 1 Entry Exit 1 OUTPUT X Entry Exit 1 OUTPUT Entry point is Enable input. The Condition is the "Select" input. Demultiplexer Outputs are the Exit points. The Control OUTPUT is the same signal as the exit value.
- 28. Chapter 8 28 Multiplier Example: Flip-flop per State Design Logic Diagram D C IDLE D C MUL0 D C MUL1 Initialize Clear _C Load Shift_dec Clock Z Q0 4 1 G 2 5 4 5 1 1 5 DEMUX D0 D1 A0 EN 2 DEMUX D1 D0 A0 EN START
- 29. Chapter 8 29 Summary Datapath and Control Algorithmic State Machines (ASM) • ASM chart • Timing considerations ASM chart examples • Binary multiplier
- 30. Chapter 8 30 Terms of Use © 2004 by Pearson Education,Inc. All rights reserved. The following terms of use apply in addition to the standard Pearson Education Legal Notice. Permission is given to incorporate these materials into classroom presentations and handouts only to instructors adopting Logic and Computer Design Fundamentals as the course text. Permission is granted to the instructors adopting the book to post these materials on a protected website or protected ftp site in original or modified form. All other website or ftp postings, including those offering the materials for a fee, are prohibited. You may not remove or in any way alter this Terms of Use notice or any trademark, copyright, or other proprietary notice, including the copyright watermark on each slide. Return to Title Page