Logic gates verification using universal gates
- 1. EXPERIMENT-2 OBJECTIVE--Realization of different logical gates by using NAND/NOR Logic (universal gates). SIMULATION ENVIRONMENT-- LTspice THEORY--Universal gates- The NAND & NOR gates are called as Universal gates. Because it is possible to implement any Boolean expression with the help of only NAND or only NOR gate. We can construct AND, OR, NOT, X-OR & X-NOR gates. All gates using NAND Gate:- 1) Not using NAND:- Y = (A.A)’ => Y = (A)’ FIG-1.i Circuit for NOT Gate INPUT OUTPUT 0 1 1 0
- 2. FIG-1.ii Pulse Output for NOT Gate 2) AND gate using NAND:- Y = ((A.B)’)’ => Y = (A.B) FIG-2.i Circuit for AND Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 0 1 0 0 1 1 1
- 3. FIG-2.ii Pulse Output for AND Gate 3) OR gate using NAND:- (A.B)’ = A’ + B’ => (A’.B’)’ = A’’ + B’’ = A + B FIG-3.i Circuit for OR Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 1
- 4. FIG-3.ii Pulse Output for OR Gate 4) Ex-OR gate using NAND:- Y = A’B + AB’ FIG-4.i Circuit for Ex-OR Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 0
- 5. FIG-4.ii Pulse Output for Ex-OR Gate 5) Ex-NOR gate using NAND:- Y = AB+ A’B’ FIG-5.i Circuit for Ex-NOR Gate INPUT A INPUT B OUTPUT 0 0 1 0 1 0 1 0 0 1 1 1
- 6. FIG-5.ii Pulse Output for Ex-NOR Gate All gates using NOR Gate:- 1) NOR gates as NOT gate Y = (A+A)’ => Y = (A)’ FIG-1.i Circuit for NOT Gate INPUT OUTPUT 0 1 1 0
- 7. FIG-1.ii Pulse Output for NOT Gate 2) NOR gates as OR gate Y = ((A+B)’)’ => Y = (A+B) FIG-2.i Circuit for OR Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 1
- 8. FIG-2.ii Pulse Output for OR Gate 3) NOR gates as AND gate - From De-Morgan’s theorems: (A+B)’ = A’B’ => (A’+B’)’ = A’’B’’ = AB FIG-3.i Circuit for AND Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 0 1 0 0 1 1 1
- 9. FIG-3.ii Pulse Output for AND Gate 4) NOR gates as Ex-OR gate Y = A’B+ AB’ FIG-4.i Circuit for Ex-OR Gate INPUT A INPUT B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 0
- 10. FIG-4.ii Pulse Output for Ex-OR Gate 5) NOR gates as Ex-NOR gate Y = AB + A’B’ FIG-5.i Circuit for Ex-NOR Gate INPUT A INPUT B OUTPUT 0 0 1 0 1 0 1 0 0 1 1 1
- 11. FIG-5.ii Pulse Output for Ex-NOR Gate RESULT--All the truth table of logic gates AND , OR , NOT , Ex-OR , Ex-NOR are verified by using the integrated circuits of NAND and NOR (UNIVERSAL GATES) only.