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Session 07 v.3

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Here are the steps to use Xilinx to generate instantiations using structural description: 1. Create a VHDL entity that defines the ports of the top-level module. 2. Create VHDL components for any lower-level modules needed. Define their ports. 3. In the architecture of the top-level module, declare instances of the lower-level components. 4. Connect the ports of each instance using a port map. You can use positional or named association. 5. Compile and synthesize the design in Xilinx. This will generate the necessary instantiations. 6. Simulate the design to verify functionality of the instantiated modules. Let me know if

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• Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Seven » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
about Start Group • Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Six 2
mini-Project Discussion • Click to edit Master text styles – Second level B(i)=[A(i)+C(i)]mod2 A(i) • Third B(i) Scrambler level – Fourth level » Fifth level Session Four 3
Outline • Click to edit Master text styles – Second level • Third level Structural Description Generic Using Package 7 – Fourth level Generate Statement » Fifth level Session Seven 4
Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 5
Structural Description • Click to edit Master textlevels Structural description allows having multiple styles – Second level of hierarchy in the design • Third Top- Down Design level – Fourth level The Design starts with the top-level block. This 8 bit » Fifth level design is then partitioned into lower-level blocks till Adder the root-level of your design is reached. Full Adder Half Adder Session Seven 6
Structural Description • Click to edit Master text styles – Second level Bottom-Up Design • Third level Used when the design is very large. – Fourth level » Fifth level When using a bottom-up design methodology. the design begins with knowledge of the root and is then partitioned based on which primitives are available as leaf-nodes. Session Seven 7
Structural Description [Component] • Click to edit Master text styles 1-Component Declaration – Second level The basic element of hirarichal design is component • <component_name> component Third level port ( <port_names>: <mode> <type>; – Fourth level <port_names>: <mode> <type>; …. » Fifth level ); end component; Component : Creates an instance of another entity. Note The definition of the component is like the definition of the entity. Component is Previously coded, simulated, synthesized and placed in design library Components are defined inside Architecture in Architecture Declaration before begin Session Seven 8
Structural Description [Instantiation] 2-Component instantiation and Interconnections method 1 • Click to edit Master text styles instance_name: component_name – Second level port map (signal1,signal2,…); • Third level – Fourth level Each signal is written in the position that describe which port it belongs to which means that the » Fifth level first signal written here represent the first port in the component. That is named association-instantiation by position. Note if you needn't use special output port, Using the key word open (that mean this port will be unconnected). This method is easier but bad in readability. Session Seven 9
Structural Description [Instantiation] 2-Component instantiation and Interconnections method 2 • Click to edit Master text styles <instance_name>: <component_name > – Second level port map( <port_name> => <sig_name>, • Third level <port_name> => <sig_name>, …. <port_name> – Fourth level => <sig_name> ); » Fifth level That is named instantiation by name. Order is not important. • The left part of the expression serve as name of port of the component • The right part of the expression serves as name of connected signal (or port of other component). Session Seven 10
Example 25 Logic Gate • Click to edit Master text styles entity test is Port ( – Second level a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; • Third level d : in STD_LOGIC; f : out STD_LOGIC); end test; – Fourth level » Fifth level architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; AND in2 : in STD_LOGIC; gate OR out_or : out STD_LOGIC); gate end component ; AND gate component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; Session Seven 11
Example 25 Logic Gate • Click to edit Master text styles – Second level … • Third level signal sig1,sig2 : std_logic; begin – Fourth level u1:and_gate » Fifth level port map (a,b,sig1); u2:and_gate AND port map (c,d,sig2); gate OR u3:or_gate gate AND port map (sig1,sig2,f); gate end Behavioral; Session Seven 12
Example 26 Logic Gate • Click to edit Master text styles entity test is Port ( – Second level a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; • Third level d : in STD_LOGIC; f : out STD_LOGIC); end test; – Fourth level » Fifth level architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; AND in2 : in STD_LOGIC; gate OR out_or : out STD_LOGIC); gate end component ; AND gate component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; Session Seven 13
Example 26 Logic Gate • Click to edit Master text styles signal sig1,sig2 : std_logic; begin – Second level u1:and_gate • Third level port map ( in1 => a, – Fourth level in2 => b, out_and => sig1); » Fifth level u2:and_gate port map ( AND in1 => c, gate in2 => d, OR out_and => sig2); gate AND u3:or_gate gate port map ( in1 => sig1, in2 => sig2, out_or => f); end Behavioral; Session Seven 14
Lab 09 • Click to edit Master text styles Title: Goal: – Second level Using Structural Description •  ThirdXilinx to Generate Instantiations Using level  Using Structural Described codes – Fourth level » Fifth level Session Seven 15
Lab 09 • Click to edit Master text styles – Second level Entity comp4 is port ( • Third level a , b : in std_logic_vector(3 downto 0); eq : out std_logic ); End comp4 ; – Fourth level Architecture struct of comp4 is » Fifth level Component xnor_2 is port ( g , f : in std_logic ; y : out std_logic ); End component ; Component and_4 is port ( in1,in2,in3,in4 :in std_logic; out1 : out std_logic ); End component ; … Session Seven 16
Lab 09 • Click to edit Master text styles … – Second level • Third level Signal x : std_logic_vector ( 3 downto 0 ) ; Begin – Fourth level U1 : xnor_2 port map (»a(0) ,level , x(0) ) ; U2 : Fifth b(0) xnor_2 port map ( a(1) , b(1) , x(1) ) ; U3 : xnor_2 port map ( a(2) , b(2) , x(2) ) ; U4 : xnor_2 port map ( a(3) , b(3) , x(3) ) ; U5 : and_4 port map ( x(0) , x(1) , x(2) , x(3) , eq ) ; End struct ; Session Seven 17
Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 18
Generic • Click to edit Master text styles VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy – Second level Syntax • Third level – Fourth level generic ( <identifier>: level [:= default_value]; » Fifth type <identifier>: type [:= default_value]) ); 4-bit counter N-bit counter 8-bit counter Session Seven 19
Example 27 Logic Gate • Click to edit Master text styles AND – Second level library IEEE; gate • Third level use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; – Fourth level use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity generic_and » Fifth level is generic (N : integer := 4 ); port(A, B : in std_logic_vector (N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) ); End entity; Architecture behave of generic_and is Begin Z <= A and B; End architecture Session Seven 20
Example 28 N-bit Full Adder C_in • Click to edit Master text styles – Second level A N bit Sum • Third level Full Adder Entity F_adder – Fourth level is B Generic ( N : integer := 4 ); Port ( » Fifth level A, B : in std_logic_vector(N-1 downto 0); C_in : in std_logic ; C_out Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic ) ; End F_adder ; … Session Seven 21
Example 28 N-bit Full Adder C_in • Click to edit Master text styles Architecture struct of f_adder is – Second level Component n_adder Generic ( N : integer := 4 ); A N bit Sum Port ( • Third level A,B : in std_logic_vector(N-1 downto 0); Full Adder C_in : in – Fourth level std_logic ; B Sum : out std_logic_vector(N-1 downto 0); » Fifth level C_out : out std_logic ); End component ; C_out Begin U1 : n_adder generic map (8) port map ( A => A, B => B , c_in => C_in , sum => Sun , c_out => C_out); End struct Session Seven 22
Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 23
Using Packages • Click to edit Master text styles Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once – Second level 1) This makes the top-level entity code cleaner • Third level 2) It also allows that complete package to be used by another designer – Fourth level A package can contain » Fifth level 1) Components 2) Functions, Procedures 3) Types, Constants Session Seven 24
Example 29 Logic circuit using package • Click to edit Master text styles library IEEE; use IEEE.STD_LOGIC_1164.ALL; – Second level use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; • Third level package logic_circuit is – Fourth component or_gate is level Port ( in1 : in STD_LOGIC; in2 : in » Fifth level STD_LOGIC; out_or : out STD_LOGIC); end component ; AND gate component and_gate is OR Port ( in1 : in STD_LOGIC; gate in2 : in STD_LOGIC; AND out_and : out STD_LOGIC); gate end component; constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; ---const definition end logic_circuit; Session Seven 25
Example 29 Logic circuit using package • Click to edit Master text styles library IEEE; . – Second level use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; u1:and_gate port map ( in1 => a, • Third level use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.logic_circuit.all; in2 => b, out_and => sig1); – Fourth level entity test is u2:and_gate port map ( Port ( » Fifth level in1 => c, a : in STD_LOGIC; in2 => d, b : in STD_LOGIC; out_and => sig2); c : in STD_LOGIC; d : in STD_LOGIC; u3:or_gate port map ( Out1 : out STD_LOGIC_vector (3 downto 0); in1 => sig1, f : out STD_LOGIC); in2 => sig2, end test; out_or => f); architecture Behavioral of test is out1<= const1; signal sig1,sig2 : std_logic; begin . end Behavioral; Session Seven 26
Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 27
Generate Statement • Click to edit Master text styles The generate statement simplifies description of regular design structures. Usually it is used to – Second level specify a group of identical components using just one component specification and repeating it using the generate mechanism. • Third level Declaration – Fourth level Label : for identifier IN range » Fifth level GENERATE (concurrent assignments) . . END GENERATE; Session Seven 28
Example 30 SEREIS OF XOR GATES • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity; Session Seven 29
Example 30 SEREIS OF XOR GATES • Click xor_out(1) xor_out(2) to edit Master text styles xor_out(3) – Second level xor_out(4) xor_out(5) xor_out(6) • Third level – Fourth level » Fifth level xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); parity_out <= xor_out(6) XOR parity_in(7); Session Seven 30
Example 30 SEREIS OF XOR GATES • Click xor_out(1) xor_out(2) to edit Master text styles xor_out(3) – Second level xor_out(0) xor_out(4) xor_out(5) xor_out(6) • Third level xor_out(7) – Fourth level » Fifth level xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7); Session Seven 31
Example 30 SEREIS OF XOR GATES • Click to edit Master text styles – Second level ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN • Third level xor_out(0) <= parity_in(0); – Fourth level G2: FOR i IN 1 TO 7 GENERATE » Fifth level xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow; Session Seven 32
Start Notes [Synthesis Notes] • Click to edit Master text styles architecture rtl of full adder Is – Second level Structural Description signal col .co2: std_logic; signal a_xor_b : std_logic; • Third level begin ul: entity work.half_adder(behave) In VHDL-93 standard, an – pair entity-architecture Fourth level port map (a,b.axorb.col); u2: entity work.half_adder(behave) may be directly » Fifth level port map( axorb,ci,s,co2); instantiated, i.e. component need not co< col or cO2; declared. This is easier. but not readably. end architecture rtl; Session Six 33
Assignment 07 • Click to edit Master text styles Study Well for Next session’s Evaluation Test – Second level • Third level – Fourth level » Fifth level Session Seven 34
Summary • Click to edit Master text styles - Structural description allows having multiple levels of hierarchy in the design - – Second level VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy. - • Third level The generate statement used to specify a group of identical components using just one component specification and repeating it using the generate mechanism. – Fourth level » Fifth level Examples Exercises Labs 25-30 - 9 Session Seven 35
Time for Your Questions • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session Seven 36
Take Your Notes Print the slides and take your notes here -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Second level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Third level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Fourth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- » Fifth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------
See You Next Session .. Don’t miss • Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level

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Session 07 v.3

  • 1. • Click to edit Master text styles – Second level • Third level – Fourthg i t a l D e s i g n u s i n g V H D L D i level Session Seven » Fifth level Introduced by Cairo-Egypt Version 03 – June 2012 1
  • 2. about Start Group • Click to edit Master text styles Mahmoud Abdellatif – Second level Alaa Salah Shehata Mohamed level • Third Salah Mohamed Talaat – Fourth level » Fifth level start.courses@gmail.com www.slideshare.net/StartGroup www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com + 02 0122-4504158 M.A www.youtube.com/StartGroup2011 + 02 0128-0090250 A.S Session Six 2
  • 3. mini-Project Discussion • Click to edit Master text styles – Second level B(i)=[A(i)+C(i)]mod2 A(i) • Third B(i) Scrambler level – Fourth level » Fifth level Session Four 3
  • 4. Outline • Click to edit Master text styles – Second level • Third level Structural Description Generic Using Package 7 – Fourth level Generate Statement » Fifth level Session Seven 4
  • 5. Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 5
  • 6. Structural Description • Click to edit Master textlevels Structural description allows having multiple styles – Second level of hierarchy in the design • Third Top- Down Design level – Fourth level The Design starts with the top-level block. This 8 bit » Fifth level design is then partitioned into lower-level blocks till Adder the root-level of your design is reached. Full Adder Half Adder Session Seven 6
  • 7. Structural Description • Click to edit Master text styles – Second level Bottom-Up Design • Third level Used when the design is very large. – Fourth level » Fifth level When using a bottom-up design methodology. the design begins with knowledge of the root and is then partitioned based on which primitives are available as leaf-nodes. Session Seven 7
  • 8. Structural Description [Component] • Click to edit Master text styles 1-Component Declaration – Second level The basic element of hirarichal design is component • <component_name> component Third level port ( <port_names>: <mode> <type>; – Fourth level <port_names>: <mode> <type>; …. » Fifth level ); end component; Component : Creates an instance of another entity. Note The definition of the component is like the definition of the entity. Component is Previously coded, simulated, synthesized and placed in design library Components are defined inside Architecture in Architecture Declaration before begin Session Seven 8
  • 9. Structural Description [Instantiation] 2-Component instantiation and Interconnections method 1 • Click to edit Master text styles instance_name: component_name – Second level port map (signal1,signal2,…); • Third level – Fourth level Each signal is written in the position that describe which port it belongs to which means that the » Fifth level first signal written here represent the first port in the component. That is named association-instantiation by position. Note if you needn't use special output port, Using the key word open (that mean this port will be unconnected). This method is easier but bad in readability. Session Seven 9
  • 10. Structural Description [Instantiation] 2-Component instantiation and Interconnections method 2 • Click to edit Master text styles <instance_name>: <component_name > – Second level port map( <port_name> => <sig_name>, • Third level <port_name> => <sig_name>, …. <port_name> – Fourth level => <sig_name> ); » Fifth level That is named instantiation by name. Order is not important. • The left part of the expression serve as name of port of the component • The right part of the expression serves as name of connected signal (or port of other component). Session Seven 10
  • 11. Example 25 Logic Gate • Click to edit Master text styles entity test is Port ( – Second level a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; • Third level d : in STD_LOGIC; f : out STD_LOGIC); end test; – Fourth level » Fifth level architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; AND in2 : in STD_LOGIC; gate OR out_or : out STD_LOGIC); gate end component ; AND gate component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; Session Seven 11
  • 12. Example 25 Logic Gate • Click to edit Master text styles – Second level … • Third level signal sig1,sig2 : std_logic; begin – Fourth level u1:and_gate » Fifth level port map (a,b,sig1); u2:and_gate AND port map (c,d,sig2); gate OR u3:or_gate gate AND port map (sig1,sig2,f); gate end Behavioral; Session Seven 12
  • 13. Example 26 Logic Gate • Click to edit Master text styles entity test is Port ( – Second level a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; • Third level d : in STD_LOGIC; f : out STD_LOGIC); end test; – Fourth level » Fifth level architecture Behavioral of test is component or_gate is Port ( in1 : in STD_LOGIC; AND in2 : in STD_LOGIC; gate OR out_or : out STD_LOGIC); gate end component ; AND gate component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC); end component; Session Seven 13
  • 14. Example 26 Logic Gate • Click to edit Master text styles signal sig1,sig2 : std_logic; begin – Second level u1:and_gate • Third level port map ( in1 => a, – Fourth level in2 => b, out_and => sig1); » Fifth level u2:and_gate port map ( AND in1 => c, gate in2 => d, OR out_and => sig2); gate AND u3:or_gate gate port map ( in1 => sig1, in2 => sig2, out_or => f); end Behavioral; Session Seven 14
  • 15. Lab 09 • Click to edit Master text styles Title: Goal: – Second level Using Structural Description •  ThirdXilinx to Generate Instantiations Using level  Using Structural Described codes – Fourth level » Fifth level Session Seven 15
  • 16. Lab 09 • Click to edit Master text styles – Second level Entity comp4 is port ( • Third level a , b : in std_logic_vector(3 downto 0); eq : out std_logic ); End comp4 ; – Fourth level Architecture struct of comp4 is » Fifth level Component xnor_2 is port ( g , f : in std_logic ; y : out std_logic ); End component ; Component and_4 is port ( in1,in2,in3,in4 :in std_logic; out1 : out std_logic ); End component ; … Session Seven 16
  • 17. Lab 09 • Click to edit Master text styles … – Second level • Third level Signal x : std_logic_vector ( 3 downto 0 ) ; Begin – Fourth level U1 : xnor_2 port map (»a(0) ,level , x(0) ) ; U2 : Fifth b(0) xnor_2 port map ( a(1) , b(1) , x(1) ) ; U3 : xnor_2 port map ( a(2) , b(2) , x(2) ) ; U4 : xnor_2 port map ( a(3) , b(3) , x(3) ) ; U5 : and_4 port map ( x(0) , x(1) , x(2) , x(3) , eq ) ; End struct ; Session Seven 17
  • 18. Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 18
  • 19. Generic • Click to edit Master text styles VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy – Second level Syntax • Third level – Fourth level generic ( <identifier>: level [:= default_value]; » Fifth type <identifier>: type [:= default_value]) ); 4-bit counter N-bit counter 8-bit counter Session Seven 19
  • 20. Example 27 Logic Gate • Click to edit Master text styles AND – Second level library IEEE; gate • Third level use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; – Fourth level use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity generic_and » Fifth level is generic (N : integer := 4 ); port(A, B : in std_logic_vector (N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) ); End entity; Architecture behave of generic_and is Begin Z <= A and B; End architecture Session Seven 20
  • 21. Example 28 N-bit Full Adder C_in • Click to edit Master text styles – Second level A N bit Sum • Third level Full Adder Entity F_adder – Fourth level is B Generic ( N : integer := 4 ); Port ( » Fifth level A, B : in std_logic_vector(N-1 downto 0); C_in : in std_logic ; C_out Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic ) ; End F_adder ; … Session Seven 21
  • 22. Example 28 N-bit Full Adder C_in • Click to edit Master text styles Architecture struct of f_adder is – Second level Component n_adder Generic ( N : integer := 4 ); A N bit Sum Port ( • Third level A,B : in std_logic_vector(N-1 downto 0); Full Adder C_in : in – Fourth level std_logic ; B Sum : out std_logic_vector(N-1 downto 0); » Fifth level C_out : out std_logic ); End component ; C_out Begin U1 : n_adder generic map (8) port map ( A => A, B => B , c_in => C_in , sum => Sun , c_out => C_out); End struct Session Seven 22
  • 23. Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 23
  • 24. Using Packages • Click to edit Master text styles Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once – Second level 1) This makes the top-level entity code cleaner • Third level 2) It also allows that complete package to be used by another designer – Fourth level A package can contain » Fifth level 1) Components 2) Functions, Procedures 3) Types, Constants Session Seven 24
  • 25. Example 29 Logic circuit using package • Click to edit Master text styles library IEEE; use IEEE.STD_LOGIC_1164.ALL; – Second level use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; • Third level package logic_circuit is – Fourth component or_gate is level Port ( in1 : in STD_LOGIC; in2 : in » Fifth level STD_LOGIC; out_or : out STD_LOGIC); end component ; AND gate component and_gate is OR Port ( in1 : in STD_LOGIC; gate in2 : in STD_LOGIC; AND out_and : out STD_LOGIC); gate end component; constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; ---const definition end logic_circuit; Session Seven 25
  • 26. Example 29 Logic circuit using package • Click to edit Master text styles library IEEE; . – Second level use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; u1:and_gate port map ( in1 => a, • Third level use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.logic_circuit.all; in2 => b, out_and => sig1); – Fourth level entity test is u2:and_gate port map ( Port ( » Fifth level in1 => c, a : in STD_LOGIC; in2 => d, b : in STD_LOGIC; out_and => sig2); c : in STD_LOGIC; d : in STD_LOGIC; u3:or_gate port map ( Out1 : out STD_LOGIC_vector (3 downto 0); in1 => sig1, f : out STD_LOGIC); in2 => sig2, end test; out_or => f); architecture Behavioral of test is out1<= const1; signal sig1,sig2 : std_logic; begin . end Behavioral; Session Seven 26
  • 27. Outline • Click to edit Master text styles Structural Description – Second level Generic • Third level Using Package – Fourth level Generate Statement » Fifth level Session Seven 27
  • 28. Generate Statement • Click to edit Master text styles The generate statement simplifies description of regular design structures. Usually it is used to – Second level specify a group of identical components using just one component specification and repeating it using the generate mechanism. • Third level Declaration – Fourth level Label : for identifier IN range » Fifth level GENERATE (concurrent assignments) . . END GENERATE; Session Seven 28
  • 29. Example 30 SEREIS OF XOR GATES • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity; Session Seven 29
  • 30. Example 30 SEREIS OF XOR GATES • Click xor_out(1) xor_out(2) to edit Master text styles xor_out(3) – Second level xor_out(4) xor_out(5) xor_out(6) • Third level – Fourth level » Fifth level xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); parity_out <= xor_out(6) XOR parity_in(7); Session Seven 30
  • 31. Example 30 SEREIS OF XOR GATES • Click xor_out(1) xor_out(2) to edit Master text styles xor_out(3) – Second level xor_out(0) xor_out(4) xor_out(5) xor_out(6) • Third level xor_out(7) – Fourth level » Fifth level xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7); Session Seven 31
  • 32. Example 30 SEREIS OF XOR GATES • Click to edit Master text styles – Second level ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN • Third level xor_out(0) <= parity_in(0); – Fourth level G2: FOR i IN 1 TO 7 GENERATE » Fifth level xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow; Session Seven 32
  • 33. Start Notes [Synthesis Notes] • Click to edit Master text styles architecture rtl of full adder Is – Second level Structural Description signal col .co2: std_logic; signal a_xor_b : std_logic; • Third level begin ul: entity work.half_adder(behave) In VHDL-93 standard, an – pair entity-architecture Fourth level port map (a,b.axorb.col); u2: entity work.half_adder(behave) may be directly » Fifth level port map( axorb,ci,s,co2); instantiated, i.e. component need not co< col or cO2; declared. This is easier. but not readably. end architecture rtl; Session Six 33
  • 34. Assignment 07 • Click to edit Master text styles Study Well for Next session’s Evaluation Test – Second level • Third level – Fourth level » Fifth level Session Seven 34
  • 35. Summary • Click to edit Master text styles - Structural description allows having multiple levels of hierarchy in the design - – Second level VHDL provides an easy way to create generic design units that can be used several times with different properties in the design hierarchy. - • Third level The generate statement used to specify a group of identical components using just one component specification and repeating it using the generate mechanism. – Fourth level » Fifth level Examples Exercises Labs 25-30 - 9 Session Seven 35
  • 36. Time for Your Questions • Click to edit Master text styles – Second level • Third level – Fourth level » Fifth level Session Seven 36
  • 37. Take Your Notes Print the slides and take your notes here -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Click to edit Master text styles -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Second level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- • Third level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- – Fourth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- » Fifth level -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------
  • 38. See You Next Session .. Don’t miss • Click to edit Master text styles Thank – Second level • Third level – Fourth level You » Fifth level