A FLOATING POINT DIVISION UNIT BASED ON TAYLOR-SERIES EXPANSION ALGORITHM AND ITERATIVE LOGARITHMIC MULTIPLIER

Natarajan Meghanathan et al. (Eds) : NeCoM, CSITEC - 2016
pp. 19–30, 2016. © CS & IT-CSCP 2016 DOI : 10.5121/csit.2016.61203
A FLOATING POINT DIVISION UNIT
BASED ON TAYLOR-SERIES EXPANSION
ALGORITHM AND ITERATIVE
LOGARITHMIC MULTIPLIER
Riyansh K. Karani, Akash K. Rana, Dhruv H. Reshamwala and
Kishore Saldanha
Electronics Department,
Dwarkadas J. Sanghvi College of Engineering, Mumbai
riyansh.karani.011235@gmail.com
akash9182akash@gmail.com
dhr.reshamwala@gmail.com
kishoresaldanha@gmail.com
ABSTRACT
Floating point division, even though being an infrequent operation in the traditional sense, is
indis-pensable when it comes to a range of non-traditional applications such as K-Means
Clustering and QR Decomposition just to name a few. In such applications, hardware support
for floating point division would boost the performance of the entire system. In this paper, we
present a novel architecture for a floating point division unit based on the Taylor-series
expansion algorithm. We show that the Iterative Logarithmic Multiplier is very well suited to be
used as a part of this architecture. We propose an implementation of the powering unit that can
calculate an odd power and an even power of a number simultaneously, meanwhile having little
hardware overhead when compared to the Iterative Logarithmic Multiplier.
KEYWORDS
Floating point division, Iterative Logarithmic Multiplier, Taylor-series
1. INTRODUCTION
Approximation methods such as Newton-Raphson and Taylor-series can be used to approximate
functions where direct computation of these functions is either computationally very expensive or
not possible. The Taylor-series expansion is an approximation method that generates a high order
polynomial approximation of a function at some value in its domain. The idea is simple; given
that a function and its first derivatives are continuous at some point in its domain, the function
can be approximated by a polynomial of degree at that point. The higher the order of this
polynomial, the better is the approximation. Following on this idea, the reciprocal of a number
can be approximated as a very simple Taylor-series polynomial, and thus the problem of division
of one number by another is essentially reduced to multiplication of one number and the Taylor-

20 Computer Science & Information Technology (CS & IT)
series polynomial of the other [6]. Calculating the terms of the Taylor-series polynomial that
approximates the reciprocal of a number involves calculating the powers of itself
where calculating each higher power generates a better approximation.
Naturally, there is a need of a multiplier unit to calculate these powers, and the performance of
the floating point division unit then depends almost solely on the performance of the multiplier
unit. There are many popular multiplier architectures in use today [3]. The Iterative Logarithmic
Multiplier is one such multiplier architecture [12]. What makes it an attractive choice is that it is
highly programmable. The accuracy of the product generated by this multiplier can be precisely
controlled, which comes in very handy when one does not need full precision multiplication, like
in the case of digital signal processing.
But perhaps what is even more important is that because of its inherent nature, its implementation
is very hardware efficient when it comes to computation of squares. This is because the
mathematical description of the Iterative Logarithmic Multiplier is quite simplified when
multiplying a number with itself, as when compared to multiplying two different numbers.
Because every even power of a number can be represented as a square of a smaller power
of the number every alternate power of is representable as a square of some other
number. Hence, the Iterative Logarithmic Multiplier is a very suitable candidate when choosing a
multiplier architecture for calculating the terms of the Taylor-series polynomial approximation of
a reciprocal.
In this paper, we present an architecture for a floating point division unit based on the Iterative
Logarithmic Multiplication algorithm, and the Taylor-series expansion algorithm. The proposed
architecture is designed to be hardware efficient, as is the requirement when designing
architectures for high speed computational units. We start by describing the Taylor-series
expansion algorithm in section II, and analyse the approximation errors generated when using this
approach. We then introduce the methodology for calculating the reciprocal of a number using
the Taylor-series approach, and derive a quantitative measure of the generated error. Since the
approach above requires an initial approximation of the reciprocal, in section III, we start by
describing and analysing linear approximation as a possible approach. We then build on this to
present the piecewise linear approximation based approach that we have employed in our
implementation of the floating point division unit. In section IV, we describe the Iterative
Logarithmic Multiplier as proposed by Babić , Avramović and Bulić [12], followed by the
discussion and implementation of the proposed squaring unit in section V. Finally, we present the
architecture for the proposed powering unit in section VI, and discuss its implementation and
features.
2. TAYLOR-SERIES EXPANSION ALGORITHM

Computer Science & Information Technology (CS & IT) 21

3. INITIAL APPROXIMATION
As stated in the previous section, we need an initial approximation of the inverse of a number, in
order to calculate a more precise approximation using the Taylor-series expansion algorithm, and
according to equation (7), the number of iterations required to obtain an approximation with a
desired precision depends on the initial approximation. So, it is very important to select an
appropriate method for finding an initial approximation. There are different kinds of methods [5]
based on linear approximation, direct lookup tables [7] [8] [11], table lookup followed by
multiplication [4] and polynomial approximations [9]. In our implementation, we choose a
different approach. We employ a piecewise linear approximation for generating the initial
approximation, and we show that one can obtain any desired amount of precision using this
method, without much increase in complexity.
Figure 1: Plot showing the actual and linear Figure 2: Plot showing the values of
approximation values of x-1
, m for x in the range [1,2]
for a = 1 and b = 2

Figure 3: Piecewise linear approximation of x-1
for x in the range [1,2], derived for n = 5
Table I: Piecewise Linear approximation segments
4. ITERATIVE LOGARITHMIC MULTIPLIER
Logarithmic Number System (LNS) based multipliers are a good choice when there is a
possibility of trading accuracy for speed (such as in Digital Signal Processing). The main
advantage of LNS based multipliers is the substitution of multiplication with addition, which is a
much simpler operation in terms of complexity. LNS multipliers can be divided into two
categories [12], one based on methods that use lookup-tables, and the others based on Mitchell’s
algorithm [10]. The major drawback with Mitchell’s algorithm is the error in the product due to
the piecewise linear approximation of the logarithmic curve. The Iterative Logarithmic
Multiplier, as the name suggests, proposes an iterative solution to computer this error term, and
hence generate a better approximation to the product.

The binary representation of a number can be written as
Figure 4: Block diagram of an Figure 5: Architecture of the
Iterative Logarithmic Multiplier proposed squaring unit

5. SQUARING UNIT

6. POWERING UNIT
Figure 6: Flow diagram indicating the operation Figure 7: System implementation
of the powering unit for calculating
up to 12 powers of x

7. CONCLUSION
In this paper, we propose and investigate a new architecture for a floating point division unit. We
show that the Taylor-series expansion algorithm can be used to generate approximations for the
reciprocal of a number up to an arbitrary precision, and analyse the errors for the same. We
propose a new piecewise linear approximation based method to generate the first approximation
required by the Taylor-series expansion algorithm, and present an extensive analysis. We then
present the architecture for a squaring unit derived from the Iterative Logarithmic Multiplier, and
argue that it requires less than 50% hardware, as compared to the Iterative Logarithmic
Multiplier. Finally, we present a cumulative implementation of the powering unit, and discuss
some of the enhancements made in order to further boost its performance. The complete system is
illustrated in Figure 7.
The performance of the system can be improved by pipelining the architecture for the Iterative
Logarithmic Multiplier [12] and the squaring unit, but at the cost of increase in hardware
utilization.
REFERENCES
[1] Tom M. Apostol. Calculus Vol. 1. 2nd ed. 2013, pp. 272–303.
[2] Birne Binegar. “Math 4513: Numerical Analysis”. 1998.
URL:https://math.okstate.edu/people/binegar/4513-F98/4513-l01.pdf.
[3] Deepak Bordiya and Lalit Bandil. “Comparative Analysis Of Multipliers (serial and parallel with
radix based on booth algorithm)”. In: International Journal of Engineering Research and Technology
Vol.2 - Issue 9 (Sept. 2013).
[4] Zhan Guo, Dongdong Chen, Bintian Zhou and Peter Nilsson. “Design and Implementation of
Reciprocal Unit”. In: IEEE (Jan. 2007)
[5] Ankit Khandelwal and Gaurav Agarwal. A Newton Raphson Divider Based on Improved Reciprocal
Approximation Algorithm. Dec. 2006.
[6] Taek-Jun Kwon. “Floating-Point unit design using Taylor-series Expansion algorithms”. PhD thesis.
University of Southern California, 2009.
[7] Albert A. Liddicoat and Michael J. Flynn. “High Performance Floating Point Divide”. In: Digital
Systems Design, 2001. Proceedings. Euromicro Symposium on. Sept. 2001.
[8] Naofumi Takagi, Masayuki Ito, and Shuzo Yajima. “Efficient Initial Approximation and Fast
Converging Methods for Division and Square Root”. In: ARITH ’95 Proceedings of the 12th
Symposium on Computer Arithmetic. 1995.

[9] Jean-Michel Muller, Milos Ercegovac and Arnaud Tisserand. “Simple Seed Architectures for
Reciprocal and Square Root Reciprocal”. In: INRIA RR-5720 (2005), p. 25.
[10] J.N. Mitchell. “Computer multiplication and division using binary logarithms”. In: IRE Transactions
on Electronic Computers EC-11 (Aug. 1962), pp. 512–517.
[11] Oskar Mencer, Patrick Hung, Hossam Fahmy and Michael J. Flynn. “Fast Division algorithm with a
Small Lookup Table”. In: Circuits, Systems and Computers, 1997. Conference Record. 1997 11th
Asilomar Conference on. 1997.
[12] Patricio Bulić, Zdenka Babić, Aleksej Avramović.“An Iterative Logarithmic Multiplier”. In:
Elektrotehnis̆ ki vestnik 77(1) (2010), pp. 25–30.

A FLOATING POINT DIVISION UNIT BASED ON TAYLOR-SERIES EXPANSION ALGORITHM AND ITERATIVE LOGARITHMIC MULTIPLIER

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