Savastiouk slides
- 1. 1 Moore’s Law – the Z dimensionMoore’s Law – the Z dimension Sergey Savastiouk, Ph.D.Sergey Savastiouk, Ph.D. savastuk@trusi.comsavastuk@trusi.com April 12April 12, 2001, 2001
- 2. 2 Introduction: The next dimension is the Z dimension Step 1: Vertical miniaturization – thinning – Thinner is better – Thinning and handling problems and solutions Step 2: Vertical integration – stacking – Thru-Silicon vias – 3D stacking for system-in-a-chip (SIP) Conclusion: 3D Wafer Level Packaging Presentation OverviewPresentation Overview
- 3. Moore’s Law – the X-Y dimensions.Moore’s Law – the X-Y dimensions. The number of components on a surface of a chip would double every 18 – 24 months.
- 4. 4 ?Si Si Si Si Si Si Si Si Moore’s Law - the Z dimensionMoore’s Law - the Z dimension The number of components in 3D space would double every 18 – 24 months.
- 5. 5 PACKAGEPACKAGE LITHOGRAPHYLITHOGRAPHY DESIGNDESIGN RULERULE 200020001995199519851985 19901990 DIPDIP CSPCSP MCMMCM TCPTCP STACKSTACK TSOPTSOP SOPSOP BGABGAPGAPGA TQFPTQFP QFPQFP BARECHIPBARECHIP STACK MEMORY MODULESTACK MEMORY MODULE SYSTEM ON MODULESYSTEM ON MODULE SYSTEM ON SILICONSYSTEM ON SILICON 1M1M 4M4M 16M16M 64M64M 256M256M 2000200010001000300300200200 0.8um0.8um 0.5um0.5um 0.35um0.35um 0.25um0.25um 0.18um0.18um PIN COUNTPIN COUNT Packaging trendsPackaging trends
- 6. 6 Package and Chip ThicknessPackage and Chip Thickness 0 1000 2000 3000 4000 5000 6000 7000 1981 1986 1992 1996 1999 2002 2006 2012 Package Thickness Bare Die Thickness CSP DIP TQFP BGA PDIP STACK MODULES
- 7. 7 Wafer and Chip ThicknessWafer and Chip Thickness 0 100 200 300 400 500 600 700 800 900 1960 1970 1980 1990 2000 2010 2020 Year of Significant Production Wafer Diameter, mm Wafer Thickness, um Chip Thickness, um DIP PDIP TQFP BGA TSSOP CSP STACK MODULES
- 8. 8 • Step 1: Vertical miniaturization – thinningStep 1: Vertical miniaturization – thinning Thinner is betterThinner is better Why to thin?Why to thin?
- 9. 9 Thinner is betterThinner is better WHY to thin ? Better packaging density More flexible More reliable Better thermal resistance Better yields 50 µm wafer.
- 10. 10 Reduction of thickness by half provides 50% reduction in height and 30% in footprint of packaging Si H1 H2 Si Thinning for smaller space: Why to thin?
- 11. 11 <100 micron thickness for improved reliability, requires damage-free silicon Hitachi Thinning for flexibility: Why to thin ?Thinning for flexibility: Why to thin ?
- 12. 12 Numerical results for reliability: Why to thin ?Numerical results for reliability: Why to thin ? Thick chip: u = 700 µm, b = 1000 µm Thin chip: u = 50 µm, b = 200 µm
- 13. 13 Thermal Resistance vs. Thickness 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 50 100 200 300 Chip Thickness (microns) Thermal Resistance (Deg.C/Watt) Chip Adhesive Chip+Adhesive Improved Power Dissipation: Why to thin?Improved Power Dissipation: Why to thin?
- 14. 14 • Step 1: Vertical miniaturization – thinningStep 1: Vertical miniaturization – thinning Thinning and handling problemsThinning and handling problems and solutionsand solutions How to thin?How to thin? How to handle thinned wafers?How to handle thinned wafers?
- 15. 15 Thinning alternativesThinning alternatives Grinding (leaves damage) Polishing (leaves some damage) Wet etching (removes damage, but wet) Dry etching (removes damage) Silicon Damage
- 16. 16 Argon CF4 C + 4F SiF4 CO2 CO Si WAFER •No induced electrical damage •No vacuum pumps – excellent process control Etch rate suitable for mass production Atmospheric Downstream Plasma: How to thin?Atmospheric Downstream Plasma: How to thin?
- 17. 17 Edge damage yield problems: How to handle? Damaged edges cause wafers to break
- 18. 18 NoTouch™ wafer holding: How to thin?NoTouch™ wafer holding: How to thin? Atmospheric Downstream Plasma Holding Gas NoTouch Holder Wafer Back Side •Maintains planarity of flexible wafers
- 19. 19 Silicon Damage Silicon No damage Damage-free wafer surface: How to thin ?Damage-free wafer surface: How to thin ?
- 20. 20 Damage free edges: How to thin?Damage free edges: How to thin?
- 21. 21 After wet spin etchingAfter grinding or polishing Old technologies After ADP etching New ADP technology Thinning alternatives: How to thin?Thinning alternatives: How to thin?
- 22. 22 Die strength etching vs. grind & CMP: How toDie strength etching vs. grind & CMP: How to thin?thin? Front tensile strength Weibull plot 160um thick die (35 mm squared) 1 10 100 0 200 400 600 800 1000 1200 Tensile strength (N/mm2) Survival probability(%) Grind & cmp /Front side Plasma 10um /FS Plasma 20um /FS
- 23. 23 0 2 4 6 8 10 12 14 16 8 10 12 14 16 18 20 Final Wafer Thickness (mils) Warpage (mils) Post-ADP Warp Post-grind Warp Wafer warp improvementWafer warp improvement
- 24. 24 Damage Free Dicing (in development) Step 2. Controlled depth dicing Step 3. Apply top side tape Step 1. Grind Individual dice Step 4. Etch the backside to singulate
- 25. 25 DBG vs. Damage Free DicingDBG vs. Damage Free Dicing Sawed die showing chipping 40 micron thin ADP etched dice, rounded and smoothed Chip Shifts and Cracks No Chip Shifts and Cracks
- 26. 26 Damage Free DicingDamage Free Dicing SEM pictures of the edges Die top
- 27. 27 • Step 2: Vertical integration – stackingStep 2: Vertical integration – stacking How to thin and to bump on aHow to thin and to bump on a backside in one step?backside in one step? How to stack?How to stack?
- 28. 28 Integration: SOC vs. SOB ,SIP ?Integration: SOC vs. SOB ,SIP ? SIP SOB SOC
- 29. 29 ADP Via Etch (continued)
- 30. 30 ADP thinning of viaADP thinning of via (continued)
- 32. 32 Back Side of a wafer with contact pad Thru-Silicon via results Silicon Metal SiO2
- 33. 33 Thru-Silicon via resultsThru-Silicon via results Back side of a wafer with contact pads
- 34. 34 Direct Chip Attach Solder Paste Or Other Joining Material Substrate Or PWB Active Circuitry Front Side Passivation Exposed Through Hole Contact Tru-CSP™ for front side up : project
- 35. 35 Opto-Electronic Devices Optically Transparent Layer Or Optical Waveguide Optical Signals Can Be Transmitted And Received From Either Surface Optical Waveguide Or Other Silicon Device Tru-CSP™ for opto-electronics: project
- 36. 36 Passive Interposer Surface Of Interposer Contains Elements Like Resistors, Capacitors, Inductors, Networks, Power And Ground Planes And Other Performance Enhancing Functions IC Connected To Passive Interposer Using Any Convienient Joining Technique (e.g. flip chip, ACA, etc.) Tru-CSP™ with passive interposer : project
- 37. 37 Active Devices Joined Face-To-Face Active Circuitry Wafers/Devices Joined Using Any Suitable Joining Technique (i.e. Flip Chip, Anisotropic et al.) Top Wafer/Device Can Be With Or Without Thru-SiliconConnections While Perimeter Contacts Are Shown, Thru-Silicon Connections Can Also Be Area Array Tru-CSP™ face-to-face : project
- 38. 38 3D Stacking An Active Wafer Is Joined To A Passive Interposer Or Other Active Wafer Using Any Convienent Joining Method. The Top Wafer Is Then Thinned To Expose The Through Hole Contacts And The Next Wafer Added. Additional Wafers Can Be Added To The Stack Tru- 3D StackingTru- 3D Stacking : project
- 39. 39 1997, $8m raised, ADP prototyping 1998, Ultra-thin handling prototyping 1999, $10m raised, Product development 2000, System sales and Thru-Silicon dev-t 2001, $18m raised, – Thru-Silicon dev-t hiring process engineers: jobs@trusi.com Conclusion: History of CompanyConclusion: History of Company
- 40. 40 Thinning by ADP and NoTouch handling: – enables low cost damage free thinning – enables low cost damage free dicing Thinning by ADP with Thru-Silicon vias: – enables the new generation of low cost 3D stacking methods of chips and wafers for System-In-a-Package – brings front-end technologies to back-end applications Conclusion: OverallConclusion: Overall SummarySummary