This document discusses double patterning lithography, which is a technique used to print integrated circuit designs smaller than the wavelength of light allows. It involves splitting the mask into two exposures to print features half as dense. The document outlines the challenges in splitting layouts and describes techniques used, including a novel polygon fracturing algorithm, dynamic priority search trees for plane sweeping, converting the problem to a graph coloring one. It shows how to decompose the graph to solve conflicts and presents results on test cases.