Lecture31
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This document discusses array subsystems for implementing logic, including programmable logic arrays (PLAs) and field programmable gate arrays (FPGAs). It describes how PLAs use an AND plane and an OR plane to implement sums-of-products logic functions more efficiently than using read-only memories (ROMs). NOR-NOR PLAs convert the logic to use only NOR gates for improved efficiency. FPGAs build on this concept by using programmable logic blocks containing lookup tables (LUTs) and programmable interconnects to route signals between blocks. This architecture provides flexibility to reprogram the FPGA for different logic functions compared to custom chips.
![To implement in FPGAs, designs need to be
decomposed and mapped to LBs
Map to a LUT in a LB
[Figure form Cong FPGA’01]
S. Reda EN1600 SP’08](https://image.slidesharecdn.com/lecture31-120612015405-phpapp01/85/Lecture31-9-320.jpg)
Lecture31
- 1. Design and Implementation of VLSI Systems (EN1600) Lecture 31: Array Subsystems (PLAs/FPGAs) S. Reda EN1600 SP’08
- 2. Using ROMs to implement logic Inputs Outputs ROM (truth table) In most designs, using ROMs can be extremely inefficient in terms of area S. Reda EN1600 SP’08
- 3. Programmable logic arrays • A Programmable Logic Array performs any function in sum-of-products form. • Literals: inputs & complements • Products / Minterms: AND of literals AND Plane OR Plane • Outputs: OR of Minterms bc ac • Example: Full Adder ab Minterms abc abc abc abc s = abc + abc + abc + abc cout = ab + bc + ac a b c s cout Inputs Outputs S. Reda EN1600 SP’08
- 4. NOR-NOR PLAs • ANDs and ORs are not very efficient in CMOS • Dynamic or Pseudo-nMOS NORs are very efficient • Use DeMorgan’s Law to convert to all NORs AND Plane OR Plane AND Plane OR Plane bc bc ac ac ab ab abc abc abc abc abc abc abc abc a b c a b c s cout s cout S. Reda EN1600 SP’08
- 5. PLA schematic and layout AND Plane OR Plane bc ac ab abc abc abc abc a b c s cout S. Reda EN1600 SP’08
- 6. PLAs vs. ROMS • PLAs are more flexible than ROMs – No need to have 2n rows for n inputs – Only generate the minterms that are needed – Take advantage of logic simplification • PLAs are popular for small-scale circuits that have 2-level implementations • PLAs are not scalable to implement large designs S. Reda EN1600 SP’08
- 7. Programmable logic blocks (lookup tables) Required function Truth table Programmed LUT a a b c y SRAM cells & b 1 000 0 0 0 1 0 8:1 Multiplexer 001 | y 0 0 1 0 c 0 1 0 1 1 010 0 1 1 1 1 011 y y = (a & b) | !c 1 0 0 1 1 100 1 0 1 0 0 101 1 1 0 1 1 110 1 1 1 1 1 111 ab c Programming information could be stored in SRAM or FLASH 4-input LUT is the typical size S. Reda EN1600 SP’08
- 8. FPGA architecture a b 4-input y c LUT mux d flip-flop q e clock Switch Programmable box interconnect Programmable logic blocks S. Reda EN1600 SP’08
- 9. To implement in FPGAs, designs need to be decomposed and mapped to LBs Map to a LUT in a LB [Figure form Cong FPGA’01] S. Reda EN1600 SP’08
- 10. Programmable interconnects (local) S. Reda EN1600 SP’08
- 11. Programmable interconnects (global) Switch box S. Reda EN1600 SP’08
- 12. Example S. Reda EN1600 SP’08
- 13. Programming the FPGA Configuration data in Configuration data out = I/O pin/pad = SRAM cell S. Reda EN1600 SP’08
- 14. FPGAs versus custom chips • Offer flexibility → FPGAs can be reprogrammed to perform different logic functions • No layouts, no masks, no custom fabrication → huge savings for low, med-volume production • Larger overhead in area, performance, and power S. Reda EN1600 SP’08