16f628a

PIC16F627A/628A/648A
Data Sheet
Flash-Based 8-Bit CMOS
Microcontrollers with nanoWatt Technology

 2004 Microchip Technology Inc. Preliminary DS40044B

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks
applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE, PowerSmart and rfPIC are registered
No representation or warranty is given and no liability is
trademarks of Microchip Technology Incorporated in the
assumed by Microchip Technology Incorporated with respect
U.S.A. and other countries.
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
use or otherwise. Use of Microchip’s products as critical SEEVAL, SmartShunt and The Embedded Control Solutions
components in life support systems is not authorized except Company are registered trademarks of Microchip Technology
with express written approval by Microchip. No licenses are Incorporated in the U.S.A.
conveyed, implicitly or otherwise, under any intellectual Application Maestro, dsPICDEM, dsPICDEM.net,
property rights. dsPICworks, ECAN, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode,
SmartSensor, SmartTel and Total Endurance are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in October
2003. The Company’s quality system processes and procedures are for
its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

DS40044B-page ii Preliminary  2004 Microchip Technology Inc.

PIC16F627A/628A/648A
18-pin Flash-Based 8-Bit CMOS Microcontrollers
with nanoWatt Technology
High Performance RISC CPU: Low Power Features:
• Operating speeds from DC - 20 MHz • Standby Current:
• Interrupt capability - 100 nA @ 2.0V, typical
• 8-level deep hardware stack • Operating Current:
• Direct, Indirect and Relative Addressing modes - 12 µA @ 32 kHz, 2.0V, typical
• 35 single word instructions - 120 µA @ 1 MHz, 2.0V, typical
- All instructions single cycle except branches • Watchdog Timer Current
- 1 µA @ 2.0V, typical
Special Microcontroller Features: • Timer1 oscillator current:
• Internal and external oscillator options - 1.2 µA @ 32 kHz, 2.0V, typical
- Precision Internal 4 MHz oscillator factory • Dual Speed Internal Oscillator:
calibrated to ±1% - Run-time selectable between 4 MHz and
- Low Power Internal 37 kHz oscillator 37 kHz
- External Oscillator support for crystals and - 4 µs wake-up from Sleep, 3.0V, typical
resonators.
• Power saving Sleep mode Peripheral Features:
• Programmable weak pull-ups on PORTB • 16 I/O pins with individual direction control
• Multiplexed Master Clear/Input-pin • High current sink/source for direct LED drive
• Watchdog Timer with independent oscillator for • Analog comparator module with:
reliable operation - Two analog comparators
• Low voltage programming - Programmable on-chip voltage reference
• In-Circuit Serial Programming™ (via two pins) (VREF) module
• Programmable code protection - Selectable internal or external reference
• Brown-out Reset - Comparator outputs are externally accessible
• Power-on Reset • Timer0: 8-bit timer/counter with 8-bit
• Power-up Timer and Oscillator Start-up Timer programmable prescaler
• Wide operating voltage range. (2.0 - 5.5V) • Timer1: 16-bit timer/counter with external crystal/
• Industrial and extended temperature range clock capability
• High Endurance Flash/EEPROM Cell • Timer2: 8-bit timer/counter with 8-bit period
- 100,000 write Flash endurance register, prescaler and postscaler
- 1,000,000 write EEPROM endurance • Capture, Compare, PWM module
- 100 year data retention - 16-bit Capture/Compare
- 10-bit PWM
• Addressable Universal Synchronous/Asynchronous
Receiver/Transmitter USART/SCI
Program
Data Memory
Memory CCP Timers
Device I/O USART Comparators
Flash SRAM EEPROM (PWM) 8/16-bit
(words) (bytes) (bytes)
PIC16F627A 1024 224 128 16 1 Y 2 2/1
PIC16F628A 2048 224 128 16 1 Y 2 2/1
PIC16F648A 4096 256 256 16 1 Y 2 2/1

 2004 Microchip Technology Inc. Preliminary DS40044B-page 1

PIC16F627A/628A/648A
Pin Diagrams
PDIP, SOIC

RA2/AN2/VREF 1 18 RA1/AN1

RA3/AN3/CMP1 2 17 RA0/AN0

PIC16F627A/628A/648A
PIC16F627A/628A/648A
RA4/TOCKI/CMP2 3 16 RA7/OSC1/CLKIN

RA5/MCLR/VPP 4 15 RA6/OSC2/CLKOUT

VSS 5 14 VDD
RB0/INT 6 13 RB7/T1OSI/PGD

RB1/RX/DT 7 12 RB6/T1OSO/T1CKI/PGC

RB2/TX/CK 8 11 RB5

RB3/CCP1 9 10 RB4/PGM

SSOP 28-Pin QFN
RB6/T1OSO/T1CKI/PGC
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN

RB7/T1OSI/PGD

RA4/T0CKI/CMP2
RA3/AN3/CMP1
RA2/AN2/VREF
RB4/PGM
RA1/AN1
RA0/AN0

RA1/AN1
RA0/AN0
RB5
VDD
VDD

25 NC

22 NC
20
19
18
17
16
15
14
13
12
11

28
27
26

24
23

RA5/MCLR/VPP 1 21 RA7/OSC1/CLKIN
PIC16F627A/628A/648A NC 2 20 RA6/OSC2/CLKOUT
VSS 3 19 VDD
NC 4 PIC16F627A/628A 18 NC
10
1
2
3
4
5
6
7
8
9

VSS PIC16F648A 17
5 VDD
NC 6 16 RB7/T1OSI/PGD
RB0/INT 7 15 RB6/T1OSO/T1CKI/PGC
10

12
13
NC 14
NC 11
8
9
RB0/INT
RB1/RX/DT
RA3/AN3/CMP1

RB3/CCP1
RA2/AN2/VREF

RA4/TOCKI/CMP2
RA5/MCLR/VPP
VSS
VSS

RB2/TX/CK

RB3/CCP1

RB5
RB2/TX/CK
RB1/RX/DT

RB4/PGM

DS40044B-page 2 Preliminary  2004 Microchip Technology Inc.

PIC16F627A/628A/648A
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16F627A/628A/648A Device Varieties ................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 31
6.0 Timer0 Module ........................................................................................................................................................................... 45
7.0 Timer1 Module ........................................................................................................................................................................... 48
8.0 Timer2 Module ........................................................................................................................................................................... 52
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 55
10.0 Comparator Module.................................................................................................................................................................... 61
11.0 Voltage Reference Module......................................................................................................................................................... 67
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 69
13.0 Data EEPROM Memory ............................................................................................................................................................. 89
14.0 Special Features of the CPU...................................................................................................................................................... 93
15.0 Instruction Set Summary .......................................................................................................................................................... 111
16.0 Development Support............................................................................................................................................................... 125
17.0 Electrical Specifications............................................................................................................................................................ 131
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 147
19.0 Packaging Information.............................................................................................................................................................. 149

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PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
1.0 GENERAL DESCRIPTION HS is for High-Speed crystals. The EC mode is for an
external clock source.
The PIC16F627A/628A/648A are 18-Pin Flash-based
The Sleep (Power-down) mode offers power savings.
members of the versatile PIC16CXX family of low cost,
Users can wake-up the chip from Sleep through
high performance, CMOS, fully-static, 8-bit
several external interrupts, internal interrupts and
microcontrollers.
Resets.
All PICmicro® microcontrollers employ an advanced
A highly reliable Watchdog Timer with its own on-chip
RISC architecture. The PIC16F627A/628A/648A have
RC oscillator provides protection against software lock-
enhanced core features, eight-level deep stack, and
up.
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard Table 1-1 shows the features of the PIC16F627A/
architecture allow a 14-bit wide instruction word with 628A/648A mid-range microcontroller families.
the separate 8-bit wide data. The two-stage instruction A simplified block diagram of the PIC16F627A/628A/
pipeline allows all instructions to execute in a single- 648A is shown in Figure 3-1.
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction The PIC16F627A/628A/648A series fits in applications
set) are available, complemented by a large register ranging from battery chargers to low power remote
set. sensors. The Flash technology makes customizing
application programs (detection levels, pulse genera-
PIC16F627A/628A/648A microcontrollers typically tion, timers, etc.) extremely fast and convenient. The
achieve a 2:1 code compression and a 4:1 speed small footprint packages makes this microcontroller
improvement over other 8-bit microcontrollers in their series ideal for all applications with space limitations.
class. Low cost, low power, high performance, ease of use
PIC16F627A/628A/648A devices have integrated and I/O flexibility make the PIC16F627A/628A/648A
features to reduce external components, thus reducing very versatile.
system cost, enhancing system reliability and reducing
power consumption. 1.1 Development Support
The PIC16F627A/628A/648A has 8 oscillator configu- The PIC16F627A/628A/648A family is supported by a
rations. The single-pin RC oscillator provides a low cost full-featured macro assembler, a software simulator, an
solution. The LP oscillator minimizes power consump- in-circuit emulator, a low cost in-circuit debugger, a low
tion, XT is a standard crystal, and INTOSC is a self- cost development programmer and a full-featured
contained precision two-speed internal oscillator. The programmer. A Third Party “C” compiler support tool is
also available.
TABLE 1-1: PIC16F627A/628A/648A FAMILY OF DEVICES
PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A
Clock Maximum Frequency 20 20 20 4 4 4
of Operation (MHz)
Flash Program Mem- 1024 2048 4096 1024 2048 4096
ory (words)
Memory RAM Data Memory 224 224 256 224 224 256
(bytes)
EEPROM Data Mem- 128 128 256 128 128 256
ory (bytes)
Timer module(s) TMR0, TMR1, TMR0, TMR1, TMR0, TMR1, TMR0, TMR1, TMR0, TMR1, TMR0, TMR1,
TMR2 TMR2 TMR2 TMR2 TMR2 TMR2
Comparator(s) 2 2 2 2 2 2
Peripherals Capture/Compare/ 1 1 1 1 1 1
PWM modules
Serial Communications USART USART USART USART USART USART
Internal Voltage Yes Yes Yes Yes Yes Yes
Reference
Interrupt Sources 10 10 10 10 10 10
I/O Pins 16 16 16 16 16 16
Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5 2.0-5.5
Brown-out Reset Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP,
SOIC, 20-pin SOIC, 20-pin SOIC, 20-pin SOIC, 20-pin SOIC, 20-pin SOIC, 20-pin
SSOP, SSOP, SSOP, SSOP, SSOP, SSOP,
28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.
All PIC16F627A/628A/648A Family devices use serial programming with clock pin RB6 and data pin RB7.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
2.0 PIC16F627A/628A/648A
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F627A/628A/648A
Product Identification System, at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.

2.1 Flash Devices
Flash devices can be erased and re-programmed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically erasable Flash is
that it can be erased and reprogrammed in-circuit, or by
device programmers, such as Microchip's
PICSTART® Plus, or PRO MATE® II programmers.

2.2 Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard Flash devices but
with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more
details.

2.3 Serialized Quick-Turnaround-
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
3.0 ARCHITECTURAL OVERVIEW The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
The high performance of the PIC16F627A/628A/648A otherwise mentioned, arithmetic operations are two's
family can be attributed to a number of architectural complement in nature. In two-operand instructions,
features commonly found in RISC microprocessors. To typically one operand is the working register
begin with, the PIC16F627A/628A/648A uses a (W register). The other operand is a file register or an
Harvard architecture, in which program and data are immediate constant. In single operand instructions, the
accessed from separate memories using separate operand is either the W register or a file register.
busses. This improves bandwidth over traditional Von
The W register is an 8-bit working register used for ALU
Neumann architecture where program and data are
operations. It is not an addressable register.
fetched from the same memory. Separating program
and data memory further allows instructions to be sized Depending on the instruction executed, the ALU may
differently than 8-bit wide data word. Instruction affect the values of the Carry (C), Digit Carry (DC), and
opcodes are 14-bits wide making it possible to have all Zero (Z) bits in the Status Register. The C and DC bits
single word instructions. A 14-bit wide program mem- operate as a Borrow and Digit Borrow out bit,
ory access bus fetches a 14-bit instruction in a single respectively, bit in subtraction. See the SUBLW and
cycle. A two-stage pipeline overlaps fetch and execu- SUBWF instructions for examples.
tion of instructions. Consequently, all instructions (35) A simplified block diagram is shown in Figure 3-1, and
execute in a single-cycle (200 ns @ 20 MHz) except for a description of the device pins in Table 3-2.
program branches.
Two types of data memory are provided on the
Table 3-1 lists device memory sizes (Flash, Data and PIC16F627A/628A/648A devices. Nonvolatile
EEPROM). EEPROM data memory is provided for long term stor-
age of data such as calibration values, look up table
TABLE 3-1: DEVICE MEMORY LIST data, and any other data which may require periodic
updating in the field. These data are not lost when
Memory power is removed. The other data memory provided is
Device Flash RAM EEPROM
regular RAM data memory. Regular RAM data memory
Program Data Data is provided for temporary storage of data during normal
operation. Data are lost when power is removed.
PIC16F627A 1024 x 14 224 x 8 128 x 8
PIC16F628A 2048 x 14 224 x 8 128 x 8
PIC16F648A 4096 x 14 256 x 8 256 x 8
PIC16LF627A 1024 x 14 224 x 8 128 x 8
PIC16LF628A 2048 x 14 224 x 8 128 x 8
PIC16LF648A 4096 x 14 256 x 8 256 x 8

The PIC16F627A/628A/648A can directly or indirectly
address its register files or data memory. All Special
Function Registers (SFR), including the program
counter, are mapped in the data memory. The
PIC16F627A/628A/648A have an orthogonal (symmet-
rical) instruction set that makes it possible to carry out
any operation, on any register, using any Addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16F627A/628A/648A simple yet efficient. In
addition, the learning curve is reduced significantly.
The PIC16F627A/628A/648A devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.


PIC16F627A/628A/648A
FIGURE 3-1: BLOCK DIAGRAM

13 Data Bus 8
Flash Program Counter

Program
Memory RAM
8-Level Stack
File
(13-bit) Registers

Program 14
Bus RAM Addr (1) 9 PORTA

Addr MUX RA0/AN0
Instruction reg
RA1/AN1
Direct Addr 7 Indirect RA2/AN2/VREF
8 Addr
RA3/AN3/CMP1
FSR reg RA4/T0CK1/CMP2
RA5/MCLR/VPP
Status Reg RA6/OSC2/CLKOUT
8 RA7/OSC1/CLKIN

3 MUX PORTB
Power-up
Timer RB0/INT
RB1/RX/DT
Instruction Oscillator
Decode & Start-up Timer RB2/TX/CK
ALU RB3/CCP1
Control
Power-on RB4/PGM
Reset 8
RB5
Timing Watchdog RB6/T1OSO/T1CKI/PGC
Generation Timer W reg
RB7/T1OSI/PGD
OSC1/CLKIN Brown-out
OSC2/CLKOUT Detect
Low-Voltage
Programming

MCLR VDD, VSS

Comparator Timer0 Timer1 Timer2

VREF CCP1 USART Data EEPROM

Note: Higher order bits are from the Status Register.


PIC16F627A/628A/648A

TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/AN0 RA0 ST CMOS Bidirectional I/O port
AN0 AN — Analog comparator input
RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port
T0CKI ST — Timer0 clock input
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port

MCLR ST — Master clear. When configured as MCLR, this
pin is an active low Reset to the device.
Voltage on MCLR/VPP must not exceed VDD
during normal device operation.
VPP — — Programming voltage input.
RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port
OSC2 — XTAL Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT — CMOS In RC/INTOSC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1
RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port
OSC1 XTAL — Oscillator crystal input
CLKIN ST — External clock source input. RC biasing pin.
RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
INT ST — External interrupt.
RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software
RX ST — USART receive pin
DT ST CMOS Synchronous data I/O.
RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port. Can be software
TX — CMOS USART transmit pin
CK ST CMOS Synchronous clock I/O.
RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software
CCP1 ST CMOS Capture/Compare/PWM I/O
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog


PIC16F627A/628A/648A
TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
PGM ST — Low voltage programming input pin. When
low voltage programming is enabled, the
interrupt-on-pin change and weak pull-up
resistor are disabled.
RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
weak pull-up.
RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
weak pull-up.
T1OSO — XTAL Timer1 oscillator output.
T1CKI ST — Timer1 clock input.
PGC ST — ICSP Programming Clock.
RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
weak pull-up.
T1OSI XTAL — Timer1 oscillator input.
PGD ST CMOS ICSP Data I/O
VSS VSS Power — Ground reference for logic and I/O pins
VDD VDD Power — Positive supply for logic and I/O pins


PIC16F627A/628A/648A
3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining
Cycle An instruction cycle consists of four Q cycles (Q1, Q2,
The clock input (OSC1/CLKIN/RA7 pin) is internally Q3 and Q4). The instruction fetch and execute are
divided by four to generate four non-overlapping pipelined such that fetch takes one instruction cycle
quadrature clocks namely Q1, Q2, Q3 and Q4. Inter- while decode and execute takes another instruction
nally, the program counter (PC) is incremented every cycle. However, due to the pipelining, each instruction
Q1, the instruction is fetched from the program memory effectively executes in one cycle. If an instruction
and latched into the instruction register in Q4. The causes the program counter to change (e.g., GOTO)
instruction is decoded and executed during the then two cycles are required to complete the instruction
following Q1 through Q4. The clocks and instruction (Example 3-1).
execution flow is shown in Figure 3-2. A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
CLKOUT
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, 3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
4.0 MEMORY ORGANIZATION 4.2 Data Memory Organization
The data memory (Figure 4-2 and Figure 4-3) is
4.1 Program Memory Organization
partitioned into four banks, which contain the General
The PIC16F627A/628A/648A has a 13-bit program Purpose Registers (GPR’s) and the Special Function
counter capable of addressing an 8K x 14 program Registers (SFR). The SFR’s are located in the first 32
memory space. Only the first 1K x 14 (0000h - 03FFh) locations of each Bank. There are General Purpose
for the PIC16F627A, 2K x 14 (0000h - 07FFh) for the Registers implemented as static RAM in each Bank.
PIC16F628A and 4K x 14 (0000h - 0FFFh) for the Table 4-1 lists the General Purpose Register available
PIC16F648A are physically implemented. Accessing a in each of the four banks.
location above these boundaries will cause a wrap-
around within the first 1K x 14 space (PIC16F627A), 2K TABLE 4-1: GENERAL PURPOSE STATIC
x 14 space (PIC16F628A) or 4K x 14 space RAM REGISTERS
(PIC16F648A). The Reset vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-1). PIC16F627A/628A PIC16F648A
Bank0 20-7Fh 20-7Fh
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK Bank1 A0h-FF A0h-FF
Bank2 120h-14Fh, 170h-17Fh 120h-17Fh
PC<12:0>
Bank3 1F0h-1FFh 1F0h-1FFh
CALL, RETURN 13
RETFIE, RETLW
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
Stack Level 1 implemented as common RAM and mapped back to
Stack Level 2 addresses 70h-7Fh.
Table 4-2 lists how to access the four banks of registers
via the Status Register bits RP1 and RP0.
Stack Level 8
TABLE 4-2: ACCESS TO BANKS OF
Reset Vector 000h REGISTERS

RP1 RP0

Interrupt Vector 0004 Bank0 0 0

On-chip Program 0005 Bank1 0 1
Memory Bank2 1 0
PIC16F627A, Bank3 1 1
PIC16F628A and
PIC16F648A 4.2.1 GENERAL PURPOSE REGISTER
03FFh FILE
On-chip Program The register file is organized as 224 x 8 in the
Memory PIC16F627A/628A and 256 x 8 in the PIC16F648A.
PIC16F628A and Each is accessed either directly or indirectly through
PIC16F648A the File Select Register (FSR), See Section 4.4 "Indi-
07FFh rect Addressing, INDF and FSR Registers".

On-chip Program
Memory
PIC16F648A only

0FFFh

1FFFh


PIC16F627A/628A/648A
FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File
Address

Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h
TMR2 11h 91h
T2CON 12h PR2 92h
13h 93h
14h 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah EEDATA 9Ah
1Bh EEADR 9Bh
1Ch EECON1 9Ch
1Dh EECON2(1) 9Dh
1Eh 9Eh
CMCON 1Fh VRCON 9Fh 11Fh
20h General 120h
A0h Purpose
General General Register
Purpose Purpose 48 Bytes 14Fh
Register Register
150h
80 Bytes
80 Bytes

6Fh EFh 16Fh 1EFh
70h F0h 170h 1F0h
accesses accesses accesses
16 Bytes
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.


PIC16F627A/628A/648A
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A
File
Address

Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h
TMR2 11h 91h
T2CON 12h PR2 92h
13h 93h
14h 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah EEDATA 9Ah
1Bh EEADR 9Bh
1Ch EECON1 9Ch
1Dh EECON2(1) 9Dh
1Eh 9Eh
CMCON 1Fh VRCON 9Fh 11Fh
20h 120h
A0h
General General General
Purpose Purpose Purpose
Register Register Register
80 Bytes 80 Bytes
80 Bytes

6Fh EFh 16Fh 1EFh
70h F0h 170h 1F0h
accesses accesses accesses
16 Bytes
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh

Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.


PIC16F627A/628A/648A
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.

TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0
Value on Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR on
Reset(1) Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
01h TMR0 Timer0 module’s Register xxxx xxxx 45
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 22
04h FSR Indirect data memory address pointer xxxx xxxx 28
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 31
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36
07h — Unimplemented — —
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 28
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 26
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 48
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 48
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 48
11h TMR2 TMR2 module’s register 0000 0000 52
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52
15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx 55
16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx 55
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 55
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 69
19h TXREG USART Transmit data register 0000 0000 76
1Ah RCREG USART Receive data register 0000 0000 79
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Eh — Unimplemented — —
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.


PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Value on Details
Reset(1) Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx 28
register)
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 31
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 25
8Eh PCON — — — — OSCF — POR BOR ---- 1-0x 27
8Fh — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 52
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 71
99h SPBRG Baud Rate Generator Register 0000 0000 71
9Ah EEDATA EEPROM data register xxxx xxxx 89
9Bh EEADR EEPROM address register xxxx xxxx 90
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 90
9Dh EECON2 EEPROM control register 2 (not a physical register) ---- ---- 90
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 67
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented


PIC16F627A/628A/648A
Value on Details
Reset(1) Page
Bank 2
101h TMR0 Timer0 module’s Register xxxx xxxx 45
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36
11Ah — Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented.


PIC16F627A/628A/648A
Value on Details
Reset(1) Page
Bank 3
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
19Ah — Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented


PIC16F627A/628A/648A
4.2.2.1 Status Register For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the Status Register
The Status Register, shown in Register 4-1, contains
as “000uu1uu” (where u = unchanged).
the arithmetic status of the ALU; the Reset status and
the bank select bits for data memory (SRAM). It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The Status Register can be the destination for any
StatusRegister because these instructions do not affect
instruction, like any other register. If the Status Register
any Status bit. For other instructions, not affecting any
is the destination for an instruction that affects the Z,
Status bits, see the “Instruction Set Summary”.
DC or C bits, then the write to these three bits is dis-
abled. These bits are set or cleared according to the Note 1: The C and DC bits operate as a Borrow
device logic. Furthermore, the TO and PD bits are non- and Digit Borrow out bit, respectively, in
writable. Therefore, the result of an instruction with the subtraction. See the SUBLW and SUBWF
Status Register as destination may be different than instructions for examples.
intended.

REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4 TO: Time out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


PIC16F627A/628A/648A
4.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for
The OPTION register is a readable and writable
TMR0, assign the prescaler to the WDT
register, which contains various control bits to configure
(PSA = 1). See Section 6.3.1 "Switching
the TMR0/WDT prescaler, the external RB0/INT
Prescaler Assignment".
interrupt, TMR0 and the weak pull-ups on PORTB.

REGISTER 4-2: OPTION REGISTER (ADDRESS: 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate

000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

Legend:


PIC16F627A/628A/648A
4.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt
The INTCON register is a readable and writable
condition occurs regardless of the state of
register, which contains the various enable and flag bits
its corresponding enable bit or the global
for all interrupt sources except the comparator module.
enable bit, GIE (INTCON<7>).
See Section 4.2.2.4 "PIE1 Register" and
Section 4.2.2.5 "PIR1 Register" for a description of
the comparator enable and flag bits.

REGISTER 4-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

Legend:


PIC16F627A/628A/648A
4.2.2.4 PIE1 Register
This register contains interrupt enable bits.

REGISTER 4-4: PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Legend:


PIC16F627A/628A/648A
4.2.2.5 PIR1 Register
Note: Interrupt flag bits get set when an interrupt
This register contains interrupt flag bits. condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.

REGISTER 4-5: PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Legend:


PIC16F627A/628A/648A
4.2.2.6 PCON Register
The PCON register contains flag bits to differentiate Note: BOR is unknown on Power-on Reset. It
between a Power-on Reset, an external MCLR Reset, must then be set by the user and checked
WDT Reset or a Brown-out Reset. on subsequent Resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR Status bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BOREN bit in the
Configuration word).

REGISTER 4-6: PCON REGISTER (ADDRESS: 8Eh)
U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-0 R/W-x
— — — — OSCF — POR BOR
bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’
bit 3 OSCF: INTOSC oscillator frequency
1 = 4 MHz typical
0 = 37 kHz typical
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:


PIC16F627A/628A/648A
4.3 PCL and PCLATH The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
The program counter (PC) is 13-bits wide. The low byte push overwrites the value that was stored from the first
comes from the PCL register, which is a readable and push. The tenth push overwrites the second push (and
writable register. The high byte (PC<12:8>) is not so on).
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 4-4 shows the Note 1: There are no Status bits to indicate stack
two situations for loading the PC. The upper example overflow or stack underflow conditions.
in Figure 4-4 shows how the PC is loaded on a write to 2: There are no instructions/mnemonics
PCL (PCLATH<4:0> → PCH). The lower example in called PUSH or POP. These are actions
Figure 4-4 shows how the PC is loaded during a CALL that occur from the execution of the
or GOTO instruction (PCLATH<4:3> → PCH). CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
FIGURE 4-4: LOADING OF PC IN interrupt address.
DIFFERENT SITUATIONS
4.4 Indirect Addressing, INDF and
PCH PCL FSR Registers
12 8 7 0 Instruction with The INDF register is not a physical register. Addressing
PC PCL as the INDF register will cause indirect addressing.
Destination
PCLATH<4:0> 8
5 ALU result
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the file select
PCLATH
register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
PCH PCL
results in a no-operation (although Status bits may be
12 11 10 8 7 0
affected). An effective 9-bit address is obtained by
PC GOTO, CALL
concatenating the 8-bit FSR register and the IRP bit
2
PCLATH<4:3> 11 (STATUS<7>), as shown in Figure 4-5.
Opcode <10:0>
A simple program to clear RAM location 20h-2Fh using
PCLATH indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: Indirect Addressing
4.3.1 COMPUTED GOTO MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
A computed GOTO is accomplished by adding an offset NEXT CLRF INDF ;clear INDF register
to the program counter (ADDWF PCL). When doing a INCF FSR ;inc pointer
table read using a computed GOTO method, care BTFSS FSR,4 ;all done?
should be exercised if the table location crosses a PCL GOTO NEXT ;no clear next
;yes continue
memory boundary (each 256-byte block). Refer to the
application note “Implementing a Table Read” (AN556).

4.3.2 STACK
The PIC16F627A/628A/648A family has an 8-level
deep x 13-bit wide hardware stack (Figure 4-1). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.


PIC16F627A/628A/648A
FIGURE 4-5: DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A

Status Status
Register Direct Addressing Indirect Addressing
Register
RP1 RP0 6 from opcode 0 IRP 7 FSR Register 0

bank select location select bank select location select
00 01 10 11
00h 180h

RAM
File
Registers

7Fh 1FFh

Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
5.0 I/O PORTS The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
The PIC16F627A/628A/648A have two ports, PORTA very high-impedance output. The user must configure
and PORTB. Some pins for these I/O ports are TRISA<2> bit as an input and use high-impedance
multiplexed with alternate functions for the peripheral loads.
features on the device. In general, when a peripheral is
In one of the Comparator modes defined by the
enabled, that pin may not be used as a general
CMCON register, pins RA3 and RA4 become outputs
purpose I/O pin.
of the comparators. The TRISA<4:3> bits must be
5.1 IPORTA and TRISA Registers cleared to enable outputs to use this function.

PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger EXAMPLE 5-1: Initializing PORTA
input and an open drain output. Port RA4 is multiplexed CLRF PORTA ;Initialize PORTA by
with the T0CKI clock input. RA5(1) is a Schmitt Trigger ;setting
input only and has no output drivers. All other RA port ;output data latches
pins have Schmitt Trigger input levels and full CMOS MOVLW 0x07 ;Turn comparators off and
output drivers. All pins have data direction bits (TRIS MOVWF CMCON ;enable pins for I/O
registers) which can configure these pins as input or ;functions
output. BCF STATUS, RP1
BSF STATUS, RP0 ;Select Bank1
A ‘1’ in the TRISA register puts the corresponding MOVLW 0x1F ;Value used to initialize
output driver in a High-impedance mode. A '0' in the ;data direction
TRISA register puts the contents of the output latch on MOVWF TRISA ;Set RA<4:0> as inputs
the selected pin(s). ;TRISA<5> always
;read as ‘1’.
Reading the PORTA register reads the status of the ;TRISA<7:6>
pins whereas writing to it will write to the port latch. All ;depend on oscillator
write operations are read-modify-write operations. So a ;mode
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch. FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these Data
Bus
pins are selected by control bits in the CMCON D Q
VDD
(comparator control register) register and the VRCON WR
(voltage reference control register) register. When PORTA
CK Q
selected as a comparator input, these pins will read
Data Latch
as ‘0’s.
D Q
I/O Pin
WR
Note 1: RA5 shares function with VPP. When VPP TRISA
CK Q
voltage levels are applied to RA5, the Analog
TRIS Latch VSS
device will enter Programming mode. Input Mode
(CMCON Reg.)
2: On Reset, the TRISA register is set to all
inputs. The digital inputs (RA<3:0>) are
disabled and the comparator inputs are RD Schmitt Trigger
TRISA Input Buffer
forced to ground to reduce current
consumption.
3: TRISA<6:7> is overridden by oscillator Q D
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
EN
TRISA<6:7> bits are ignored.
TRISA controls the direction of the RA pins, even when RD PORTA
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs. To Comparator


PIC16F627A/628A/648A
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/VREF PIN
Data
Bus
D Q
VDD
WR
PORTA
CK Q
Data Latch
D Q
RA2 Pin
WR
TRISA
CK Q Analog
Input Mode VSS
TRIS Latch (CMCON Reg.)

RD
TRISA Schmitt Trigger
Input Buffer

Q D

EN

RD PORTA

To Comparator

VROE

VREF

FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN
Data Comparator Mode = 110 (CMCON Reg.)
Bus VDD
D Q
Comparator Output
WR 1
PORTA
CK Q
Data Latch 0

D Q
RA3 Pin
WR
TRISA Analog
CK Q
Input Mode VSS
TRIS Latch (CMCON Reg.)

RD
TRISA Schmitt Trigger
Input Buffer

Q D

EN

RD PORTA

To Comparator


PIC16F627A/628A/648A
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI PIN
Data Comparator Mode = 110 (CMCON Reg.)
Bus
D Q
Comparator Output
WR
1
PORTA
CK Q
Data Latch 0

D Q
RA4 Pin
WR N
TRISA
CK Q
TRIS Latch Vss Vss

Schmitt Trigger
Input Buffer
RD TRISA

Q D

EN

RD PORTA

TMR0 Clock Input

FIGURE 5-5: BLOCK DIAGRAM OF THE FIGURE 5-6: BLOCK DIAGRAM OF
RA5/MCLR/VPP PIN RA6/OSC2/CLKOUT PIN

From OSC1 OSC
Circuit VDD

CLKOUT(FOSC/4)
1
MCLRE (Configuration Bit)
MCLR
circuit D Q 0
WR
MCLR Filter PORTA
CK Q
Program Schmitt Trigger (FOSC = VSS
Data Latch
mode Input Buffer 101, 111) (2)
HV Detect
RA5/MCLR/VPP
D Q
WR
Data TRISA
CK Q
Bus
VSS TRIS Latch
RD
TRISA Schmitt
Trigger
Input Buffer
FOSC =
RD 011, 100, 110 (1)
TRISA VSS
Q D
Q D
EN

EN RD PORTA
RD
PORTA Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with RA6 =
CLKOUT.


PIC16F627A/628A/648A
FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN

To Clock Circuits
VDD

Data Bus
D Q

RA7/OSC1/CLKIN Pin
WR PORTA
CK Q
Data Latch
D VSS
Q

WR TRISA
CK Q

TRIS Latch

RD TRISA

FOSC = 100, 101(1)

Q D

Schmitt Trigger
Input Buffer
EN

RD PORTA

Note 1: INTOSC with CLKOUT, and INTOSC with I/O.


PIC16F627A/628A/648A
TABLE 5-1: PORTA FUNCTIONS
Input Output
Name Function Description
Type Type
RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port. Output is open drain type.
T0CKI ST — External clock input for TMR0 or comparator output
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port
MCLR ST — Master clear. When configured as MCLR, this pin is an
active low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation.
VPP HV — Programming voltage input.
RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port
OSC2 — XTAL Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
CLKOUT — CMOS In RC or INTOSC mode. OSC2 pin can output CLKOUT,
which has 1/4 the frequency of OSC1
RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port
OSC1 XTAL — Oscillator crystal input. Connects to crystal resonator in
Crystal Oscillator mode.
CLKIN ST — External clock source input. RC biasing pin.


PIC16F627A/628A/648A
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1)
Value on
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other
POR
Resets
05h PORTA RA7 RA6 RA5(2) RA4 RA3 RA2 RA1 RA0 xxxx 0000 qqqu 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Shaded bits are not used by PORTA.
2: MCLRE Configuration Bit sets RA5 functionality.

5.2 PORTB and TRISB Registers This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
PORTB is an 8-bit wide bidirectional port. The easy interface to a key pad and make it possible for
corresponding data direction register is TRISB. A ‘1’ in wake-up on key-depression. (See AN552)
the TRISB register puts the corresponding output driver
in a High-impedance mode. A '0' in the TRISB register Note: If a change on the I/O pin should occur
puts the contents of the output latch on the selected when a read operation is being executed
pin(s). (start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output. The interrupt-on-change feature is recommended for
The standard port functions and the alternate port wake-up on key depression operation and operations
functions are shown in Table 5-3. Alternate port where PORTB is only used for the interrupt-on-change
functions may override TRIS setting when enabled. feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.


PIC16F627A/628A/648A
FIGURE 5-8: BLOCK DIAGRAM OF FIGURE 5-9: BLOCK DIAGRAM OF
RB0/INT PIN RB1/RX/DT PIN
VDD VDD
RBPU RBPU Weak
P Weak Pull-up
SPEN P Pull-up
VDD
VDD

USART Data Output
1

Data Bus Data Bus D 0
Q RB1/
D Q
RX/DT
RB0/INT WR PORTB
WR PORTB CK Q
CK Q
Data Latch VSS
Data Latch VSS
D Q

D Q WR TRISB
CK Q
WR TRISB
CK Q TRIS Latch
Peripheral OE(1)
TRIS Latch
TTL
RD TRISB Input
TTL Buffer
RD TRISB
Input Q D
Buffer

Q D EN

RD PORTB
EN
EN

USART Receive Input
RD PORTB Schmitt
Trigger
INT
Note 1: Peripheral OE (output enable) is only active if
Schmitt peripheral select is active.
Trigger


PIC16F627A/628A/648A
FIGURE 5-10: BLOCK DIAGRAM OF FIGURE 5-11: BLOCK DIAGRAM OF
RB2/TX/CK PIN RB3/CCP1 PIN
VDD VDD
RBPU Weak RBPU Weak
SPEN P Pull-up CCP1CON P Pull-up
VDD VDD

USART TX/CK Output CCP output
1 0

Data Bus D 0 RB2/ Data Bus D 1 RB3/
Q Q
TX/CK CCP1

WR PORTB WR PORTB
CK Q CK Q

Data Latch VSS Data Latch VSS

D Q D Q

WR TRISB WR TRISB
CK Q CK Q

TRIS Latch TRIS Latch
Peripheral OE(1) Peripheral OE(2)

TTL TTL
RD TRISB Input RD TRISB Input
Buffer Buffer

Q D Q D

EN EN

RD PORTB RD PORTB

USART Slave Clock In CCP In
Schmitt Schmitt
Trigger Trigger

Note 1: Peripheral OE (output enable) is only active if Note 1: Peripheral OE (output enable) is only active if
peripheral select is active. peripheral select is active.


PIC16F627A/628A/648A
FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P weak pull-up

Data Bus
D Q VDD

WR PORTB
CK Q

Data Latch
RB4/PGM
D Q

WR TRISB
CK Q
VSS
TRIS Latch

RD TRISB

LVP (Configuration Bit)

RD PORTB

PGM input

TTL
Schmitt
input
Trigger
buffer

Q D

EN Q1

Set RBIF

From other Q D
RB<7:4> pins
Q3
EN

Note: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.


PIC16F627A/628A/648A
FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
weak VDD
P pull-up

Data Bus
D Q
RB5 pin
WR PORTB
CK Q

Data Latch
VSS

D Q

WR TRISB
CK Q

TRIS Latch
TTL
input
buffer
RD TRISB

Q D
RD PORTB
EN Q1
Set RBIF

From other Q D
RB<7:4> pins
Q3
EN


PIC16F627A/628A/648A
FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN

VDD
RBPU
P weak pull-up

Data Bus
D Q
VDD
WR PORTB
CK Q

Data Latch
RB6/
D Q T1OSO/
T1CKI
WR TRISB pin
CK Q
VSS
TRIS Latch

RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB

TMR1 Clock

Schmitt
From RB7 Trigger

Serial programming clock TMR1 oscillator

Q D

EN Q1

Set RBIF

From other Q D
RB<7:4> pins
Q3
EN


PIC16F627A/628A/648A
FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD
RBPU
P weak pull-up

To RB6 TMR1 oscillator

VDD

Data Bus
D Q

WR PORTB RB7/T1OSI
CK Q
pin
Data Latch

D Q VSS

WR TRISB
CK Q

TRIS Latch

RD TRISB

T10SCEN

TTL
RD PORTB input
buffer

Serial programming input

Schmitt
Trigger
Q D

EN Q1

Set RBIF

From other Q D
RB<7:4> pins
Q3
EN


PIC16F627A/628A/648A
TABLE 5-3: PORTB FUNCTIONS
Output
Name Function Input Type Description
Type
RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
INT ST — External interrupt.
RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for
RX ST — USART Receive Pin
DT ST CMOS Synchronous data I/O
RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port
TX — CMOS USART Transmit Pin
CK ST CMOS Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software programmed for
CCP1 ST CMOS Capture/Compare/PWM/I/O
RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM ST — Low voltage programming input pin. When low voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
RB6/T1OSO/T1CKI/ RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
PGC software programmed for internal weak pull-up.
T1OSO — XTAL Timer1 Oscillator Output
T1CKI ST — Timer1 Clock Input
PGC ST — ICSP Programming Clock
RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
T1OSI XTAL — Timer1 Oscillator Input
PGD ST CMOS ICSP Data I/O

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)
Value on
Value on
POR
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4(2) RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTB.
2: LVP Configuration Bit sets RB4 functionality.


PIC16F627A/628A/648A
5.3 I/O Programming Considerations EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
5.3.1 BIDIRECTIONAL I/O PORTS I/O PORT
Any instruction that writes, operates internally as a read ;Initial PORT settings:PORTB<7:4> Inputs
; PORTB<3:0> Outputs
followed by a write operation. The BCF and BSF instruc-
;PORTB<7:6> have external pull-up and are
tions, for example, read the register into the CPU, ;not connected to other circuitry
execute the bit operation and write the result back to ;
the register. Caution must be used when these instruc- ; PORT latchPORT Pins
tions are applied to a port with both inputs and outputs ---------- ----------
defined. For example, a BSF operation on bit5 of BCF STATUS, RP0 ;
PORTB will cause all eight bits of PORTB to be read BCF PORTB, 7 ;01pp pppp 11pp pppp
into the CPU. Then the BSF operation takes place on BSF STATUS, RP0 ;
bit5 and PORTB is written to the output latches. If BCF TRISB, 7 ;10pp pppp 11pp pppp
another bit of PORTB is used as a bidirectional I/O pin BCF TRISB, 6 ;10pp pppp 10pp pppp
;
(e.g., bit 0) and is defined as an input at this time, the
;Note that the user may have expected the
input signal present on the pin itself would be read into ;pin values to be 00pp pppp. The 2nd BCF
the CPU and rewritten to the data latch of this particular ;caused RB7 to be latched as the pin value
pin, overwriting the previous content. As long as the pin ;(High).
stays in the Input mode, no problem occurs. However,
if bit 0 is switched into Output mode later on, the con- 5.3.2 SUCCESSIVE OPERATIONS ON I/O
tent of the data latch may now be unknown.
PORTS
Reading a port register reads the values of the port
pins. Writing to the port register writes the value to the The actual write to an I/O port happens at the end of an
port latch. When using read-modify-write instructions instruction cycle, whereas for reading, the data must be
(ex. BCF, BSF, etc.) on a port, the value of the port pins valid at the beginning of the instruction cycle (Figure 5-
is read, the desired operation is done to this value, and 16). Therefore, care must be exercised if a write
this value is then written to the port latch. followed by a read operation is carried out on the same
I/O port. The sequence of instructions should be such
Example 5-2 shows the effect of two sequential read- to allow the pin voltage to stabilize (load dependent)
modify-write instructions (ex., BCF, BSF, etc.) on an before the next instruction, which causes that file to be
I/O port. read into the CPU, is executed. Otherwise, the
A pin actively outputting a Low or High should not be previous state of that pin may be read into the CPU
driven from external devices at the same time in order rather than the new state. When in doubt, it is better to
to change the level on this pin (“wired-or”, “wired-and”). separate these instructions with a NOP or another
The resulting high output currents may damage the instruction not accessing this I/O port.
chip.

FIGURE 5-16: SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC PC + 1 PC + 2 PC + 3
Instruction MOVWF PORTB MOVF PORTB, W NOP NOP
fetched Write to PORTB Read to PORTB

Port pin
sampled here

TPD
Execute Execute Execute
MOVWF MOVF NOP
PORTB PORTB, W

Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Therefore, at higher clock frequencies, a write followed by a read may be problematic.


PIC16F627A/628A/648A
6.0 TIMER0 MODULE 6.2 Using Timer0 with External Clock
The Timer0 module timer/counter has the following When an external clock input is used for Timer0, it must
features: meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
• 8-bit timer/counter
synchronization. Also, there is a delay in the actual
• Read/Write capabilities incrementing of Timer0 after synchronization.
• 8-bit software programmable prescaler
• Internal or external clock select 6.2.1 EXTERNAL CLOCK
• Interrupt on overflow from FFh to 00h SYNCHRONIZATION
• Edge select for external clock When no prescaler is used, the external clock input is
Figure 6-1 is a simplified block diagram of the Timer0 the same as the prescaler output. The synchronization
module. Additional information is available in the of T0CKI with the internal phase clocks is
PICmicro® Mid-Range MCU Family Reference Manual accomplished by sampling the prescaler output on the
(DS33023). Q2 and Q4 cycles of the internal phase clocks
(Figure 6-1). Therefore, it is necessary for T0CKI to be
Timer mode is selected by clearing the T0CS bit
high for at least 2TOSC (and a small RC delay of 20 ns)
(OPTION<5>). In Timer mode, the TMR0 register value
and low for at least 2TOSC (and a small RC delay of
will increment every instruction cycle (without
20 ns). Refer to the electrical specification of the
prescaler). If the TMR0 register is written to, the
desired device.
increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value When a prescaler is used, the external clock input is
to the TMR0 register. divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
Counter mode is selected by setting the T0CS bit. In
For the external clock to meet the sampling
this mode the TMR0 register value will increment either
requirement, the ripple-counter must be taken into
on every rising or falling edge of pin RA4/T0CKI. The
account. Therefore, it is necessary for T0CKI to have a
incrementing edge is determined by the source edge
period of at least 4TOSC (and a small RC delay of 40 ns)
(T0SE) control bit (OPTION<4>). Clearing the T0SE bit
divided by the prescaler value. The only requirement
selects the rising edge. Restrictions on the external
on T0CKI high and low time is that they do not violate
clock input are discussed in detail in Section 6.2
the minimum pulse width requirement of 10 ns. Refer to
"Using Timer0 with External Clock".
parameters 40, 41 and 42 in the electrical specification
The prescaler is shared between the Timer0 module of the desired device. See Table 17-8.
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 "Timer0 Prescaler" details
the operation of the prescaler.

6.1 Timer0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by clear-
ing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut
off during Sleep.


PIC16F627A/628A/648A
6.3 Timer0 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog When assigned to the Timer0 module, all instructions
Timer. A prescaler assignment for the Timer0 module writing to the TMR0 register (e.g., CLRF 1,
means that there is no postscaler for the Watchdog MOVWF 1, BSF 1, x....etc.) will clear the
Timer, and vice-versa. prescaler. When assigned to WDT, a CLRWDT instruc-
tion will clear the prescaler along with the Watchdog
Timer. The prescaler is not readable or writable.

FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT

FOSC/4 DATA BUS

8
0

T0CKI 1 SYNC
PIN 1 TMR0 REG
2
0 CYCLES

T0SE
T0CS
SET FLAG BIT T0IF
TMR1 Clock Source PSA
ON OVERFLOW

0
WDT POSTSCALER/
WATCHDOG TMR0 PRESCALER
1
TIMER
8
PSA
8-TO-1MUX PS0 - PS2

WDT ENABLE BIT

1
WDT
0 TIME OUT

PSA

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option Register.
.


PIC16F627A/628A/648A
6.3.1 SWITCHING PRESCALER To change prescaler from the WDT to the Timer0
ASSIGNMENT module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
EXAMPLE 6-2: CHANGING PRESCALER
program execution). Use the instruction sequences
(WDT→TIMER0)
shown in Example 6-1 when changing the prescaler
assignment from Timer0 to WDT, to avoid an CLRWDT ;Clear WDT and
unintended device Reset. ;prescaler
BSF STATUS, RP0
MOVLW b'xxxx0xxx' ;Select TMR0, new
EXAMPLE 6-1: CHANGING PRESCALER ;prescale value and
(TIMER0→WDT) ;clock source
BCF STATUS, RP0 ;Skip if already in MOVWF OPTION_REG
;Bank 0 BCF STATUS, RP0
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;Prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW '00101111’b ;These 3 lines
;(5, 6, 7)
MOVWF OPTION_REG ;are required only
;if desired PS<2:0>
;are
CLRWDT ;000 or 001
MOVLW '00101xxx’b ;Set Postscaler to
MOVWF OPTION_REG ;desired WDT rate
BCF STATUS, RP0 ;Return to Bank 0

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
POR
Resets
01h, 101h TMR0 Timer0 module register xxxx xxxx uuuu uuuu
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh

81h, 181h OPTION(2) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by Timer0 module.
2: Option is referred by OPTION_REG in MPLAB®.


PIC16F627A/628A/648A
7.0 TIMER1 MODULE The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
The Timer1 module is a 16-bit timer/counter consisting
In Timer mode, the TMR1 register pair value
of two 8-bit registers (TMR1H and TMR1L) which are
increments every instruction cycle. In Counter mode, it
readable and writable. The TMR1 register pair
increments on every rising edge of the external clock
(TMR1H:TMR1L) increments from 0000h to FFFFh
input.
and rolls over to 0000h. The Timer1 Interrupt, if
enabled, is generated on overflow of the TMR1 register Timer1 can be enabled/disabled by setting/clearing
pair which latches the interrupt flag bit TMR1IF control bit TMR1ON (T1CON<0>).
(PIR1<0>). This interrupt can be enabled/disabled by Timer1 also has an internal “Reset input”. This Reset
setting/clearing the Timer1 interrupt enable bit TMR1IE can be generated by the CCP module (Section 9.0
(PIE1<0>). "Capture/Compare/PWM (CCP) Module").
Timer1 can operate in one of two modes: Register 7-1 shows the Timer1 control register.
• As a timer For the PIC16F627A/628A/648A, when the Timer1
• As a counter oscillator is enabled (T1OSCEN is set), the RB7/T1OSI
and RB6/T1OSO/T1CKI pins become inputs. That is,
the TRISB<7:6> value is ignored.

REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.

Legend:


PIC16F627A/628A/648A
7.1 Timer1 Operation in Timer Mode 7.2.1 EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
Timer mode is selected by clearing the TMR1CS
MODE
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC When an external clock input is used for Timer1 in
(T1CON<2>) has no effect since the internal clock is synchronized Counter mode, it must meet certain
always in sync. requirements. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
7.2 Timer1 Operation in Synchronized is a delay in the actual incrementing of the TMR1
Counter Mode register pair value after synchronization.
Counter mode is selected by setting bit TMR1CS. In When the prescaler is 1:1, the external clock input is
this mode the TMR1 register pair value increments on the same as the prescaler output. The synchronization
every rising edge of clock input on pin RB7/T1OSI of T1CKI with the internal phase clocks is accom-
when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI plished by sampling the prescaler output on the Q2 and
when bit T1OSCEN is cleared. Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
If T1SYNC is cleared, then the external clock input is a small RC delay of 20 ns) and low for at least 2Tosc
synchronized with internal phase clocks. The synchro- (and a small RC delay of 20 ns). Refer to the appropri-
nization is done after the prescaler stage. The ate electrical specifications, parameters 45, 46, and 47.
prescaler stage is an asynchronous ripple-counter.
When a prescaler other than 1:1 is used, the external
In this configuration, during Sleep mode, the TMR1 clock input is divided by the asynchronous ripple-
register pair value will not increment even if the counter type prescaler so that the prescaler output is
external clock is present, since the synchronization symmetrical. In order for the external clock to meet the
circuit is shut off. The prescaler however will continue sampling requirement, the ripple-counter must be
to increment. taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of 10
ns). Refer to the appropriate electrical specifications,
parameters 45, 46, and 47.

FIGURE 7-1: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow Synchronized
TMR1 0
Clock Input
TMR1H TMR1L
1
TMR1ON
T1SYNC
T1OSC
RB6/T1OSO/T1CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
RB7/T1OSI Oscillator(1) Clock 2
Sleep Input
T1CKPS1:T1CKPS0
TMR1CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.


PIC16F627A/628A/648A
7.3 Timer1 Operation in EXAMPLE 7-1: READING A 16-BIT FREE-
Asynchronous Counter Mode RUNNING TIMER
; All interrupts are disabled
If control bit T1SYNC (T1CON<2>) is set, the external MOVF TMR1H, W ;Read high byte
clock input is not synchronized. The timer continues to MOVWF TMPH ;
increment asynchronous to the internal phase clocks. MOVF TMR1L, W ;Read low byte
The timer will continue to run during Sleep and can MOVWF TMPL ;
generate an interrupt on overflow, which will wake-up MOVF TMR1H, W ;Read high byte
the processor. However, special precautions in soft- SUBWF TMPH, W ;Sub 1st read with
ware are needed to read/write the timer (Section 7.3.2 ;2nd read
"Reading and Writing Timer1 in Asynchronous BTFSC STATUS,Z ;Is result = 0
GOTO CONTINUE ;Good 16-bit read
Counter Mode").
;
Note: In Asynchronous Counter mode, Timer1 ; TMR1L may have rolled over between the
cannot be used as a time-base for capture ; read of the high and low bytes. Reading
or compare operations. ; the high and low bytes now will read a good
; value.
;
7.3.1 EXTERNAL CLOCK INPUT TIMING
MOVF TMR1H, W ;Read high byte
WITH UNSYNCHRONIZED CLOCK MOVWF TMPH ;
If control bit T1SYNC is set, the timer will increment MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
completely asynchronously. The input clock must meet
; Re-enable the Interrupts (if required)
certain minimum high and low time requirements. Refer CONTINUE ;Continue with your
to Table 17-8 in the Electrical Specifications Section, ;code
timing parameters 45, 46, and 47.

7.3.2 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading the TMR1H or TMR1L register while the timer
is running, from an external asynchronous clock, will
produce a valid read (taken care of in hardware).
However, the user should keep in mind that reading the
16-bit timer in two 8-bit values itself poses certain
problems since the timer may overflow between the
reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.


PIC16F627A/628A/648A
7.4 Timer1 Oscillator 7.5 Resetting Timer1 Using a CCP
A crystal oscillator circuit is built in between pins T1OSI
Trigger Output
(input) and T1OSO (amplifier output). It is enabled by If the CCP1 module is configured in Compare mode to
setting control bit T1OSCEN (T1CON<3>). It will generate a “special event trigger” (CCP1M3:CCP1M0
continue to run during Sleep. It is primarily intended for = 1011), this signal will Reset Timer1.
a 32.768 kHz watch crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator. Note: The special event triggers from the CCP1
module will not set interrupt flag bit
The user must provide a software time delay to ensure TMR1IF (PIR1<0>).
proper oscillator start-up.
Timer1 must be configured for either timer or synchro-
nized Counter mode to take advantage of this feature.
TABLE 7-1: CAPACITOR SELECTION FOR
If Timer1 is running in Asynchronous Counter mode,
THE TIMER1 OSCILLATOR
this Reset operation may not work.
Freq C1 C2 In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
32.768 kHz 15 pF 15 pF
precedence.
These values are for design guidance only.
Consult AN826 (DS00826) for further information In this mode of operation, the CCPRxH:CCPRxL
on Crystal/Capacitor Selection. registers pair effectively becomes the period register
for Timer1.

7.6 Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other Reset except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.

7.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.

TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR
Resets
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.


PIC16F627A/628A/648A
8.0 TIMER2 MODULE 8.1 Timer2 Prescaler and Postscaler
Timer2 is an 8-bit timer with a prescaler and a The prescaler and postscaler counters are cleared
postscaler. It can be used as the PWM time-base for when any of the following occurs:
PWM mode of the CCP module. The TMR2 register is • a write to the TMR2 register
readable and writable, and is cleared on any device
• a write to the T2CON register
Reset.
• any device Reset (Power-on Reset, MCLR Reset,
The input clock (FOSC/4) has a prescale option of 1:1, Watchdog Timer Reset, or Brown-out Reset)
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The TMR2 register is not cleared when T2CON is
written.
The Timer2 module has an 8-bit period register PR2.
The TMR2 register value increments from 00h until it 8.2 TMR2 Output
matches the PR2 register value and then resets to 00h
on the next increment cycle. The PR2 register is a The TMR2 output (before the postscaler) is fed to the
readable and writable register. The PR2 register is Synchronous Serial Port module which optionally uses
initialized to FFh upon Reset. it to generate shift clock.
The match output of Timer2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive) FIGURE 8-1: TIMER2 BLOCK DIAGRAM
to generate a Timer2 interrupt (latched in flag bit
Sets flag
TMR2IF, (PIR1<1>)). bit TMR2IF
TMR2
output
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption. Reset Prescaler
TMR2 reg FOSC/4
Register 8-1 shows the Timer2 control register. 1:1, 1:4, 1:16
Postscaler 2
Comparator
1:1 to 1:16 EQ
T2CKPS<1:0>
4 PR2 reg
TOUTPS<3:0>


PIC16F627A/628A/648A
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale Value
0001 = 1:2 Postscale Value
•
•
•
1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = 1:1 Prescaler Value
01 = 1:4 Prescaler Value
1x = 1:16 Prescaler Value

Legend:

TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
Value on
POR
Resets
10Bh, 18Bh


11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
9.0 CAPTURE/COMPARE/PWM TABLE 9-1: CCP MODE - TIMER
(CCP) MODULE RESOURCE

The CCP (Capture/Compare/PWM) module contains a CCP Mode Timer Resource
16-bit register which can operate as a 16-bit capture Capture Timer1
register, as a 16-bit compare register or as a PWM Compare Timer1
master/slave Duty Cycle register. Table 9-1 shows the PWM Timer2
timer resources of the CCP module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
Additional information on the CCP module is available
in the PICmicro® Mid-Range Reference Manual
(DS33023).

REGISTER 9-1: CCP1CON REGISTER (ADDRESS: 17h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0

bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
bit 3-0 CCP1M3:CCP1M0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode

Legend:


PIC16F627A/628A/648A
9.1 Capture Mode 9.1.4 CCP PRESCALER
In Capture mode, CCPR1H:CCPR1L captures the There are four prescaler settings, specified by bits
16-bit value of the TMR1 register when an event occurs CCP1M3:CCP1M0. Whenever the CCP module is
on pin RB3/CCP1. An event is defined as: turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
• Every falling edge
Reset will clear the prescaler counter.
• Every rising edge
Switching from one capture prescaler to another may
• Every 4th rising edge
generate an interrupt. Also, the prescaler counter will
• Every 16th rising edge not be cleared, therefore the first capture may be from
An event is selected by control bits CCP1M3:CCP1M0 a non-zero prescaler. Example 9-1 shows the recom-
(CCP1CON<3:0>). When a capture is made, the inter- mended method for switching between capture
rupt request flag bit CCP1IF (PIR1<2>) is set. It must prescalers. This example also clears the prescaler
be cleared in software. If another capture occurs before counter and will not generate the “false” interrupt.
the value in register CCPR1 is read, the old captured
value will be lost. EXAMPLE 9-1: CHANGING BETWEEN
CAPTURE PRESCALERS
9.1.1 CCP PIN CONFIGURATION
CLRF CCP1CON ;Turn CCP module off
In Capture mode, the RB3/CCP1 pin should be config- MOVLW NEW_CAPT_PS ;Load the W reg with
ured as an input by setting the TRISB<3> bit. ; the new prescaler
; mode value and CCP ON
Note: If the RB3/CCP1 is configured as an MOVWF CCP1CON ;Load CCP1CON with this
output, a write to the port can cause a ; value
capture condition.
9.2 Compare Mode
FIGURE 9-1: CAPTURE MODE
OPERATION BLOCK In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
DIAGRAM
value. When a match occurs, the RB3/CCP1 pin is:
Set flag bit CCP1IF • Driven High
Prescaler (PIR1<2>)
³ 1, 4, 16 • Driven Low
RB3/CCP1 CCPR1H CCPR1L • Remains Unchanged
Pin
The action on the pin is based on the value of control
and Capture
Enable
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
edge detect
same time, interrupt flag bit CCP1IF is set.
TMR1H TMR1L
CCP1CON<3:0>
Q’s
FIGURE 9-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
9.1.2 TIMER1 MODE SELECTION
Set flag bit CCP1IF
Timer1 must be running in Timer mode or synchronized (PIR1<2>)
Counter mode for the CCP module to use the capture CCPR1H CCPR1L
feature. In Asynchronous Counter mode, the capture Q S Output
operation may not work. Logic match
Comparator
RB3/CCP1 R
Pin
9.1.3 SOFTWARE INTERRUPT TRISB<3> TMR1H TMR1L
Output Enable CCP1CON<3:0>
When the Capture mode is changed, a false capture Mode Select

interrupt may be generated. The user should keep bit
Note: Special event trigger will reset Timer1, but not
CCP1IE (PIE1<2>) clear to avoid false interrupts and set interrupt flag bit TMR1IF (PIR1<0>).
should clear the flag bit CCP1IF following any such
change in Operating mode.


PIC16F627A/628A/648A
9.2.1 CCP PIN CONFIGURATION 9.2.3 SOFTWARE INTERRUPT MODE
The user must configure the RB3/CCP1 pin as an When generate software interrupt is chosen the CCP1
output by clearing the TRISB<3> bit. pin is not affected. Only a CCP interrupt is generated (if
enabled).
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the 9.2.4 SPECIAL EVENT TRIGGER
default low level. This is not the data latch.
In this mode, an internal hardware trigger is generated
9.2.2 TIMER1 MODE SELECTION which may be used to initiate an action.
Timer1 must be running in Timer mode or Synchro- The special event trigger output of CCP1 resets the
nized Counter mode if the CCP module is using the TMR1 register pair. This allows the CCPR1 register to
compare feature. In Asynchronous Counter mode, the effectively be a 16-bit programmable period register for
compare operation may not work. Timer1.

TABLE 9-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
Value on
POR
Resets
10Bh, 18Bh
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.


PIC16F627A/628A/648A
9.3 PWM Mode A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
In Pulse Width Modulation (PWM) mode, the CCP1 pin frequency of the PWM is the inverse of the period
produces up to a 10-bit resolution PWM output. Since (frequency = 1/period).
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
FIGURE 9-4: PWM OUTPUT
pin an output.
Note: Clearing the CCP1CON register will force Period
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Figure 9-3 shows a simplified block diagram of the Duty Cycle
CCP module in PWM mode.
TMR2 = PR2
For a step by step procedure on how to set up the CCP
TMR2 = Duty Cycle
module for PWM operation, see Section 9.3.3 "Set-Up
for PWM Operation". TMR2 = PR2

FIGURE 9-3: SIMPLIFIED PWM BLOCK
9.3.1 PWM PERIOD
DIAGRAM
The PWM period is specified by writing to the PR2
CCP1CON<5:4>
Duty cycle registers register. The PWM period can be calculated using the
CCPR1L following formula:
PWM period = [ ( PR2 ) + 1 ] ⋅ 4 ⋅ Tosc ⋅ TMR2 prescale
value

CCPR1H (Slave) PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
Comparator R Q occur on the next increment cycle:

RB3/CCP1 • TMR2 is cleared
TMR2 (1) • The CCP1 pin is set (exception: if PWM duty
S
cycle = 0%, the CCP1 pin will not be set)
Comparator TRISB<3> • The PWM duty cycle is latched from CCPR1L into
Clear Timer, CCPR1H
CCP1 pin and
latch D.C.
PR2
Note: The Timer2 postscaler (see Section 8.0) is
Note 1: 8-bit timer is concatenated with 2-bit internal Q
not used in the determination of the PWM
clock or 2 bits of the prescaler to create 10-bit frequency. The postscaler could be used to
time-base. have a servo update rate at a different
frequency than the PWM output.


PIC16F627A/628A/648A
9.3.2 PWM DUTY CYCLE Maximum PWM resolution (bits) for a given PWM
frequency:
The PWM duty cycle is specified by writing to the
log  -------------------------------------------------------------
CCPR1L register and to the CCP1CON<5:4> bits. Up Fosc
to 10-bit resolution is available: the CCPR1L contains PWM  Fpwm × TMR2 Prescaler
Resolution = -------------------------------------------------------------------------- bits
-
the eight MSbs and the CCP1CON<5:4> contains the log(2)
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Note: If the PWM duty cycle value is longer than
PWM duty cycle = the PWM period the CCP1 pin will not be
cleared.
(CCPR1L:CCP1CON<5:4>) ⋅ Tosc ⋅ TMR2 prescale
For an example PWM period and duty cycle
value calculation, see the PICmicro® Mid-Range Reference
CCPR1L and CCP1CON<5:4> can be written to at any Manual (DS33023).
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2 9.3.3 SET-UP FOR PWM OPERATION
occurs (i.e., the period is complete). In PWM mode, The following steps should be taken when configuring
CCPR1H is a read-only register. the CCP module for PWM operation:
The CCPR1H register and a 2-bit internal latch are 1. Set the PWM period by writing to the PR2
used to double buffer the PWM duty cycle. This double register.
buffering is essential for glitch less PWM operation.
2. Set the PWM duty cycle by writing to the
When the CCPR1H and 2-bit latch match TMR2 CCPR1L register and CCP1CON<5:4> bits.
concatenated with an internal 2-bit Q clock or 2 bits of 3. Make the CCP1 pin an output by clearing the
the TMR2 prescaler, the CCP1 pin is cleared. TRISB<3> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.

TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.5

TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on
POR
Resets
10Bh, 18Bh
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
10.0 COMPARATOR MODULE The CMCON register, shown in Register 10-1, controls
the comparator input and output multiplexers. A block
The Comparator module contains two analog diagram of the comparator is shown in Figure 10-1.
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The on-chip
Voltage Reference (Section 11.0 "Voltage Reference
Module") can also be an input to the comparators.

REGISTER 10-1: CMCON REGISTER (ADDRESS: 01Fh)
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0

bit 7 C2OUT: Comparator 2 Output
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-

When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-

When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion
1 = C2 Output inverted
0 = C2 Output not inverted
bit 4 C1INV: Comparator 1 Output Inversion
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Comparator Input Switch
When CM2:CM0: = 001
Then:
1 = C1 VIN- connects to RA3

When CM2:CM0 = 010
Then:
C2 VIN- connects to RA2
C2 VIN- connects to RA1
bit 2-0 CM2:CM0: Comparator Mode
Figure 10-1 shows the Comparator modes and CM2:CM0 bit settings

Legend:


PIC16F627A/628A/648A
10.1 Comparator Configuration If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
There are eight modes of operation for the change delay shown in Table 17-2.
comparators. The CMCON register is used to select
the mode. Figure 10-1 shows the eight possible Note 1: Comparator interrupts should be disabled
modes. The TRISA register controls the data direction during a Comparator mode change,
of the comparator pins for each mode. otherwise a false interrupt may occur.
2: Comparators can have an inverted
output. See Figure 10-3.

FIGURE 10-1: COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value) Comparators Off
CM2:CM0 = 000 CM2:CM0 = 111
RA0/AN0 D VIN-
RA0/AN0 A VIN-
D VIN+ C1 Off (Read as '0')
C1 Off (Read as '0') RA3/AN3/CMP1
RA3/AN3/CMP1 A VIN+

D VIN-
RA1/AN1 A VIN- RA1/AN1
Off (Read as '0') D VIN+ C2 Off (Read as '0')
RA2/AN2/VREF A VIN+ C2 RA2/AN2/VREF
VSS
Four Inputs Multiplexed to Two Comparators
Two Independent Comparators CM2:CM0 = 010
CM2:CM0 = 100
RA0/AN0 A
A VIN- CIS = 0 VIN-
RA0/AN0
C1 C1VOUT RA3/AN3/CMP1 A CIS = 1
C1 C1VOUT
A VIN+ VIN+
RA3/AN3/CMP1

RA1/AN1 A
CIS = 0 VIN-
RA1/AN1 A VIN- RA2/AN2/VREF A CIS = 1 C2VOUT
VIN+ C2
C2 C2VOUT
RA2/AN2/VREF A VIN+

From VREF
Module

Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 011 CM2:CM0 = 110
A VIN-
A VIN- RA0/AN0
RA0/AN0 C1VOUT
D VIN+ C1
D VIN+ C1 C1VOUT RA3/AN3/CMP1
RA3/AN3/CMP1

RA1/AN1 A VIN-
RA1/AN1 A VIN-
C2VOUT A VIN+ C2 C2VOUT
RA2/AN2/VREF A VIN+ C2 RA2/AN2/VREF

RA4/T0CKI/CMP2 Open Drain

One Independent Comparator Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 101 CM2:CM0 = 001

RA0/AN0 D VIN- A
RA0/AN0 CIS = 0 VIN-
VIN+ C1 Off (Read as '0')
RA3/AN3/CMP1 D RA3/AN3/CMP1 A CIS = 1
C1 C1VOUT
VIN+
VSS

RA1/AN1 A VIN- RA1/AN1 A VIN-
A VIN+ C2 C2VOUT C2 C2VOUT
RA2/AN2/VREF A VIN+
RA2/AN2/VREF

A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.


PIC16F627A/628A/648A
The code example in Example 10-1 depicts the steps FIGURE 10-2: SINGLE COMPARATOR
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are Vin+ +
configured as the V- inputs and RA2 as the V+ input to Result
both comparators. Vin- –

EXAMPLE 10-1: INITIALIZING
COMPARATOR MODULE
FLAG_REG EQU 0X20
CLRF FLAG_REG ;Init flag register VIN-
CLRF PORTA ;Init PORTA
MOVF CMCON, W ;Load comparator bits
ANDLW 0xC0 ;Mask comparator bits VIN+
IORWF FLAG_REG,F ;Store bits in flag register
MOVLW 0x03 ;Init comparator mode
MOVWF CMCON ;CM<2:0> = 011
BSF STATUS,RP0 ;Select Bank1
MOVLW 0x07 ;Initialize data direction
MOVWF TRISA ;Set RA<2:0> as inputs Result
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
BCF STATUS,RP0 ;Select Bank 0
CALL DELAY10 ;10µs delay 10.3.1 EXTERNAL REFERENCE SIGNAL
MOVF CMCON,F ;Read CMCON to end change
;condition When external voltage references are used, the
BCF PIR1,CMIF ;Clear pending interrupts Comparator module can be configured to have the
BSF STATUS,RP0 ;Select Bank 1
BSF PIE1,CMIE ;Enable comparator interrupts comparators operate from the same or different
BCF STATUS,RP0 ;Select Bank 0 reference sources. However, threshold detector
BSF INTCON,PEIE ;Enable peripheral interrupts applications may require the same reference. The
BSF INTCON,GIE ;Global interrupt enable
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
10.2 Comparator Operation
A single comparator is shown in Figure 10-2 along with 10.3.2 INTERNAL REFERENCE SIGNAL
the relationship between the analog input levels and The Comparator module also allows the selection of
the digital output. When the analog input at VIN+ is less an internally generated voltage reference for the
than the analog input VIN-, the output of the comparator comparators. Section 11.0 "Voltage Reference
is a digital low level. When the analog input at VIN+ is Module", contains a detailed description of the
greater than the analog input VIN-, the output of the Voltage Reference Module that provides this signal.
comparator is a digital high level. The shaded areas of The internal reference signal is used when the com-
the output of the comparator in Figure 10-2 represent parators are in mode CM<2:0>=010 (Figure 10-1). In
the uncertainty due to input offsets and response time. this mode, the internal voltage reference is applied to
See Table 17-2 for Common Mode Voltage. the VIN+ pin of both comparators.
10.3 Comparator Reference 10.4 Comparator Response Time
An external or internal reference signal may be used Response time is the minimum time, after selecting a
depending on the comparator Operating mode. The new reference voltage or input source, before the
analog signal that is present at VIN- is compared to the comparator output is to have a valid level. If the internal
signal at VIN+, and the digital output of the comparator reference is changed, the maximum delay of the inter-
is adjusted accordingly (Figure 10-2). nal voltage reference must be considered when using
the comparator outputs. Otherwise, the maximum
delay of the comparators should be used (Table 17-2).


PIC16F627A/628A/648A
10.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110 or 001, multiplexors
in the output path of the RA3 and RA4/T0CK1 pins will
switch and the output of each pin will be the unsynchro-
nized output of the comparator. The uncertainty of each
of the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 10-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4/T0CK1 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.

FIGURE 10-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM

CnINV

To RA3 or RA4/T0CK1 pin
CnVOUT
To Data Bus Q D
CMCON<7:6>
Q3
EN

RD CMCON

Set CMIF bit Q D

EN Q1
CL
From other Comparator
Reset


PIC16F627A/628A/648A
10.6 Comparator Interrupts 10.7 Comparator Operation During
The comparator interrupt flag is set whenever there is
Sleep
a change in the output value of either comparator. When a comparator is active and the device is placed
Software will need to maintain information about the in Sleep mode, the comparator remains active and the
status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will
determine the actual change that has occurred. The wake-up the device from Sleep mode when enabled.
CMIF bit, PIR1<6>, is the comparator interrupt flag. While the comparator is powered-up, higher Sleep
The CMIF bit must be Reset by clearing ‘0’. Since it is currents than shown in the power-down current
also possible to write a ‘1’ to this register, a simulated specification will occur. Each comparator that is
interrupt may be initiated. operational will consume additional current as shown in
The CMIE bit (PIE1<6>) and the PEIE bit the comparator specifications. To minimize power
(INTCON<6>) must be set to enable the interrupt. In consumption while in Sleep mode, turn off the
addition, the GIE bit must also be set. If any of these comparators, CM<2:0> = 111, before entering Sleep. If
bits are clear, the interrupt is not enabled, though the the device wakes up from Sleep, the contents of the
CMIF bit will still be set if an interrupt condition occurs. CMCON register are not affected.
Note: If a change in the CMCON register 10.8 Effects of a Reset
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of A device Reset forces the CMCON register to its Reset
the Q2 cycle), then the CMIF (PIR1<6>) state. This forces the Comparator module to be in the
interrupt flag may not get set. comparator Reset mode, CM2:CM0 = 000. This
ensures that all potential inputs are analog inputs.
The user, in the interrupt service routine, can clear the
Device current is minimized when analog inputs are
interrupt in the following manner:
present at Reset time. The comparators will be
a) Any write or read of CMCON. This will end the powered-down during the Reset interval.
mismatch condition.
b) Clear flag bit CMIF. 10.9 Analog Input Connection
A mismatch condition will continue to set flag bit CMIF. Considerations
Reading CMCON will end the mismatch condition and A simplified circuit for an analog input is shown in
allow flag bit CMIF to be cleared. Figure 10-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.


PIC16F627A/628A/648A
FIGURE 10-4: ANALOG INPUT MODE
VDD

VT = 0.6V RIC
RS < 10 K

AIN
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF

VSS
Legend CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current At The Pin
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage

TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
Value on
POR
Resets
1Fh CMCON C2OUT C1OUT C2INV C1NV CIS CM2 CM1 CM0 0000 0000 0000 0000
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
Legend: x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’


PIC16F627A/628A/648A
11.0 VOLTAGE REFERENCE The equations used to calculate the output of the
Voltage Reference are as follows:
MODULE
if VRR = 1:
The Voltage Reference is a 16-tap resistor ladder
VR <3:0>
network that provides a selectable voltage reference. VREF = --------------------- × VDD
-
The resistor ladder is segmented to provide two ranges 24
of VREF values and has a power-down function to if VRR = 0:
conserve power when the reference is not being used.
VREF =  VDD × -- + --------------------- × VDD
The VRCON register controls the operation of the 1 VR <3:0>
- -
reference as shown in Figure 11-1. The block diagram  4 32
is given in Figure 11-1.
The setting time of the Voltage Reference must be
considered when changing the VREF output
11.1 Voltage Reference Configuration
(Table 17-3). Example 11-1 demonstrates how Voltage
The Voltage Reference can output 16 distinct voltage Reference is configured for an output voltage of 1.25V
levels for each range. with VDD = 5.0V.

REGISTER 11-1: VRCON REGISTER (ADDRESS: 9Fh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR — VR3 VR2 VR1 VR0
bit 7 bit 0

bit 7 VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6 VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5 VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 3-0 VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: VREF = (VR<3:0>/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD

Legend:

FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM
VDD 16 Stages

VREN
8R R R R R

8R VRR

VSS VSS

VR3
VREF 16-1 Analog Mux (From VRCON<3:0>)
VR0

Note: R is defined in Table 17-3.


PIC16F627A/628A/648A
EXAMPLE 11-1: VOLTAGE REFERENCE 11.4 Effects of a Reset
CONFIGURATION
A device Reset disables the Voltage Reference by
MOVLW 0x02 ;4 Inputs Muxed
clearing bit VREN (VRCON<7>). This Reset also
MOVWF CMCON ;to 2 comps.
BSF STATUS,RP0 ;go to Bank 1 disconnects the reference from the RA2 pin by clearing
MOVLW 0x07 ;RA3-RA0 are bit VROE (VRCON<6>) and selects the high voltage
MOVWF TRISA ;outputs range by clearing bit VRR (VRCON<5>). The VREF
MOVLW 0xA6 ;enable VREF value select bits, VRCON<3:0>, are also cleared.
MOVWF VRCON ;low range set VR<3:0>=6
BCF STATUS,RP0 ;go to Bank 0 11.5 Connection Considerations
CALL DELAY10 ;10µs delay
The Voltage Reference Module operates
independently of the comparator module. The output of
11.2 Voltage Reference Accuracy/Error the reference generator may be connected to the RA2
The full range of VSS to VDD cannot be realized due to pin if the TRISA<2> bit is set and the VROE bit,
the construction of the module. The transistors on the VRCON<6>, is set. Enabling the Voltage Reference
top and bottom of the resistor ladder network output onto the RA2 pin with an input signal present will
(Figure 11-1) keep VREF from approaching VSS or VDD. increase current consumption. Connecting RA2 as a
The Voltage Reference is VDD derived and therefore, digital output with VREF enabled will also increase
the VREF output changes with fluctuations in VDD. The current consumption.
tested absolute accuracy of the Voltage Reference can The RA2 pin can be used as a simple D/A output with
be found in Table 17-3. limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
11.3 Operation During Sleep Voltage Reference output for external connections to
When the device wakes up from Sleep through an VREF. Figure 11-2 shows an example buffering
interrupt or a Watchdog Timer time out, the contents of technique.
the VRCON register are not affected. To minimize
current consumption in Sleep mode, the Voltage
Reference should be disabled.

FIGURE 11-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

Opamp
R(1) RA2
VREF +
Module VREF Output

Voltage
Reference
Output
Impedance

Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.

TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Value On
Value On
POR
Resets
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
Legend: — = Unimplemented, read as ‘0’.


PIC16F627A/628A/648A
12.0 UNIVERSAL SYNCHRONOUS The USART can be configured in the following modes:
ASYNCHRONOUS RECEIVER • Asynchronous (full-duplex)
TRANSMITTER (USART) • Synchronous - Master (half-duplex)
MODULE • Synchronous - Slave (half-duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to
The Universal Synchronous Asynchronous Receiver
be set in order to configure pins RB2/TX/CK and RB1/
Transmitter (USART) is also known as a Serial
RX/DT as the Universal Synchronous Asynchronous
Communications Interface or SCI. The USART can be
Receiver Transmitter.
configured as a full-duplex asynchronous system that
can communicate with peripheral devices such as CRT Register 12-1 shows the Transmit Status and Control
terminals and personal computers, or it can be config- Register (TXSTA) and Register 12-2 shows the
ured as a half-duplex synchronous system that can Receive Status and Control Register (RCSTA).
communicate with peripheral devices such as A/D or D/
A integrated circuits, Serial EEPROMs, etc.

REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0

bit 7 CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be parity bit.
Note: SREN/CREN overrides TXEN in SYNC mode.

Legend:


PIC16F627A/628A/648A
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADEN FERR OERR RX9D
bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2 FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of received data (Can be parity bit)

Legend:


PIC16F627A/628A/648A
12.1 USART Baud Rate Generator EXAMPLE 12-1: CALCULATING BAUD
(BRG) RATE ERROR
The BRG supports both the Asynchronous and Fosc
Desired Baud Rate = ----------------------
-
Synchronous modes of the USART. It is a dedicated 8- 64 ( x + 1 )
bit baud rate generator. The SPBRG register controls
the period of a free running 8-bit timer. In Asynchro-
nous mode bit BRGH (TXSTA<2>) also controls the 16000000
9600 = -----------------------
-
baud rate. In Synchronous mode bit BRGH is ignored. 64 ( x + 1 )
Table 12-1 shows the formula for computation of the
baud rate for different USART modes, which only apply x = 25.042
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest 16000000
Calculated Baud Rate = ------------------------- = 9615
-
integer value for the SPBRG register can be calculated 64 ( 25 + 1 )
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate (Calculated Baud Rate - Desired Baud Rate)
Error = ---------------------------------------------------------------------------------------------------------
-
error for the following conditions: Desired Baud Rate
FOSC = 16 MHz
9615 – 9600
Desired Baud Rate = 9600 = ----------------------------- = 0.16%
-
9600
BRGH = 0
SYNC = 0 It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register, causes the
BRG timer to be Reset (or cleared), this ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.

TABLE 12-1: BAUD RATE FORMULA
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate= FOSC/(16(X+1))
1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA
Legend: X = value in SPBRG (0 to 255)

TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR
Resets
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’.
Shaded cells are not used by the BRG.


PIC16F627A/628A/648A
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG
BAUD
value value value
RATE (K) KBAUD ERROR KBAUD ERROR KBAUD ERROR
(decimal) (decimal) (decimal)
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 NA — — NA — — 9.766 +1.73% 255
19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129
76.8 76.92 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32
96 96.15 +0.16% 51 95.24 -0.79% 41 96.15 +0.16% 25
300 294.1 -1.96 16 307.69 +2.56% 12 312.5 +4.17% 7
500 500 0 9 500 0 7 500 0 4
HIGH 5000 — 0 4000 — 0 2500 — 0
LOW 19.53 — 255 15.625 — 255 9.766 — 255

FOSC = 7.15909 MHz SPBRG 5.0688 MHz SPBRG 4 MHz SPBRG
BAUD
value value value
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 9.622 +0.23% 185 9.6 0 131 9.615 +0.16% 103
19.2 19.24 +0.23% 92 19.2 0 65 19.231 +0.16% 51
76.8 77.82 +1.32 22 79.2 +3.13% 15 75.923 +0.16% 12
96 94.20 -1.88 18 97.48 +1.54% 12 1000 +4.17% 9
300 298.3 -0.57 5 316.8 5.60% 3 NA — —
500 NA — — NA — — NA — —
HIGH 1789.8 — 0 1267 — 0 100 — 0
LOW 6.991 — 255 4.950 — 255 3.906 — 255

FOSC = 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG
BAUD
value value value
0.3 NA — — NA — — 0.303 +1.14% 26
1.2 NA — — 1.202 +0.16% 207 1.170 -2.48% 6
2.4 NA — — 2.404 +0.16% 103 NA — —
9.6 9.622 +0.23% 92 9.615 +0.16% 25 NA — —
19.2 19.04 -0.83% 46 19.24 +0.16% 12 NA — —
76.8 74.57 -2.90% 11 83.34 +8.51% 2 NA — —
96 99.43 +3.57% 8 NA — — NA — —
300 298.3 0.57% 2 NA — — NA — —
500 NA — — NA — — — —
HIGH 894.9 — 0 250 — 0 8.192 — 0
LOW 3.496 — 255 0.9766 — 255 0.032 — 255


PIC16F627A/628A/648A
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
value value value
0.3 NA — — NA — — NA — —
1.2 1.221 +1.73% 255 1.202 +0.16% 207 1.202 +0.16% 129
2.4 2.404 +0.16% 129 2.404 +0.16% 103 2.404 +0.16% 64
9.6 9.469 -1.36% 32 9.615 +0.16% 25 9.766 +1.73% 15
19.2 19.53 +1.73% 15 19.23 +0.16% 12 19.53 +1.73V 7
76.8 78.13 +1.73% 3 83.33 +8.51% 2 78.13 +1.73% 1
96 104.2 +8.51% 2 NA — — NA — —
300 312.5 +4.17% 0 NA — — NA — —
500 NA — — NA — — NA — —
HIGH 312.5 — 0 250 — 0 156.3 — 0
LOW 1.221 — 255 0.977 — 255 0.6104 — 255

BAUD
value value value
0.3 NA — — 0.31 +3.13% 255 0.3005 -0.17% 207
1.2 1.203 +0.23% 92 1.2 0 65 1.202 +1.67% 51
2.4 2.380 -0.83% 46 2.4 0 32 2.404 +1.67% 25
9.6 9.322 -2.90% 11 9.9 +3.13% 7 NA — —
19.2 18.64 -2.90% 5 19.8 +3.13% 3 NA — —
76.8 NA — — 79.2 +3.13% 0 NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 111.9 — 0 79.2 — 0 62.500 — 0
LOW 0.437 — 255 0.3094 — 255 3.906 — 255

BAUD
value value value
0.3 0.301 +0.23% 185 0.300 +0.16% 51 0.256 -14.67% 1
1.2 1.190 -0.83% 46 1.202 +0.16% 12 NA — —
2.4 2.432 +1.32% 22 2.232 -6.99% 6 NA — —
9.6 9.322 -2.90% 5 NA — — NA — —
19.2 18.64 -2.90% 2 NA — — NA — —
76.8 NA — — NA — — NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 55.93 — 0 15.63 — 0 0.512 — 0
LOW 0.2185 — 255 0.0610 — 255 0.0020 — 255


PIC16F627A/628A/648A
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
value value value
9600 9.615 +0.16% 129 9.615 +0.16% 103 9.615 +0.16% 64
19200 19.230 +0.16% 64 19.230 +0.16% 51 18.939 -1.36% 32
38400 37.878 -1.36% 32 38.461 +0.16% 25 39.062 +1.7% 15
57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10
115200 113.636 -1.36% 10 111.111 -3.55% 8 125 +8.51% 4
250000 250 0 4 250 0 3 NA — —
625000 625 0 1 NA — — 625 0 0
1250000 1250 0 0 NA — — NA — —

BAUD
value value value
9600 9.520 -0.83% 46 9598.485 0.016% 32 9615.385 0.160% 25
19200 19.454 +1.32% 22 18632.35 -2.956% 16 19230.77 0.160% 12
38400 37.286 -2.90% 11 39593.75 3.109% 7 35714.29 -6.994% 6
57600 55.930 -2.90% 7 52791.67 -8.348% 5 62500 8.507% 3
115200 111.860 -2.90% 3 105583.3 -8.348% 2 125000 8.507% 1
250000 NA — — 316750 26.700% 0 250000 0.000% 0
625000 NA — — NA — — NA — —
1250000 NA — — NA — — NA — —

BAUD
value value value
9600 9725.543 1.308% 22 8.928 -6.994% 6 NA NA NA
19200 18640.63 -2.913% 11 20833.3 8.507% 2 NA NA NA
38400 37281.25 -2.913% 5 31250 -18.620% 1 NA NA NA
57600 55921.88 -2.913% 3 62500 +8.507 0 NA NA NA
115200 111243.8 -2.913% 1 NA — — NA NA NA
250000 223687.5 -10.525% 0 NA — — NA NA NA
625000 NA — — NA — — NA NA NA
1250000 NA — — NA — — NA NA NA


PIC16F627A/628A/648A
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).

FIGURE 12-1: RX PIN SAMPLING SCHEME. BRGH = 0

RX Start bit
(RB1/RX/DT pin) bit 0

Baud CLK for all but Start bit
Baud CLK

x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Samples

FIGURE 12-2: RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
Start Bit bit 0 bit 1

Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1 2 3 4 1 2 3 4 1 2

Q2, Q4 CLK

Samples Samples Samples

FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
Start Bit bit 0

Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1 2 3 4

Q2, Q4 CLK

Samples


PIC16F627A/628A/648A
FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1

RX Start bit
(RB1/RX/DT pin) bit 0

Baud CLK

x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Samples

12.2 USART Asynchronous Mode software. It will Reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicated the
In this mode, the USART uses standard non-return-to- status of the TXREG register, another bit TRMT
zero (NRZ) format (one Start bit, eight or nine data bits (TXSTA<1>) shows the status of the TSR register.
and one Stop bit). The most common data format is Status bit TRMT is a read only bit which is set when the
8-bit. A dedicated 8-bit baud rate generator is used to TSR register is empty. No interrupt logic is tied to this
derive baud rate frequencies from the oscillator. The bit, so the user has to poll this bit in order to determine
USART transmits and receives the LSb first. The if the TSR register is empty.
USART’s transmitter and receiver are functionally
independent but use the same data format and baud Note 1: The TSR register is not mapped in data
rate. The baud rate generator produces a clock either memory so it is not available to the user.
x16 or x64 of the bit shift rate, depending on bit BRGH 2: Flag bit TXIF is set when enable bit TXEN
(TXSTA<2>). Parity is not supported by the hardware, is set.
but can be implemented in software (and stored as the
Transmission is enabled by setting enable bit TXEN
ninth data bit). Asynchronous mode is stopped during
(TXSTA<5>). The actual transmission will not occur
Sleep.
until the TXREG register has been loaded with data
Asynchronous mode is selected by clearing bit SYNC and the baud rate generator (BRG) has produced a
(TXSTA<4>). shift clock (Figure 12-5). The transmission can also be
The USART Asynchronous module consists of the started by first loading the TXREG register and then
following important elements: setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
• Baud Rate Generator
to the TXREG register will result in an immediate
• Sampling Circuit transfer to TSR resulting in an empty TXREG. A back-
• Asynchronous Transmitter to-back transfer is thus possible (Figure 12-7). Clearing
• Asynchronous Receiver enable bit TXEN during a transmission will cause the
transmission to be aborted and will Reset the
12.2.1 USART ASYNCHRONOUS transmitter. As a result the RB2/TX/CK pin will revert to
TRANSMITTER hi-impedance.
The USART transmitter block diagram is shown in In order to select 9-bit transmission, transmit bit TX9
Figure 12-5. The heart of the transmitter is the transmit (TXSTA<6>) should be set and the ninth bit should be
(serial) shift register (TSR). The shift register obtains its written to TX9D (TXSTA<0>). The ninth bit must be
data from the read/write transmit buffer, TXREG. The written before writing the 8-bit data to the TXREG
TXREG register is loaded with data in software. The register. This is because a data write to the TXREG
TSR register is not loaded until the Stop bit has been register can result in an immediate transfer of the data
transmitted from the previous load. As soon as the Stop to the TSR register (if the TSR is empty). In such a
bit is transmitted, the TSR is loaded with new data from case, an incorrect ninth data bit maybe loaded in the
the TXREG register (if available). Once the TXREG TSR register.
register transfers the data to the TSR register (occurs
in one TCY), the TXREG register is empty and flag bit
TXIF (PIR1<4>) is set. This interrupt can be enabled/
disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in


PIC16F627A/628A/648A
FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF TXREG register
TXIE
8
MSb LSb
(8) ² ² ² 0 Pin Buffer
and Control
TSR register RB2/TX/CK pin
Interrupt

TXEN Baud Rate CLK
TRMT SPEN
SPBRG

Baud Rate Generator TX9
TX9D

Follow these steps when setting up an Asynchronous
Transmission:
1. TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 "USART Baud
Rate Generator (BRG)")
3. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set transmit
bit TX9.
6. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Load data to the TXREG register (starts
transmission).

FIGURE 12-6: ASYNCHRONOUS TRANSMISSION

Write to TXREG
Word 1
BRG output
(shift clock)

RB2/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)

WORD 1
TRMT bit Transmit Shift Reg
(Transmit shift
reg. empty flag)


PIC16F627A/628A/648A
FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG
Word 1 Word 2
BRG output
(shift clock)
RB2/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0
TXIF bit
(interrupt reg. flag) WORD 1 WORD 2

TRMT bit WORD 1 WORD 2
(Transmit shift Transmit Shift Reg.
reg. empty flag) Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.
.

TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
POR
Resets
19h TXREG USART Transmit data register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’.
Shaded cells are not used for Asynchronous Transmission.


PIC16F627A/628A/648A
12.2.2 USART ASYNCHRONOUS double buffered register, (i.e., it is a two deep FIFO). It
RECEIVER is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
The receiver block diagram is shown in Figure 12-8. shifting to the RSR register. On the detection of the
The data is received on the RB1/RX/DT pin and drives Stop bit of the third byte, if the RCREG register is still
the data recovery block. The data recovery block is full then overrun error bit OERR (RCSTA<1>) will be
actually a high-speed shifter operating at x16 times the set. The word in the RSR will be lost. The RCREG
baud rate, whereas the main receive serial shifter register can be read twice to retrieve the two bytes in
operates at the bit rate or at FOSC. the FIFO. Overrun bit OERR has to be cleared in soft-
When Asynchronous mode is selected, reception is ware. This is done by resetting the receive logic (CREN
enabled by setting bit CREN (RCSTA<4>). is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
The heart of the receiver is the receive (serial) shift
ited, so it is essential to clear error bit OERR if it is set.
register (RSR). After sampling the Stop bit, the
Framing error bit FERR (RCSTA<2>) is set if a Stop bit
received data in the RSR is transferred to the RCREG
is detected as clear. Bit FERR and the 9th receive bit
register (if it is empty). If the transfer is complete, flag
are buffered the same way as the receive data. Read-
bit RCIF (PIR1<5>) is set. The actual interrupt can be
ing the RCREG, will load bits RX9D and FERR with
enabled/disabled by setting/clearing enable bit RCIE
new values, therefore it is essential for the user to read
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
the RCSTA register before reading RCREG register in
cleared by the hardware. It is cleared when the RCREG
order not to lose the old FERR and RX9D information.
register has been read and is empty. The RCREG is a

FIGURE 12-8: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
OERR FERR
CREN

SPBRG
³ 64 MSb RSR register LSb
or
³ 16 0 Start
Baud Rate Generator Stop (8) 7 ² ² ² 1

RB1/RX/DT
Pin Buffer Data
and Control Recovery RX9

8

SPEN

RX9 Enable
ADEN Load of

RX9 Receive
Buffer
ADEN
RSR<8> 8

RX9D RCREG register
FIFO
RX9D RCREG register

8

Interrupt RCIF
Data Bus
RCIE


PIC16F627A/628A/648A
FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
RB1/RX/DT (PIN) START START
BIT BIT0 BIT1 BIT8 STOP BIT BIT0 BIT8 STOP
BIT BIT
RCV SHIFT REG
RCV BUFFER REG
BIT8 = 0, DATA BYTE BIT8 = 1, ADDRESS BYTE WORD 1
RCREG
READ RCV
BUFFER REG
RCREG

RCIF
(INTERRUPT FLAG)
‘1’ ‘1’
ADEN = 1
(ADDRESS MATCH
ENABLE)

Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.

FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
BIT BIT
RCV SHIFT
REG
RCV BUFFER REG
BIT8 = 1, ADDRESS BYTE WORD 1 BIT8 = 0, DATA BYTE
RCREG
READ RCV
BUFFER REG
RCREG

RCIF
(INTERRUPT FLAG)
‘1’ ‘1’
ADEN = 1
(ADDRESS MATCH
ENABLE)

Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.

FIGURE 12-11: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
BIT BIT
RCV SHIFT
REG
RCV BUFFER REG
BIT8 = 1, ADDRESS BYTE WORD 1 BIT8 = 0, DATA BYTE WORD 2
RCREG RCREG
READ RCV
BUFFER REG
RCREG

RCIF
(INTERRUPT FLAG)

ADEN
(ADDRESS MATCH
ENABLE)

Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.


PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
set bit BRGH. (Section 12.1 "USART Baud
Rate Generator (BRG)").
3. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit CREN.

TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
POR
Resets
18h RCSTA SPEN RX9 SREN CREN ADENFERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive data register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.


PIC16F627A/628A/648A
12.3 USART Address Detect Function The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = ‘1’). When ADEN is
12.3.1 USART 9-BIT RECEIVER WITH disabled (= ‘0’), all data bytes are received and the 9th
ADDRESS DETECT bit can be used as the parity bit.

When the RX9 bit is set in the RCSTA register, 9 bits The receive block diagram is shown in Figure 12-8.
are received and the ninth bit is placed in the RX9D bit Reception is enabled by setting bit CREN
of the RCSTA register. The USART module has a (RCSTA<4>).
special provision for multi-processor communication.
Multiprocessor communication is enabled by setting 12.3.1.1 Setting up 9-bit mode with Address
the ADEN bit (RCSTA<3>) along with the RX9 bit. The Detect
port is now programmed such that when the last bit is Follow these steps when setting up Asynchronous
received, the contents of the receive shift register Reception with Address Detect Enabled:
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the 1. TRISB<1> bit needs to be set and TRISB<2> bit
receive interrupt is set if and only if RSR<8> = 1. This cleared in order to configure pins RB2/TX/CK
feature can be used in a multi-processor system as and RB1/RX/DT as the Universal Synchronous
follows: Asynchronous Receiver Transmitter pins.
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
set bit BRGH.
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a ‘1’ 3. Enable asynchronous communication by setting
(instead of a ‘0’ for a data byte). If the ADEN and RX9 or clearing bit SYNC and setting bit SPEN.
bits are set in the slave’s RCSTA register, enabling 4. If interrupts are desired, then set enable bit
multiprocessor communication, all data bytes will be RCIE.
ignored. However, if the ninth received bit is equal to a 5. Set bit RX9 to enable 9-bit reception.
‘1’, indicating that the received byte is an address, the 6. Set ADEN to enable address detect.
slave will be interrupted and the contents of the RSR 7. Enable the reception by setting enable bit CREN
register will be transferred into the receive buffer. This or SREN.
allows the slave to be interrupted only by addresses, so
8. Flag bit RCIF will be set when reception is
that the slave can examine the received byte to see if it
complete, and an interrupt will be generated if
is being addressed. The addressed slave will then clear
enable bit RCIE was set.
its ADEN bit and prepare to receive data bytes from the
master. 9. Read the 8-bit received data by reading the
RCREG register to determine if the device is
When ADEN is enabled (= ‘1’), all data bytes are being addressed.
ignored. Following the Stop bit, the data will not be
loaded into the receive buffer, and no interrupt will
enable bit CREN if it was already set.
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost. 11. If the device has been addressed (RSR<8> = ‘1’
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.

TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
POR
Resets
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.


PIC16F627A/628A/648A
12.4 USART Synchronous Master Clearing enable bit TXEN, during a transmission, will
Mode cause the transmission to be aborted and will Reset the
transmitter. The DT and CK pins will revert to hi-imped-
In Synchronous Master mode, the data is transmitted in ance. If either bit CREN or bit SREN is set, during a
a half-duplex manner, (i.e., transmission and reception transmission, the transmission is aborted and the DT
do not occur at the same time). When transmitting data, pin reverts to a hi-impedance state (for a reception).
the reception is inhibited and vice versa. Synchronous The CK pin will remain an output if bit CSRC is set
mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic however is not
addition enable bit SPEN (RCSTA<7>) is set in order to Reset although it is disconnected from the pins. In
configure the RB2/TX/CK and RB1/RX/DT I/O pins to order to Reset the transmitter, the user has to clear bit
CK (clock) and DT (data) lines respectively. The Master TXEN. If bit SREN is set (to interrupt an on-going
mode indicates that the processor transmits the master transmission and receive a single word), then after the
clock on the CK line. The Master mode is entered by single word is received, bit SREN will be cleared and
setting bit CSRC (TXSTA<7>). the serial port will revert back to transmitting since bit
TXEN is still set. The DT line will immediately switch
12.4.1 USART SYNCHRONOUS MASTER from hi-impedance Receive mode to transmit and start
TRANSMISSION driving. To avoid this, bit TXEN should be cleared.
The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9
Figure 12-5. The heart of the transmitter is the transmit (TXSTA<6>) bit should be set and the ninth bit should
(serial) shift register (TSR). The shift register obtains its be written to bit TX9D (TXSTA<0>). The ninth bit must
data from the read/write transmit buffer register be written before writing the 8-bit data to the TXREG
TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can
software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR
bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and
soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D,
with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded.
TXREG register transfers the data to the TSR register Follow these steps when setting up a Synchronous
(occurs in one Tcycle), the TXREG is empty and inter- Master Transmission:
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE 1. TRISB<1> bit needs to be set and TRISB<2> bit
(PIE1<4>). Flag bit TXIF will be set regardless of the cleared in order to configure pins RB2/TX/CK
state of enable bit TXIE and cannot be cleared in soft- and RB1/RX/DT as the Universal Synchronous
ware. It will Reset only when new data is loaded into the Asynchronous Receiver Transmitter pins.
TXREG register. While flag bit TXIF indicates the status 2. Initialize the SPBRG register for the appropriate
of the TXREG register, another bit TRMT (TXSTA<1>) baud rate (Section 12.1 "USART Baud Rate
shows the status of the TSR register. TRMT is a read Generator (BRG)").
only bit which is set when the TSR is empty. No inter- 3. Enable the synchronous master serial port by
rupt logic is tied to this bit, so the user has to poll this setting bits SYNC, SPEN, and CSRC.
bit in order to determine if the TSR register is empty. 4. If interrupts are desired, then set enable bit
The TSR is not mapped in data memory so it is not TXIE.
available to the user. 5. If 9-bit transmission is desired, then set bit TX9.
Transmission is enabled by setting enable bit TXEN 6. Enable the transmission by setting bit TXEN.
(TXSTA<5>). The actual transmission will not occur 7. If 9-bit transmission is selected, the ninth bit
until the TXREG register has been loaded with data. should be loaded in bit TX9D.
The first data bit will be shifted out on the next available
8. Start transmission by loading data to the TXREG
rising edge of the clock on the CK line. Data out is
register.
stable around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started
by first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is kept in Reset
when bits TXEN, CREN, and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back
transfers are possible.


PIC16F627A/628A/648A
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR other Resets
19h TXREG USART Transmit data register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

FIGURE 12-12: SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q1Q2Q3Q4

RB1/RX/DT PIN BIT 0 BIT 1 BIT 2 BIT 7 BIT 0 BIT 1 BIT 7
WORD 1 WORD 2
RB2/TX/CK PIN
WRITE TO
TXREG REG
WRITE WORD1 WRITE WORD2
TXIF BIT
(INTERRUPT FLAG)

TRMT
TRMT BIT

‘1’ ‘1’
TXEN BIT

Note: Sync Master Mode; SPBRG = ‘0’. Continuous transmission of two 8-bit words.

FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RB1/RX/DT PIN BIT0 BIT1 BIT2 BIT6 BIT7

RB2/TX/CK PIN

WRITE TO
TXREG REG

TXIF BIT

TRMT BIT

TXEN BIT


PIC16F627A/628A/648A
12.4.2 USART SYNCHRONOUS MASTER with a new value, therefore it is essential for the user to
RECEPTION read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN Follow these steps when setting up a Synchronous
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is Master Reception:
sampled on the RB1/RX/DT pin on the falling edge of 1. TRISB<1> bit needs to be set and TRISB<2> bit
the clock. If enable bit SREN is set, then only a single cleared in order to configure pins RB2/TX/CK
word is received. If enable bit CREN is set, the recep- and RB1/RX/DT as the Universal Synchronous
tion is continuous until CREN is cleared. If both bits are Asynchronous Receiver Transmitter pins.
set then CREN takes precedence. After clocking the 2. Initialize the SPBRG register for the appropriate
last bit, the received data in the Receive Shift Register baud rate. (Section 12.1 "USART Baud Rate
(RSR) is transferred to the RCREG register (if it is Generator (BRG)").
empty). When the transfer is complete, interrupt flag bit 3. Enable the synchronous master serial port by
RCIF (PIR1<5>) is set. The actual interrupt can be setting bits SYNC, SPEN, and CSRC.
enabled/disabled by setting/clearing enable bit RCIE
4. Ensure bits CREN and SREN are clear.
(PIE1<5>). Flag bit RCIF is a read only bit which is
Reset by the hardware. In this case it is Reset when the 5. If interrupts are desired, then set enable bit
RCREG register has been read and is empty. The RCIE.
RCREG is a double buffered register, (i.e., it is a two 6. If 9-bit reception is desired, then set bit RX9.
deep FIFO). It is possible for two bytes of data to be 7. If a single reception is required, set bit SREN.
received and transferred to the RCREG FIFO and a For continuous reception set bit CREN.
third byte to begin shifting into the RSR register. On the 8. Interrupt flag bit RCIF will be set when reception
clocking of the last bit of the third byte, if the RCREG is complete and an interrupt will be generated if
register is still full then overrun error bit OERR enable bit RCIE was set.
(RCSTA<1>) is set. The word in the RSR will be lost.
9. Read the RCSTA register to get the ninth bit (if
The RCREG register can be read twice to retrieve the
enabled) and determine if any error occurred
two bytes in the FIFO. Bit OERR has to be cleared in
during reception.
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so 10. Read the 8-bit received data by reading the
it is essential to clear bit OERR if it is set. The 9th RCREG register.
receive bit is buffered the same way as the receive 11. If any error occurred, clear the error by clearing
data. Reading the RCREG register, will load bit RX9D bit CREN.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on: Value on all
POR other Resets
8Ch PIE1 EEPIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 0000 -000 -000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.


PIC16F627A/628A/648A
FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4

RB1/RX/DT PIN BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

RB2/TX/CK PIN

WRITE TO
BIT SREN

SREN BIT
CREN BIT ‘0’ ‘0’

RCIF BIT
(INTERRUPT)
READ
RXREG

Note: Timing diagram demonstrates Sync Master Mode with bit SREN = ‘1’ and bit BRG = ‘0’.

12.5 USART Synchronous Slave Mode Follow these steps when setting up a Synchronous
Slave Transmission:
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at 1. TRISB<1> bit needs to be set and TRISB<2> bit
the RB2/TX/CK pin (instead of being supplied internally cleared in order to configure pins RB2/TX/CK
in Master mode). This allows the device to transfer or and RB1/RX/DT as the Universal Synchronous
receive data while in Sleep mode. Slave mode is Asynchronous Receiver Transmitter pins.
entered by clearing bit CSRC (TXSTA<7>). 2. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
12.5.1 USART SYNCHRONOUS SLAVE CSRC.
TRANSMIT 3. Clear bits CREN and SREN.
The operation of the synchronous Master and Slave 4. If interrupts are desired, then set enable bit
modes are identical except in the case of the Sleep TXIE.
mode. 5. If 9-bit transmission is desired, then set bit TX9.
If two words are written to the TXREG and then the 6. Enable the transmission by setting enable bit
SLEEP instruction is executed, the following will occur: TXEN.
7. If 9-bit transmission is selected, the ninth bit
a) The first word will immediately transfer to the
should be loaded in bit TX9D.
TSR register and transmit.
8. Start transmission by loading data to the TXREG
b) The second word will remain in TXREG register.
register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).


PIC16F627A/628A/648A
12.5.2 USART SYNCHRONOUS SLAVE 2. Enable the synchronous master serial port by
RECEPTION setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Mlave
modes is identical except in the case of the Sleep
RCIE.
mode. Also, bit SREN is a don't care in Slave mode.
4. If 9-bit reception is desired, then set bit RX9.
If receive is enabled, by setting bit CREN, prior to the
5. To enable reception, set enable bit CREN.
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR 6. Flag bit RCIF will be set when reception is
register will transfer the data to the RCREG register complete and an interrupt will be generated, if
and if enable bit RCIE bit is set, the interrupt generated enable bit RCIE was set.
will wake the chip from Sleep. If the global interrupt is 7. Read the RCSTA register to get the ninth bit (if
enabled, the program will branch to the interrupt vector enabled) and determine if any error occurred
(0004h). during reception.
Follow these steps when setting up a Synchronous 8. Read the 8-bit received data by reading the
Slave Reception: RCREG register.
bit CREN.

TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
POR other Resets
18hRCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
19hTXREG USART Transmit data register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
POR other Resets
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
13.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
The EEPROM data memory is readable and writable writes the new data (erase before write). The EEPROM
during normal operation (full VDD range). This memory data memory is rated for high erase/write cycles. The
is not directly mapped in the register file space. Instead write time is controlled by an on-chip timer. The write-
it is indirectly addressed through the Special Function time will vary with voltage and temperature as well as
Registers (SFRs). There are four SFRs used to read from chip to chip. Please refer to AC specifications for
and write this memory. These registers are: exact limits.
• EECON1 When the device is code protected, the CPU can
• EECON2 (Not a physically implemented register) continue to read and write the data EEPROM memory.
• EEDATA A device programmer can no longer access
• EEADR this memory.

EEDATA holds the 8-bit data for read/write, and Additional information on the data EEPROM is
EEADR holds the address of the EEPROM location available in the PICmicro® Mid-Range Reference
being accessed. PIC16F627A/628A devices have 128 Manual (DS33023).
bytes of data EEPROM with an address range from 0h
to 7Fh. PIC16F648A device has 256 bytes of data
EEPROM with an address range from 0h to FFh.

REGISTER 13-1: EEDATA REGISTER (ADDRESS: 9Ah)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0

bit 7-0 EEDATn: Byte value to write to or read from Data EEPROM memory location.

Legend:

REGISTER 13-2: EEADR REGISTER (ADDRESS: 9Bh)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EADR7 EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit 7 bit 0

bit 7 PIC16F627A/628A - Unimplemented Address: Must be set to ‘0’
PIC16F648A - EEADR: Set to ‘1’ specifies top 128 locations (128-256) of EEPROM Read/Write
Operation
bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation

Legend:


PIC16F627A/628A/648A
13.1 EEADR Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
The PIC16F648A EEADR register addresses 256 software. They are cleared in hardware at completion
bytes of data EEPROM. All eight bits in the register of the read or write operation. The inability to clear the
(EEADR<7:0>) are required. WR bit in software prevents the accidental, premature
The PIC16F627A/628A EEADR register addresses termination of a write operation.
only the first 128 bytes of data EEPROM so only seven The WREN bit, when set, will allow a write operation.
of the eight bits in the register (EEADR<6:0>) are On power-up, the WREN bit is clear. The WRERR bit is
required. The upper bit is address decoded. This set when a write operation is interrupted by a MCLR
means that this bit should always be '0' to ensure that Reset or a WDT Time out Reset during normal opera-
the address is in the 128 byte memory space. tion. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
13.2 EECON1 AND EECON2 data and address will be unchanged in the EEDATA
REGISTERS and EEADR registers.
EECON1 is the control register with four low order bits Interrupt flag bit EEIF in the PIR1 register is set when
physically implemented. The upper-four bits are non- write is complete. This bit must be cleared in software.
existent and read as '0's. EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the Data EEPROM write sequence.

REGISTER 13-3: EECON1 REGISTER (ADDRESS: 9Ch) DEVICES
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
— — — — WRERR WREN WR RD
bit 7 bit 0

bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during nor-
mal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0 = Does not initiate an EEPROM read

Legend:


PIC16F627A/628A/648A
13.3 READING THE EEPROM DATA At the completion of the write cycle, the WR bit is
MEMORY cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
To read a data memory location, the user must write the enable this interrupt or poll this bit. The EEIF bit in the
address to the EEADR register and then set control bit PIR1 registers must be cleared by software.
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be 13.5 WRITE VERIFY
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user Depending on the application, good programming
(during a write operation). practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
EXAMPLE 13-1: DATA EEPROM READ
applications where an EEPROM bit will be stressed
near the specification limit.
MOVLW CONFIG_ADDR ;
MOVWF EEADR ;Address to read
BSF EECON1, RD ;EE Read EXAMPLE 13-3: WRITE VERIFY
MOVF EEDATA, W ;W = EEDATA BSF STATUS, RP0 ;Bank 1
BCF STATUS, RP0 ;Bank 0 MOVF EEDATA, W
BSF EECON1, RD ;Read the
;value written
13.4 WRITING TO THE EEPROM DATA
;
MEMORY ;Is the value written (in W reg) and
;read (in EEDATA) the same?
To write an EEPROM data location, the user must first
;
write the address to the EEADR register and the data SUBWF EEDATA, W ;
to the EEDATA register. Then the user must follow a BTFSS STATUS, Z ;Is difference 0?
specific sequence to initiate the write for each byte. GOTO WRITE_ERR ;NO, Write error
: ;YES, Good write
EXAMPLE 13-2: DATA EEPROM WRITE : ;Continue program
BSF EECON1, WREN ;Enable write
BCF INTCON, GIE ;Disable INTs. 13.6 PROTECTION AGAINST
MOVLW 55h ; SPURIOUS WRITE
Sequence
Required

MOVWF EECON2 ;Write 55h
MOVLW AAh ; There are conditions when the device may not want to
MOVWF EECON2 ;Write AAh write to the data EEPROM memory. To protect against
BSF EECON1,WR ;Set WR bit spurious EEPROM writes, various mechanisms have
;begin write been built in. On power-up, WREN is cleared. Also
BSF INTCON, GIE ;Enable INTs. when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to The write initiate sequence, and the WREN bit together
EECON2, then set WR bit) for each byte. We strongly help prevent an accidental write during brown-out,
recommend that interrupts be disabled during this power glitch, or software malfunction.
code segment. A cycle count is executed during the
required sequence. Any number what is not equal to
the required cycles to execute the required sequence
will cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.


PIC16F627A/628A/648A
13.7 Using the Data EEPROM For this reason, variables that change infrequently
(such as constants, IDs, calibration, etc.) should be
The data EEPROM is a high endurance, byte address- stored in Flash program memory.
able array that has been optimized for the storage of
frequently changing information (e.g., program A simple data EEPROM refresh routine is shown in
variables or other data that are updated often). Example 13-4.
Frequently changing values will typically be updated Note: If data EEPROM is only used to store
more often than specification D124. If this is not the constants and/or data that changes rarely,
case, an array refresh must be performed. an array refresh is likely not required. See
specification D124.

EXAMPLE 13-4: DATA EEPROM REFRESH ROUTINE
BANKSEL 0X80 ;select Bank1
CLRF EEADR ;start at address 0
BCF INTCON, GIE ;disable interrupts
BSF EECON1, WREN ;enable EE writes
Loop
BSF EECON1, RD ;retrieve data into EEDATA
MOVLW 0x55 ;first step of ...
MOVWF EECON2 ;... required sequence
MOVLW 0xAA ;second step of ...
MOVWF EECON2 ;... required sequence
BSF EECON1, WR ;start write sequence
BTFSC EECON1, WR ;wait for write complete
GOTO $ - 1

#IFDEF __16F648A ;256 bytes in 16F648A

INCFSZ EEADR, f ;test for end of memory
#ELSE ;128 bytes in 16F627A/628A
INCF EEADR, f ;next address
BTFSS EEADR, 7 ;test for end of memory
#ENDIF ;end of conditional assembly

GOTO Loop ;repeat for all locations

BCF EECON1, WREN ;disable EE writes
BSF INTCON, GIE ;enable interrupts (optional)

13.8 DATA EEPROM OPERATION
DURING CODE PROTECT
When the device is code protected, the CPU is able to
read and write data to the Data EEPROM.

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other
Reset Resets
9Ah EEDATA EEPROM data register xxxx xxxx uuuu uuuu
9Bh EEADR EEPROM address register xxxx xxxx uuuu uuuu
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000
9Dh EECON2(1) EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register.


PIC16F627A/628A/648A
14.0 SPECIAL FEATURES OF THE 14.1 Configuration Bits
CPU The configuration bits can be programmed (read as ‘0’)
Special circuits to deal with the needs of real-time or left unprogrammed (read as ‘1’) to select various
applications are what sets a microcontroller apart from device configurations. These bits are mapped in
other processors. The PIC16F627A/628A/648A family program memory location 2007h.
has a host of such features intended to maximize The user will note that address 2007h is beyond
system reliability, minimize cost through elimination of the user program memory space. In fact, it belongs
external components, provide power saving Operating to the special configuration memory space (2000h –
modes and offer code protection. 3FFFh), which can be accessed only during
These are: programming. See Programming Specification
(DS41196) for additional information.
1. OSC selection
2. Reset
3. Power-on Reset (POR)
4. Power-up Timer (PWRT)
5. Oscillator Start-Up Timer (OST)
6. Brown-out Reset (BOR)
7. Interrupts
8. Watchdog Timer (WDT)
9. Sleep
10. Code protection
11. ID Locations
12. In-Circuit Serial Programming™ (ICSP™)
The PIC16F627A/628A/648A has a Watchdog Timer
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in Reset while the
power supply stabilizes. There is also circuitry to Reset
the device if a Brown-out occurs. With these three
functions on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.


PIC16F627A/628A/648A
REGISTER 14-1: CONFIGURATION WORD

CP — — — — CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0

bit 13: CP: Flash Program Memory Code Protection bit(2)
(PIC16F648A)
1 = Code protection off
0 = 0000h to 0FFFh code protected
(PIC16F628A)
0 = 0000h to 07FFh code protected
(PIC16F627A)
0 = 0000h to 03FFh code protected

bit 12-9: Unimplemented: Read as ‘0’

bit 8: CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code protected

bit 7: LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming

bit 6: BOREN: Brown-out Reset Enable bit (1)
1 = BOR Reset enabled
0 = BOR Reset disabled

bit 5: MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to VDD

bit 3: PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled

bit 2: WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled

bit 4, 1-0: FOSC2:FOSC0: Oscillator Selection bits(4)
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it did in the PIC16F627/628.
2: The code protection scheme has changed from the code protection scheme used in the PIC16F627/628. The entire Flash program mem-
ory needs to be bulk erased to set the CP bit, turning the code protection off. See Programming Specification DS41196 for details.
3: The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See Programming Specification
DS41196 for details.
4: When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.

Legend:
-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown


PIC16F627A/628A/648A
14.2 Oscillator Configurations TABLE 14-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
14.2.1 OSCILLATOR TYPES Mode Freq OSC1(C1) OSC2(C2)
The PIC16F627A/628A/648A can be operated in eight XT 455 kHz 22 - 100 pF 22 - 100 pF
different oscillator options. The user can program three 2.0 MHz 15 - 68 pF 15 - 68 pF
4.0 MHz 15 - 68 pF 15 - 68 pF
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes: HS 8.0 MHz 10 - 68 pF 10 - 68 pF
16.0 MHz 10 - 22 pF 10 - 22 pF
• LP Low Power Crystal Note: Higher capacitance increases the stability of the
• XT Crystal/Resonator oscillator but also increases the start-up time. These
values are for design guidance only. Since each
• HS High Speed Crystal/Resonator resonator has its own characteristics, the user should
• RC External Resistor/Capacitor (2 modes) consult the resonator manufacturer for appropriate
values of external components.
• INTOSC Internal Precision Oscillator (2 modes)
• EC External Clock In TABLE 14-2: CAPACITOR SELECTION FOR
14.2.2 CRYSTAL OSCILLATOR / CERAMIC CRYSTAL OSCILLATOR
RESONATORS Mode Freq OSC1(C1) OSC2(C2)

LP 32 kHz 15 - 30 pF 15 - 30 pF
In XT, LP or HS modes a crystal or ceramic resonator 200 kHz 0 - 15 pF 0 - 15 pF
is connected to the OSC1 and OSC2 pins to establish
XT 100 kHz 68 - 150 pF 150 - 200 pF
oscillation (Figure 14-1). The PIC16F627A/628A/648A 2 MHz 15 - 30 pF 15 - 30 pF
oscillator design requires the use of a parallel cut 4 MHz 15 - 30 pF 15 - 30 pF
crystal. Use of a series cut crystal may give a frequency HS 8 MHz 15 - 30 pF 15 - 30 pF
out of the crystal manufacturers specifications. When in 10 MHz 15 - 30 pF 15 - 30 pF
20 MHz 15 - 30 pF 15 - 30 pF
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1 pin (Figure 14-4). Note: Higher capacitance increases the stability of the
oscillator but also increases the start-up time. These
values are for design guidance only. A series resistor
FIGURE 14-1: CRYSTAL OPERATION (RS) may be required in HS mode as well as XT mode
to avoid overdriving crystals with low drive level speci-
(OR CERAMIC fication. Since each crystal has its own characteristics,
RESONATOR) (HS, XT OR the user should consult the crystal manufacturer for
appropriate values of external components.
LP OSC
CONFIGURATION) 14.2.3 EXTERNAL CRYSTAL OSCILLATOR
OSC1
CIRCUIT
C1 Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
XTAL Sleep Prepackaged oscillators provide a wide operating
RF
OSC2 range and better stability. A well-designed crystal
RS(1) FOSC oscillator will provide good performance with TTL
C2 gates. Two types of crystal oscillator circuits can be
PIC16F627A/628A/648A used; one with series resonance, or one with parallel
Note 1: A series resistor may be required for AT strip cut resonance.
crystals.
2: See Table 14-1 and Table 14-2 for recommended Figure 14-2 shows implementation of a parallel reso-
values of C1 and C2. nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.


PIC16F627A/628A/648A
FIGURE 14-2: EXTERNAL PARALLEL FIGURE 14-4: EXTERNAL CLOCK INPUT
RESONANT CRYSTAL OPERATION (EC, HS, XT
OSCILLATOR CIRCUIT OR LP OSC
CONFIGURATION)
+5V
TO OTHER
DEVICES Clock From RA7/OSC1/CLKIN
10K ext. system
4.7K 74AS04 PIC16F627A/628A/648A PIC16F627A/628A/648A
74AS04 CLKIN
RA6 RA6/OSC2/CLKOUT

10K
14.2.6 RC OSCILLATOR
XTAL
For applications where precise timing is not a require-
10K ment, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
C1 C2 dependent upon a number of variables. The RC
oscillator frequency is a function of:
Figure 14-3 shows a series resonant oscillator circuit. • Supply voltage
This circuit is also designed to use the fundamental • Resistor (REXT) and capacitor (CEXT) values
frequency of the crystal. The inverter performs a 180° • Operating temperature.
phase shift in a series resonant oscillator circuit. The
The oscillator frequency will vary from unit to unit due
330 kΩ resistors provide the negative feedback to bias
to normal process parameter variation. The difference
the inverters in their linear region.
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
FIGURE 14-3: EXTERNAL SERIES CEXT values. The user also needs to account for the
RESONANT CRYSTAL tolerance of the external R and C components.
OSCILLATOR CIRCUIT Figure 14-5 shows how the R/C combination is
connected.
TO OTHER
330 KΩ 330 KΩ DEVICES FIGURE 14-5: RC OSCILLATOR MODE
74AS04 74AS04 74AS04

CLKIN VDD
0.1 PF PIC16F627A/628A/648A
PIC16F627A/
628A/648A REXT
RA7/OSC1/ Internal
CLKIN Clock
XTAL
CEXT
VSS
14.2.4 PRECISION INTERNAL 4 MHZ
OSCILLATOR FOSC/4
RA6/OSC2/CLKOUT
The internal precision oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5 V and 25°C. See
The RC Oscillator mode has two options that control
Section 17.0 "Electrical Specifications", for informa-
the unused OSC2 pin. The first allows it to be used as
tion on variation over voltage and temperature.
a general purpose I/O port. The other configures the
14.2.5 EXTERNAL CLOCK IN pin as an output providing the Fosc signal (internal
clock divided by 4) for test or external synchronization
For applications where a clock is already available purposes.
elsewhere, users may directly drive the PIC16F627A/
628A/648A provided that this external clock source 14.2.7 CLKOUT
meets the AC/DC timing requirements listed in
The PIC16F627A/628A/648A can be configured to
Section 17.6 "Timing Diagrams and Specifica-
provide a clock out signal by programming the configu-
tions". Figure 14-4 below shows how an external clock
ration word. The oscillator frequency, divided by 4 can
circuit should be configured.
be used for test purposes or to synchronize other logic.


PIC16F627A/628A/648A
14.2.8 SPECIAL FEATURE: DUAL SPEED 14.3 Reset
OSCILLATOR MODES
The PIC16F627A/628A/648A differentiates between
A software programmable dual speed Oscillator mode various kinds of Reset:
is provided when the PIC16F627A/628A/648A is a) Power-on Reset (POR)
configured in the INTOSC Oscillator mode. This feature
b) MCLR Reset during normal operation
allows users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz nominal in the INTOSC c) MCLR Reset during Sleep
mode. Applications that require low current power d) WDT Reset (normal operation)
savings, but cannot tolerate putting the part into Sleep, e) WDT wake-up (Sleep)
may use this mode. f) Brown-out Reset (BOR)
There is a time delay associated with the transition Some registers are not affected in any Reset condition;
between Fast and Slow oscillator speeds. This their status is unknown on POR and unchanged in any
Oscillator Speed Transition delay consists of two other Reset. Most other registers are reset to a “Reset
existing clock pulses and eight new speed clock state” on Power-on Reset, Brown-out Reset, MCLR
pulses. During this Clock Speed Transition Delay the Reset, WDT Reset and MCLR Reset during Sleep.
System Clock is halted causing the processor to be They are not affected by a WDT wake-up, since this is
frozen in time. During this delay the Program Counter viewed as the resumption of normal operation. TO and
and the Clock Out stop. PD bits are set or cleared differently in different Reset
The OSCF bit in the PCON register is used to control Dual situations as indicated in Table 14-4. These bits are
Speed mode. See Section 4.2.2.6 "PCON Register", used in software to determine the nature of the Reset.
Register 4-6. See Table 14-7 for a full description of Reset states of
all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.

FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset

Schmitt Trigger Input
MCLR/
VPP Pin Sleep
WDT WDT
Module Time out
Reset
VDD rise
detect Power-on Reset
VDD
Brown-out
detect Reset S Q
BOREN

OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R Q
OSC1/
CLKIN
Pin
PWRT
On-chip(1)
OSC 10-bit Ripple-counter

Enable PWRT See Table 14-3 for time out situations.

Enable OST
Note 1: This is a separate oscillator from the INTOSC/RC oscillator.


PIC16F627A/628A/648A
14.4 Power-on Reset (POR), Power-up The Power-Up Time delay will vary from chip to chip
Timer (PWRT), Oscillator Start-up and due to VDD, temperature and process variation.
See DC parameters Table 17-7 for details.
Timer (OST) and Brown-out Reset
(BOR) 14.4.3 OSCILLATOR START-UP TIMER
(OST)
14.4.1 POWER-ON RESET (POR)
The OST provides a 1024 oscillator cycle (from OSC1
The on-chip POR circuit holds the chip in Reset until input) delay after the PWRT delay is over. Program
VDD has reached a high enough level for proper execution will not start until the OST time out is
operation. To take advantage of the POR, just tie the complete. This ensures that the crystal oscillator or
MCLR pin through a resistor to VDD. This will eliminate resonator has started and stabilized.
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is The OST time out is invoked only for XT, LP and HS
required. See Electrical Specifications for details. modes and only on Power-on Reset or wake-up from
Sleep. See Table 17-7.
The POR circuit does not produce an internal Reset
when VDD declines. 14.4.4 BROWN-OUT RESET (BOR)
When the device starts normal operation (exits the
The PIC16F627A/628A/648A have on-chip BOR
Reset condition), device operating parameters
circuitry. A configuration bit, BOREN, can disable (if
(voltage, frequency, temperature, etc.) must be met to
clear/programmed) or enable (if set) the BOR Reset
ensure operation. If these conditions are not met, the
circuitry. If VDD falls below VBOR for longer than TBOR,
device must be held in Reset until the operating
the brown-out situation will Reset the chip. A Reset is
conditions are met.
not guaranteed to occur if VDD falls below VBOR for
For additional information, refer to Application Note shorter than TBOR. VBOR and TBOR are defined in
AN607, “Power-up Trouble Shooting”. Table 17-2 and Table 17-7, respectively.
On any Reset (Power-on, Brown-out, Watchdog, etc.),
14.4.2 POWER-UP TIMER (PWRT)
the chip will remain in Reset until VDD rises above
The PWRT provides a fixed 72 ms (nominal) time out BVDD (see Figure 14-7). The Power-up Timer will now
on power-up (POR) or if enabled from a Brown-out be invoked, if enabled, and will keep the chip in Reset
Reset. The PWRT operates on an internal RC oscilla- an additional 72 ms.
tor. The chip is kept in Reset as long as PWRT is active. If VDD drops below VBOR while the Power-up Timer is
The PWRT delay allows the VDD to rise to an accept- running, the chip will go back into a Brown-out Reset
able level. A configuration bit, PWRTE can disable (if and the Power-up Timer will be re-initialized. Once VDD
set) or enable (if cleared or programmed) the PWRT. It rises above VBOR, the Power-Up Timer will execute a
is recommended that the PWRT be enabled when 72 ms Reset. Figure 14-7 shows typical Brown-out
Brown-out Reset is enabled. situations.

FIGURE 14-7: BROWN-OUT SITUATIONS WITH PWRT ENABLED
VDD
VBOR
≥ TBOR
INTERNAL
72 ms
RESET

VDD
VBOR

INTERNAL <72 ms
RESET 72 ms

VDD
VBOR

INTERNAL
72 ms
RESET
Note: 72 ms delay only if PWRTE bit is programmed to ‘0’.


PIC16F627A/628A/648A
14.4.5 TIME OUT SEQUENCE 14.4.6 POWER CONTROL (PCON) STATUS
REGISTER
On power-up the time out sequence is as follows: First
PWRT time out is invoked after POR has expired. Then The power control/Status Register, PCON (address
OST is activated. The total time out will vary based on 8Eh) has two bits.
oscillator configuration and PWRTE bit Status. For
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
example, in RC mode with PWRTE bit set (PWRT
Power-on-Reset. It must then be set by the user and
disabled), there will be no time out at all. Figure 14-8,
checked on subsequent Resets to see if BOR = 0
Figure 14-9 and Figure 14-10 depict time out
indicating that a brown-out has occurred. The BOR
sequences.
Status bit is a don’t care and is not necessarily
Since the time outs occur from the POR pulse, if MCLR predictable if the brown-out circuit is disabled (by
is kept low long enough, the time outs will expire. Then setting BOREN bit = 0 in the Configuration word).
bringing MCLR high will begin execution immediately
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
(see Figure 14-9). This is useful for testing purposes or
Reset and unaffected otherwise. The user must write a
to synchronize more than one PIC16F627A/628A/
‘1’ to this bit following a Power-on Reset. On a
648A device operating in parallel.
subsequent Reset if POR is ‘0’, it will indicate that a
Table 14-6 shows the Reset conditions for some Power-on Reset must have occurred (VDD may have
special registers, while Table 14-7 shows the Reset gone too low).
conditions for all the registers.

TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS

Power-up Brown-out Reset
Wake-up
Oscillator Configuration
from Sleep
PWRTEN = 0 PWRTEN = 1 PWRTEN = 0 PWRTEN = 1

XT, HS, LP 72 ms + 1024•TOSC 72 ms + 1024•TOSC 1024•TOSC
1024•TOSC 1024•TOSC
RC, EC 72 ms — 72 ms — —

INTOSC 72 ms — 72 ms — 6 µs

TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR BOR TO PD Condition

0 X 1 1 Power-on Reset

0 X 0 X Illegal, TO is set on POR

0 X X 0 Illegal, PD is set on POR
1 0 X X Brown-out Reset
1 1 0 u WDT Reset
1 1 0 0 WDT Wake-up

1 1 u u MCLR Reset during normal operation

1 1 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown


PIC16F627A/628A/648A
TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Value on all
Value on
POR Reset
Resets(1)

03h, 83h, STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu
103h, 183h
8Eh PCON — — — — OSCF — POR BOR ---- 1-0x ---- u-uq
Shaded cells are not used by Brown-out Reset.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program Status PCON
Condition
Counter Register Register

Power-on Reset 000h 0001 1xxx ---- 1-0x

MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu

MCLR Reset during Sleep 000h 0001 0uuu ---- 1-uu
WDT Reset 000h 0000 uuuu ---- 1-uu
WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu
Brown-out Reset 000h 000x xuuu ---- 1-u0
(1)
Interrupt Wake-up from Sleep PC + 1 uuu1 0uuu ---- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.


PIC16F627A/628A/648A
TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS
• MCLR Reset during normal • Wake-up from Sleep(7)
operation through interrupt
Power-on
Register Address • MCLR Reset during Sleep • Wake-up from Sleep(7)
Reset
• WDT Reset through WDT time out
• Brown-out Reset (1)
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h — — —
TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h, 82h, 0000 0000 0000 0000 PC + 1(3)
102h, 182h
STATUS 03h, 83h, 0001 1xxx 000q quuu(4) uuuq 0uuu(4)
103h, 183h
FSR 04h, 84h, xxxx xxxx uuuu uuuu uuuu uuuu
104h, 184h
PORTA 05h xxxx 0000 xxxx 0000 uuuu uuuu
PORTB 06h, 106h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah, 8Ah, ---0 0000 ---0 0000 ---u uuuu
10Ah, 18Ah
INTCON 0Bh, 8Bh, 0000 000x 0000 000u uuuu uqqq(2)
10Bh,18Bh
PIR1 0Ch 0000 -000 0000 -000 qqqq -qqq(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h --00 0000 --uu uuuu(6) --uu uuuu
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 17h --00 0000 --00 0000 --uu uuuu
RCSTA 18h 0000 000x 0000 000x uuuu uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
CMCON 1Fh 0000 0000 0000 0000 uu-- uuuu
OPTION 81h,181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h 1111 1111 1111 1111 uuuu uuuu
TRISB 86h, 186h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 -000 0000 -000 uuuu -uuu
PCON 8Eh ---- 1-0x ---- 1-uq(1,5) ---- u-uu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
EEDATA 9Ah xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 9Bh xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
EECON2 9Dh — — —
VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-6 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: Reset to ‘--00 0000’ on a Brown-out Reset (BOR).
7: Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers.


PIC16F627A/628A/648A
FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE

VDD

MCLR

INTERNAL POR

Tpwrt

PWRT TIME OUT Tost

OST TIME OUT

INTERNAL RESET

FIGURE 14-9: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

Tpwrt

PWRT TIME OUT Tost

OST TIME OUT

INTERNAL RESET

FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

Tpwrt

PWRT TIME OUT Tost

OST TIME OUT

INTERNAL RESET


PIC16F627A/628A/648A
FIGURE 14-11: EXTERNAL POWER-ON FIGURE 14-13: EXTERNAL BROWN-OUT
RESET CIRCUIT (FOR PROTECTION CIRCUIT 2
SLOW VDD POWER-UP)
VDD VDD
VDD VDD
R1

Q1
D R MCLR
PIC16F627A/628A/648A
R1 R2 40k PIC16F627A/628A/648A
MCLR

C

Note 1: This Brown-out Circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
Note 1: External Power-on Reset circuit is required
when VDD is below a certain level such that:
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor R1
VDD x = 0.7 V
quickly when VDD powers down. R1 + R2
2: R < 40 kΩ is recommended to make sure R1
= 0.7 V
2: Internal Brown-out Reset should be dis-
Vdd x
that voltage drop across R does not violate R1 + R2
abled when using this circuit.
the device’s electrical specification.
3: Resistors should be adjusted for the
3: R1 = 100Ω to 1 kΩ will limit any current
characteristics of the transistor.
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).

FIGURE 14-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1

VDD VDD
33k

10k MCLR

40k PIC16F627A/628A/648A

Note 1: This circuit will activate Reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.


PIC16F627A/628A/648A
14.5 Interrupts When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
The PIC16F627A/628A/648A has 10 sources of pushed into the stack and the PC is loaded with 0004h.
interrupt: Once in the interrupt service routine the source(s) of
• External Interrupt RB0/INT the interrupt can be determined by polling the interrupt
• TMR0 Overflow Interrupt flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid RB0/
• PORTB Change Interrupts (pins RB7:RB4)
INT recursive interrupts.
• Comparator Interrupt
For external interrupt events, such as the INT pin or
• USART Interrupt TX
PORTB change interrupt, the interrupt latency will be
• USART Interrupt RX three or four instruction cycles. The exact latency
• CCP Interrupt depends when the interrupt event occurs (Figure 14-
• TMR1 Overflow Interrupt 15). The latency is the same for one or two cycle
• TMR2 Match Interrupt instructions. Once in the interrupt service routine the
• Data EEPROM Interrupt source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
The interrupt control register (INTCON) records cleared in software before re-enabling interrupts to
individual interrupt requests in flag bits. It also has avoid multiple interrupt requests. Individual interrupt
individual and global interrupt enable bits. flag bits are set regardless of the status of their
A global interrupt enable bit, GIE (INTCON<7>) corresponding mask bit or the GIE bit.
enables (if set) all un-masked interrupts or disables (if Note 1: Individual interrupt flag bits are set
cleared) all interrupts. Individual interrupts can be regardless of the status of their
disabled through their corresponding enable bits in corresponding mask bit or the GIE bit.
INTCON register. GIE is cleared on Reset.
2: When an instruction that clears the GIE
The “return from interrupt” instruction, RETFIE, exits bit is executed, any interrupts that were
interrupt routine as well as sets the GIE bit, which re- pending for execution in the next cycle
enable RB0/INT interrupts. are ignored. The CPU will execute a NOP
The INT pin interrupt, the RB port change interrupt and in the cycle immediately following the
the TMR0 overflow interrupt flags are contained in the instruction which clears the GIE bit. The
INTCON register. interrupts which were ignored are still
The peripheral interrupt flag is contained in the special pending to be serviced when the GIE bit
register PIR1. The corresponding interrupt enable bit is is set again.
contained in special registers PIE1.

FIGURE 14-14: INTERRUPT LOGIC

TMR1IF T0IF Wake-up (If in Sleep mode)
TMR1IE T0IE
TMR2IF INTF
TMR2IE INTE
CCP1IF RBIF
CCP1IE Interrupt to CPU
RBIE
CMIF
CMIE PEIE
TXIF
TXIE
RCIF
RCIE GIE
EEIF
EEIE


PIC16F627A/628A/648A
14.5.1 RB0/INT INTERRUPT 14.5.3 PORTB INTERRUPT
External interrupt on RB0/INT pin is edge triggered: An input change on PORTB <7:4> sets the RBIF
either rising if INTEDG bit (OPTION<6>) is set, or (INTCON<0>) bit. The interrupt can be enabled/disabled
falling, if INTEDG bit is clear. When a valid edge by setting/clearing the RBIE (INTCON<4>) bit. For
appears on the RB0/INT pin, the INTF bit operation of PORTB (Section 5.2 "PORTB and TRISB
(INTCON<1>) is set. This interrupt can be disabled by Registers").
clearing the INTE control bit (INTCON<4>). The INTF
Note: If a change on the I/O pin should occur
bit must be cleared in software in the interrupt service
when the read operation is being executed
routine before re-enabling this interrupt. The RB0/INT
(starts during the Q2 cycle and ends before
interrupt can wake-up the processor from Sleep, if the
the start of the Q3 cycle), then the RBIF
INTE bit was set prior to going into Sleep. The status of
interrupt flag may not get set.
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
14.5.4 COMPARATOR INTERRUPT
Section 14.8 "Power-Down Mode (Sleep)" for details
on Sleep, and Figure 14-17 for timing of wake-up from See Section 10.6 "Comparator Interrupts" for
Sleep through RB0/INT interrupt. complete description of comparator interrupts.

14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0 "Timer0 Module".

FIGURE 14-15: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1) (5)
INTF flag Interrupt Latency (2)
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h)

Instruction Dummy Cycle Dummy Cycle Inst (0004h)
Executed Inst (PC-1) Inst (PC)

Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available in RC and INTOSC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.


PIC16F627A/628A/648A
TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS
Value on all
Value on
POR Reset
Resets(1)
10Bh, 18Bh
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.

14.6 Context Saving During Interrupts 14.7 Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved The watchdog timer is a free running on-chip RC
on the stack. Typically, users may wish to save key oscillator which does not require any external
registers during an interrupt (e.g., W register and components. This RC oscillator is separate from the
Status Register). This must be implemented in RC oscillator of the CLKIN pin. That means that the
software. WDT will run, even if the clock on the OSC1 and OSC2
Example 14-2 stores and restores the Status and W pins of the device has been stopped, for example, by
registers. The user register, W_TEMP, must be defined execution of a SLEEP instruction. During normal oper-
in a common memory location (i.e., W_TEMP is ation, a WDT time out generates a device Reset. If the
defined at 0x70 in Bank 0 and is therefore, accessible device is in Sleep mode, a WDT time out causes the
at 0xF0, 0x170 and 0x1F0). The Example 14-2: device to wake-up and continue with normal operation.
The WDT can be permanently disabled by program-
• Stores the W register ming the configuration bit WDTE as clear
• Stores the Status Register (Section 14.1 "Configuration Bits").
• Executes the ISR code
• Restores the Status (and bank select bit register) 14.7.1 WDT PERIOD
• Restores the W register The WDT has a nominal time out period of 18 ms (with
no prescaler). The time out periods vary with tempera-
EXAMPLE 14-2: SAVING THE STATUS ture, VDD and process variations from part to part (see
AND W REGISTERS IN DC Specifications, Table 17-7). If longer time out
RAM periods are desired, a postscaler with a division ratio of
up to 1:128 can be assigned to the WDT under
MOVWF W_TEMP ;copy W to temp register,
;could be in any bank
software control by writing to the OPTION register.
SWAPF STATUS,W ;swap status to be saved Thus, time out periods up to 2.3 seconds can be
;into W realized.
BCF STATUS,RP0 ;change to bank 0
The CLRWDT and SLEEP instructions clear the WDT
;regardless of current
;bank and the postscaler, if assigned to the WDT, and prevent
MOVWF STATUS_TEMP ;save status to bank 0 it from timing out and generating a device Reset.
;register The TO bit in the Status Register will be cleared upon a
:
:(ISR)
Watchdog Timer time out.
:
14.7.2 WDT PROGRAMMING
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register CONSIDERATIONS
;into W, sets bank to original
;state It should also be taken in account that under worst case
MOVWF STATUS ;move W into STATUS register conditions (VDD = Min., Temperature = Max., max.
SWAPF W_TEMP,F ;swap W_TEMP WDT prescaler) it may take several seconds before a
SWAPF W_TEMP,W ;swap W_TEMP into W WDT time out occurs.


PIC16F627A/628A/648A
FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source
(Figure 6-1)

0
M
WDT POSTSCALER/
U
Watchdog TMR0 PRESCALER
Timer 1X
8

8 to 1 MUX PS<2:0>
PSA 3
WDT
Enable Bit
To TMR0
(Figure 6-1)

0 1
MUX PSA

WDT
Time out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on all
Value on
POR Reset
Resets

2007h Config. LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 uuuu uuuu uuuu uuuu
bits
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Note: Shaded cells are not used by the Watchdog Timer.

14.8 Power-Down Mode (Sleep) For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
The Power-down mode is entered by executing a circuitry drawing current from the I/O pin and the
SLEEP instruction. comparators, and VREF should be disabled. I/O pins
If enabled, the Watchdog Timer will be cleared but that are hi-impedance inputs should be pulled high or
keeps running, the PD bit in the Status Register is low externally to avoid switching currents caused by
cleared, the TO bit is set, and the oscillator driver is floating inputs. The T0CKI input should also be at VDD
turned off. The I/O ports maintain the status they or VSS for lowest current consumption. The
had, before SLEEP was executed (driving high, low, contribution from on chip pull-ups on PORTB should be
or hi-impedance). considered.
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a Reset generated
by a WDT time out does not drive MCLR
pin low.


PIC16F627A/628A/648A
14.8.1 WAKE-UP FROM SLEEP When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
The device can wake-up from Sleep through one of the to wake-up through an interrupt event, the correspond-
following events: ing interrupt enable bit must be set (enabled). Wake-up
1. External Reset input on MCLR pin is regardless of the state of the GIE bit. If the GIE bit is
2. Watchdog Timer wake-up (if WDT was enabled) clear (disabled), the device continues execution at the
3. Interrupt from RB0/INT pin, RB Port change, or instruction after the SLEEP instruction. If the GIE bit is
any Peripheral Interrupt. set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
The first event will cause a device Reset. The two latter rupt address (0004h). In cases where the execution of
events are considered a continuation of program the instruction following SLEEP is not desirable, the
execution. The TO and PD bits in the Status Register user should have an NOP after the SLEEP instruction.
can be used to determine the cause of device Reset.
PD bit, which is set on power-up is cleared when Sleep Note: If the global interrupts are disabled (GIE is
is invoked. TO bit is cleared if WDT wake-up occurred. cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will not
enter Sleep. The SLEEP instruction is
executed as a NOP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.

FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) Tost(2)

INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>) Processor in
Sleep
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy cycle Dummy cycle
Executed Inst(PC - 1) Inst(0004h)

Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for RC Osc mode.
3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = ‘0’, execution will continue
in-line.
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.

14.9 Code Protection 14.10 User ID Locations
With the Code Protect bit is cleared (Code Protect Four memory locations (2000h-2003h) are designated
enabled) the contents of the program memory locations as user ID locations where the user can store
are read out as “00”. See Programing Specification, checksum or other code-identification numbers. These
DS41196, for details. locations are not accessible during normal execution
but are readable and writable during program/verify.
Note: Only a Bulk Erase function can set the CP
Only the Least Significant 4 bits of the user ID locations
and CPD bits by turning off the code
are used.
protection. The entire data EEPROM and
Flash program memory will be erased to
turn the code protection off.


PIC16F627A/628A/648A
14.11 In-Circuit Serial Programming 14.12 Low Voltage Programming
The PIC16F627A/628A/648A microcontrollers can be The LVP bit of the configuration word, enables the low
serially programmed while in the end application circuit. voltage programming. This mode allows the microcon-
This is simply done with two lines for clock and data, troller to be programmed via ICSP using only a 5V
and three other lines for power, ground, and the source. This mode removes the requirement of VIHH to
programming voltage. This allows customers to manu- be placed on the MCLR pin. The LVP bit is normally
facture boards with unprogrammed devices and then erased to '1' which enables the low voltage program-
program the microcontroller just before shipping the ming. In this mode, the RB4/PGM pin is dedicated to
product. This also allows the most recent firmware, or the programming function and ceases to be a general
a custom firmware to be programmed. purpose I/O pin. The device will enter Programming
The device is placed into a Program/Verify mode by mode when a '1' is placed on the RB4/PGM pin. The
holding the RB6 and RB7 pins low while raising the HV Programming mode is still available by placing VIHH
MCLR (VPP) pin from VIL to VIHH (see programming on the MCLR pin.
specification). RB6 becomes the programming clock Note 1: While in this mode the RB4 pin can no
and RB7 becomes the programming data. Both RB6 longer be used as a general purpose I/O
and RB7 are Schmitt Trigger inputs in this mode. pin.
After Reset, to place the device into Programming/Verify 2: VDD must be 5.0V +10% during erase
mode, the program counter (PC) is at location 00h. A 6- operations.
bit command is then supplied to the device. Depending
on the command, 14 bits of program data are then If low-voltage Programming mode is not used, the LVP
supplied to or from the device, depending if the bit should be programmed to a '0' so that RB4/PGM
command was a load or a read. For complete details of becomes a digital I/O pin. To program the device, VIHH
serial programming, please refer to the Programming must be placed onto MCLR during programming. The
Specifications (DS41196). LVP bit may only be programmed when programming
is entered with VIHH on MCLR. The LVP bit cannot be
A typical In-Circuit Serial Programming connection is programmed when programming is entered with RB4/
shown in Figure 14-18. PGM.
It should be noted, that once the LVP bit is programmed
FIGURE 14-18: TYPICAL IN-CIRCUIT
to 0, only high voltage Programming mode can be used
SERIAL PROGRAMMING
to program the device.
CONNECTION

To Normal
Connections
External
Connector PIC16F627A/628A/648A
Signals

+5V VDD
0V VSS
VPP RA5/MCLR/VPP

CLK RB6/PGC

Data I/O RB7/PGD

VDD

To Normal
Connections


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
15.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
into three basic categories:
Each PIC16F627A/628A/648A instruction is a 14-bit
• Byte-oriented operations
word divided into an OPCODE which specifies the
instruction type and one or more operands which • Bit-oriented operations
further specify the operation of the instruction. The • Literal and control operations
PIC16F627A/628A/648A instruction set summary in All instructions are executed within one single
Table 15-2 lists byte-oriented, bit-oriented, and instruction cycle, unless a conditional test is true or the
literal and control operations. Table 15-1 shows the program counter is changed as a result of an
opcode field descriptions. instruction. In this case, the execution takes two
For byte-oriented instructions, ‘f’ represents a file instruction cycles with the second cycle executed as a
register designator and ‘d’ represents a destination NOP. One instruction cycle consists of four oscillator
designator. The file register designator specifies which periods. Thus, for an oscillator frequency of 4 MHz, the
file register is to be used by the instruction. normal instruction execution time is 1 µs. If a
conditional test is true or the program counter is
The destination designator specifies where the result of
changed as a result of an instruction, the instruction
the operation is to be placed. If ‘d’ is zero, the result is
execution time is 2 µs.
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction. Table 15-2 lists the instructions recognized by the
MPASM™ assembler.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected Figure 15-1 shows the three general formats that the
by the operation, while ‘f’ represents the number of the instructions can have.
file in which the bit is located.
Note 1: Any unused opcode is reserved. Use of
For literal and control operations, ‘k’ represents an any reserved opcode may cause unex-
eight or eleven bit constant or literal value. pected operation.
2: To maintain upward compatibility with
TABLE 15-1: OPCODE FIELD future PICmicro products, do not use the
DESCRIPTIONS OPTION and TRIS instructions.
Field Description All examples use the following format to represent a
f Register file address (0x00 to 0x7F) hexadecimal number:
W Working register (accumulator) 0xhh
b Bit address within an 8-bit file register
where h signifies a hexadecimal digit.
k Literal field, constant data or label
x Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the FIGURE 15-1: GENERAL FORMAT FOR
recommended form of use for compatibility with all INSTRUCTIONS
Microchip software tools.
Byte-oriented file register operations
d Destination select; d = 0: store result in W, 13 8 7 6 0
d = 1: store result in file register f.
OPCODE d f (FILE #)
Default is d = 1
label Label name d = 0 for destination W
TOS Top of Stack d = 1 for destination f
f = 7-bit file register address
PC Program Counter
PCLATH Program Counter High Latch Bit-oriented file register operations
GIE Global Interrupt Enable bit 13 10 9 76 0
WDT Watchdog Timer/Counter OPCODE b (BIT #) f (FILE #)
TO Time out bit
b = 3-bit bit address
PD Power-down bit f = 7-bit file register address
dest Destination either the W register or the specified
register file location Literal and control operations
General
[ ] Options
13 8 7 0
( ) Contents
→ Assigned to OPCODE k (literal)

<> Register bit field k = 8-bit immediate value
∈ In the set of CALL and GOTO instructions only
italics User defined term (font is courier) 13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value


PIC16F627A/628A/648A
TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET
14-Bit Opcode
Mnemonic, Status
Description Cycles Notes
Operands Affected
MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW — Clear W 1 00 0001 0000 0011 Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP — No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1(2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1(2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE — Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN — Return from Subroutine 2 00 0000 0000 1000
SLEEP — Go into Standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data
will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.


PIC16F627A/628A/648A
15.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW AND Literal with W
Syntax: [ label ] ADDLW k Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal ‘k’ and AND’ed with the eight bit literal ‘k’.
the result is placed in the W register. The result is placed in the W
Words: 1 register.

Cycles: 1 Words: 1

Example ADDLW 0x15 Cycles: 1

Before Instruction Example ANDLW 0x5F
W = 0x10 Before Instruction
After Instruction W = 0xA3
W = 0x25 After Instruction
W = 0x03

ADDWF Add W and f ANDWF AND W with f
Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff

Description: Add the contents of the W register Description: AND the W register with register ‘f’.
with register ‘f’. If ‘d’ is 0 the result is If ‘d’ is 0 the result is stored in the W
stored in the W register. If ‘d’ is 1 the register. If ‘d’ is 1 the result is stored
result is stored back in register ‘f’. back in register ‘f’.

Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example ADDWF REG1, 0 Example ANDWF REG1, 1

Before Instruction Before Instruction
W = 0x17 W = 0x17
REG1 = 0xC2 REG1 = 0xC2
After Instruction After Instruction
W = 0xD9 W = 0x17
REG1 = 0xC2 REG1 = 0x02
Z = 0
C = 0
DC = 0


PIC16F627A/628A/648A

BCF Bit Clear f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b
0≤b≤7 0≤b≤7
Operation: 0 → (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘0’ then the
Words: 1 next instruction is skipped.
If bit ‘b’ is ‘0’ then the next instruction
Cycles: 1 fetched during the current instruction
Example BCF REG1, 7 execution is discarded, and a NOP is
executed instead, making this a two-
Before Instruction
cycle instruction.
REG1 = 0xC7
After Instruction Words: 1
REG1 = 0x47 Cycles: 1(2)
Example HERE BTFSC REG1
FALSE GOTO PROCESS_CODE
BSF Bit Set f TRUE •
•
Syntax: [ label ] BSF f,b •
Operands: 0 ≤ f ≤ 127 Before Instruction
0≤b≤7 PC = address HERE
Operation: 1 → (f<b>) After Instruction
Status Affected: None if REG<1> = 0,
PC = address TRUE
Encoding: 01 01bb bfff ffff if REG<1>=1,
Description: Bit ‘b’ in register ‘f’ is set. PC = address FALSE
Words: 1
Cycles: 1
Example BSF REG1, 7
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A


PIC16F627A/628A/648A

BTFSS Bit Test f, Skip if Set CALL Call Subroutine
Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 2047
0≤b<7 Operation: (PC)+ 1→ TOS,
Operation: skip if (f<b>) = 1 k → PC<10:0>,
Status Affected: None (PCLATH<4:3>) → PC<12:11>

Encoding: 01 11bb bfff ffff Status Affected: None

Description: If bit ‘b’ in register ‘f’ is ‘1’ then the Encoding: 10 0kkk kkkk kkkk
next instruction is skipped. Description: Call Subroutine. First, return
If bit ‘b’ is ‘1’, then the next address (PC+1) is pushed onto
instruction fetched during the the stack. The eleven bit imme-
current instruction execution, is diate address is loaded into PC
discarded and a NOP is executed bits <10:0>. The upper bits of
instead, making this a two-cycle the PC are loaded from
instruction. PCLATH. CALL is a two-cycle
Words: 1 instruction.

Cycles: 1(2) Words: 1

Example HERE BTFSS REG1 Cycles: 2
FALSE GOTO PROCESS_CODE Example HERE CALL THERE
TRUE •
• Before Instruction
• PC = Address HERE
After Instruction
Before Instruction
PC = Address THERE
PC = address HERE
TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1, CLRF Clear f
PC = address TRUE Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1→Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
Words: 1
Cycles: 1
Example CLRF REG1
Before Instruction
REG1 = 0x5A
After Instruction
REG1 = 0x00
Z = 1


PIC16F627A/628A/648A

CLRW Clear W COMF Complement f
Syntax: [ label ] CLRW Syntax: [ label ] COMF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: 00h → (W) d ∈ [0,1]
1→Z Operation: (f) → (dest)
Status Affected: Z Status Affected: Z
Encoding: 00 0001 0000 0011 Encoding: 00 1001 dfff ffff
Description: W register is cleared. Zero bit Description: The contents of register ‘f’ are
(Z) is set. complemented. If ‘d’ is 0 the
Words: 1 result is stored in W. If ‘d’ is 1
the result is stored back in regis-
Cycles: 1 ter ‘f’.
Example CLRW Words: 1
Before Instruction Cycles: 1
W = 0x5A
After Instruction Example COMF REG1, 0
W = 0x00 Before Instruction
Z = 1 REG1 = 0x13
After Instruction
REG1 = 0x13
W = 0xEC

CLRWDT Clear Watchdog Timer DECF Decrement f
Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: 00h → WDT d ∈ [0,1]
0 → WDT prescaler, Operation: (f) - 1 → (dest)
1 → TO
1 → PD Status Affected: Z

Status Affected: TO, PD Encoding: 00 0011 dfff ffff

Encoding: 00 0000 0110 0100 Description: Decrement register ‘f’. If ‘d’ is 0
the result is stored in the W
Description: CLRWDT instruction resets the register. If ‘d’ is 1 the result is
Watchdog Timer. It also resets stored back in register ‘f’.
the prescaler of the WDT. Status
bits TO and PD are set. Words: 1

Words: 1 Cycles: 1

Cycles: 1 Example DECF CNT, 1

Example CLRWDT Before Instruction
CNT = 0x01
Before Instruction Z = 0
WDT counter = ? After Instruction
After Instruction CNT = 0x00
WDT counter = 0x00 Z = 1
WDT prescaler = 0
TO = 1
PD = 1


PIC16F627A/628A/648A

DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch
Syntax: [ label ] DECFSZ f,d Syntax: [ label ] GOTO k
d ∈ [0,1]
Operation: k → PC<10:0>
Operation: (f) - 1 → (dest); skip if result = PCLATH<4:3> → PC<12:11>
0
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Encoding: 00 1011 dfff ffff
Description: GOTO is an unconditional
Description: The contents of register ‘f’ are branch. The eleven-bit immedi-
decremented. If ‘d’ is 0 the result ate value is loaded into PC bits
is placed in the W register. If ‘d’ <10:0>. The upper bits of PC
is 1 the result is placed back in are loaded from PCLATH<4:3>.
register ‘f’. GOTO is a two-cycle instruction.
If the result is 0, the next instruc-
tion, which is already fetched, is Words: 1
discarded. A NOP is executed Cycles: 2
instead making it a two-cycle
Example GOTO THERE
instruction.
After Instruction
Words: 1
PC = Address THERE
Cycles: 1(2)
Example HERE DECFSZ REG1, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 - 1
if REG1 = 0,
PC = address CONTINUE
if REG1 ≠ 0,
PC = address HERE+1


PIC16F627A/628A/648A

INCF Increment f INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCF f,d Syntax: [ label ] INCFSZ f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0
Status Affected: Z Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
incremented. If ‘d’ is 0 the result incremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’ is placed in the W register. If ‘d’
is 1 the result is placed back in is 1 the result is placed back in
register ‘f’. register ‘f’.
Words: 1 If the result is 0, the next instruc-
tion, which is already fetched, is
Cycles: 1 discarded. A NOP is executed
Example INCF REG1, 1 instead making it a two-cycle
instruction.
Before Instruction
REG1 = 0xFF Words: 1
Z = 0 Cycles: 1(2)
After Instruction
REG1 = 0x00 Example HERE INCFSZ REG1, 1
GOTO LOOP
Z = 1 CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1≠ 0,
PC = address HERE +1


PIC16F627A/628A/648A

IORLW Inclusive OR Literal with W MOVLW Move Literal to W
Syntax: [ label ] IORLW k Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W) Operation: k → (W)
Status Affected: Z Status Affected: None
Encoding: 11 1000 kkkk kkkk Encoding: 11 00xx kkkk kkkk
Description: The contents of the W register is Description: The eight bit literal ‘k’ is loaded
OR’ed with the eight bit literal ‘k’. into W register. The don’t cares
The result is placed in the W will assemble as 0’s.
register. Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example MOVLW 0x5A
Example IORLW 0x35
After Instruction
Before Instruction W = 0x5A
W = 0x9A
After Instruction
W = 0xBF
Z = 0

IORWF Inclusive OR W with f MOVF Move f
Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (W) .OR. (f) → (dest) Operation: (f) → (dest)
Status Affected: Z Status Affected: Z
Description: Inclusive OR the W register with Description: The contents of register f is
register ‘f’. If ‘d’ is 0 the result is moved to a destination depen-
placed in the W register. If ‘d’ is dent upon the status of d. If d =
1 the result is placed back in 0, destination is W register. If d
register ‘f’. = 1, the destination is file regis-
Words: 1 ter f itself. d = 1 is useful to test
a file register since status flag Z
Cycles: 1 is affected.
Example IORWF REG1, 0
Words: 1
Before Instruction Cycles: 1
REG1 = 0x13
W = 0x91 Example MOVF REG1, 0
After Instruction After Instruction
REG1 = 0x13 W= value in REG1 register
W = 0x93 Z = 1
Z = 1


PIC16F627A/628A/648A

MOVWF Move W to f OPTION Load Option Register
Syntax: [ label ] MOVWF f Syntax: [ label ] OPTION
Operands: 0 ≤ f ≤ 127 Operands: None
Operation: (W) → (f) Operation: (W) → OPTION

Status Affected: None Status Affected: None
Encoding: 00 0000 0110 0010
Encoding: 00 0000 1fff ffff
Description: The contents of the W register are
Description: Move data from W register to
loaded in the OPTION register.
register ‘f’.
This instruction is supported for
Words: 1 code compatibility with PIC16C5X
Cycles: 1 products. Since OPTION is a
readable/writable register, the
Example MOVWF REG1
user can directly address it. Using
Before Instruction only register instruction such as
REG1 = 0xFF MOVWF.
W = 0x4F Words: 1
After Instruction
Cycles: 1
REG1 = 0x4F
W = 0x4F Example
To maintain upward compatibil-
ity with future PICmicro®
products, do not use this
instruction.

NOP No Operation RETFIE Return from Interrupt

Syntax: [ label ] NOP Syntax: [ label ] RETFIE

Operands: None Operands: None

Operation: No operation Operation: TOS → PC,
1 → GIE
Encoding: 00 0000 0xx0 0000
Encoding: 00 0000 0000 1001
Description: No operation.
Description: Return from Interrupt. Stack is
Words: 1 POPed and Top of Stack (TOS)
Cycles: 1 is loaded in the PC. Interrupts
Example NOP are enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-
cycle instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1


PIC16F627A/628A/648A

RETLW Return with Literal in W RLF Rotate Left f through Carry
Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: k → (W); d ∈ [0,1]
TOS → PC Operation: See description below
Status Affected: None Status Affected: C
Encoding: 11 01xx kkkk kkkk Encoding: 00 1101 dfff ffff
Description: The W register is loaded with Description: The contents of register ‘f’ are
the eight bit literal ‘k’. The rotated one bit to the left through
program counter is loaded from the Carry Flag. If ‘d’ is 0 the result
the top of the stack (the return is placed in the W register. If ‘d’ is
address). This is a two-cycle 1 the result is stored back in
instruction. register ‘f’.
Words: 1 C REGISTER F

Cycles: 2
Words: 1
Example CALL TABLE;W contains table
;offset value Cycles: 1
• ;W now has table value Example RLF REG1, 0
•
• Before Instruction
TABLE
ADDWF PC;W = offset REG1=1110 0110
RETLW k1;Begin table C = 0
RETLW k2; After Instruction
• REG1=1110 0110
• W = 1100 1100
• C = 1
RETLW kn; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
two-cycle instruction.
Words: 1
Cycles: 2
Example RETURN
After Interrupt
PC = TOS


PIC16F627A/628A/648A

RRF Rotate Right f through Carry SUBLW Subtract W from Literal
Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k
d ∈ [0,1] Operation: k - (W) → (W)
Operation: See description below Status C, DC, Z
Status Affected: C Affected:
Encoding: 00 1100 dfff ffff Encoding: 11 110x kkkk kkkk
Description: The contents of register ‘f’ are Description: The W register is subtracted (2’s
rotated one bit to the right complement method) from the eight
through the Carry Flag. If ‘d’ is 0 bit literal ‘k’. The result is placed in
the result is placed in the W the W register.
register. If ‘d’ is 1 the result is Words: 1
placed back in register ‘f’.
Cycles: 1
C REGISTER F
Example 1: SUBLW 0x02

Words: 1 Before Instruction
Cycles: 1 W = 1
C = ?
Example RRF REG1, 0
After Instruction
Before Instruction
REG1 = 1110 0110 W = 1
C = 0 C = 1; result is positive
After Instruction Example 2: Before Instruction
REG1 = 1110 0110
W = 2
W = 0111 0011
C = ?
C = 0
After Instruction
W = 0
SLEEP C = 1; result is zero
Syntax: [ label ] SLEEP Example 3: Before Instruction
Operands: None W = 3
C = ?
Operation: 00h → WDT,
0 → WDT prescaler, After Instruction
1 → TO, W = 0xFF
0 → PD C = 0; result is negative
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down Status bit, PD
is cleared. Time out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator
stopped. See Section 14.8
"Power-Down Mode (Sleep)"
for more details.
Words: 1
Cycles: 1
Example: SLEEP


PIC16F627A/628A/648A

SUBWF Subtract W from f SWAPF Swap Nibbles in f
Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - (W) → (dest) Operation: (f<3:0>) → (dest<7:4>),
Status C, DC, Z (f<7:4>) → (dest<3:0>)
Affected: Status Affected: None
Description: Subtract (2’s complement method) Description: The upper and lower nibbles of
W register from register ‘f’. If ‘d’ is 0 register ‘f’ are exchanged. If ‘d’ is
the result is stored in the W register. 0 the result is placed in W
If ‘d’ is 1 the result is stored back in register. If ‘d’ is 1 the result is
register ‘f’. placed in register ‘f’.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example 1: SUBWF REG1, 1 Example SWAPF REG1, 0
Before Instruction Before Instruction
REG1 = 3 REG1 = 0xA5
W = 2 After Instruction
C = ?
REG1 = 0xA5
After Instruction W = 0x5A
REG1 = 1
W = 2
C = 1; result is positive TRIS Load TRIS Register
DC = 1 Syntax: [ label ] TRIS f
Z = 0
Operands: 5≤f≤7
Example 2: Before Instruction
Operation: (W) → TRIS register f;
REG1 = 2
W = 2
C = ? Encoding: 00 0000 0110 0fff

After Instruction Description: The instruction is supported for
code compatibility with the
REG1 = 0 PIC16C5X products. Since TRIS
W = 2 registers are readable and
C = 1; result is zero writable, the user can directly
Z = DC = 1 address them.
Example 3: Before Instruction Words: 1
REG1 = 1 Cycles: 1
W = 2 Example
C = ?
To maintain upward compatibil-
After Instruction ity with future PICmicro®
REG1 = 0xFF products, do not use this
W = 2 instruction.
C = 0; result is negative
Z = DC = 0


PIC16F627A/628A/648A

XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f
Syntax: [ label ] XORLW k Syntax: [ label ] XORWF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) .XOR. k → (W) d ∈ [0,1]

Status Affected: Z Operation: (W) .XOR. (f) → (dest)

Encoding: 11 1010 kkkk kkkk Status Affected: Z

Description: The contents of the W register Encoding: 00 0110 dfff ffff
are XOR’ed with the eight bit Description: Exclusive OR the contents of the
literal ‘k’. The result is placed in W register with register ‘f’. If ‘d’ is
the W register. 0 the result is stored in the W
Words: 1 register. If ‘d’ is 1 the result is
stored back in register ‘f’.
Cycles: 1
Words: 1
Example: XORLW 0xAF
Cycles: 1
Before Instruction
Example XORWF REG1, 1
W = 0xB5
Before Instruction
After Instruction
REG1 = 0xAF
W = 0x1A W = 0xB5
After Instruction
REG1 = 0x1A
W = 0xB5


PIC16F627A/628A/648A
16.0 DEVELOPMENT SUPPORT 16.1 MPLAB Integrated Development
Environment Software
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
based application that contains:
• Assemblers/Compilers/Linkers
• An interface to debugging tools
- MPASMTM Assembler
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - emulator (sold separately)
- MPLAB C30 C Compiler - in-circuit debugger (sold separately)
- MPLAB ASM30 Assembler/Linker/Library • A full-featured editor with color coded context
• Simulators • A multiple project manager
- MPLAB SIM Software Simulator • Customizable data windows with direct edit of
contents
- MPLAB dsPIC30 Software Simulator
• High-level source code debugging
• Emulators
• Mouse over variable inspection
- MPLAB ICE 2000 In-Circuit Emulator
• Extensive on-line help
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger The MPLAB IDE allows you to:
- MPLAB ICD 2 • Edit your source files (either assembly or C)
• Device Programmers • One touch assemble (or compile) and download
- PRO MATE® II Universal Device Programmer to PICmicro emulator and simulator tools
(automatically updates all project information)
- PICSTART® Plus Development Programmer
• Debug using:
- MPLAB PM3 Device Programmer
- source files (assembly or C)
• Low-Cost Demonstration Boards
- mixed assembly and C
- PICDEMTM 1 Demonstration Board
- machine code
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
- PICDEM 3 Demonstration Board
simulators, through low-cost in-circuit debuggers, to
- PICDEM 4 Demonstration Board full-featured emulators. This eliminates the learning
- PICDEM 17 Demonstration Board curve when upgrading to tools with increasing flexibility
- PICDEM 18R Demonstration Board and power.
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
16.2 MPASM Assembler
• Evaluation Kits The MPASM assembler is a full-featured, universal
- KEELOQ® macro assembler for all PICmicro MCUs.
- PICDEM MSC The MPASM assembler generates relocatable object
- microID® files for the MPLINK object linker, Intel® standard hex
- CAN files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
- PowerSmart®
and generated machine code and COFF files for
- Analog debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process


PIC16F627A/628A/648A
16.3 MPLAB C17 and MPLAB C18 16.6 MPLAB ASM30 Assembler, Linker
C Compilers and Librarian
The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable
Systems are complete ANSI C compilers for machine code from symbolic assembly language for
Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the
microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler
integration capabilities, superior code optimization and generates relocatable object files that can then be
ease of use not found with other compilers. archived or linked with other relocatable object files and
For easy source level debugging, the compilers provide archives to create an executable file. Notable features
symbol information that is optimized to the MPLAB IDE of the assembler include:
debugger. • Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
16.4 MPLINK Object Linker/ • Command line interface
MPLIB Object Librarian • Rich directive set
The MPLINK object linker combines relocatable • Flexible macro language
objects created by the MPASM assembler and the • MPLAB IDE compatibility
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using 16.7 MPLAB SIM Software Simulator
directives from a linker script.
The MPLAB SIM software simulator allows code devel-
The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the
modification of library files of precompiled code. When PICmicro series microcontrollers on an instruction
a routine from a library is called from a source file, only level. On any given instruction, the data areas can be
the modules that contain that routine will be linked in examined or modified and stimuli can be applied from
with the application. This allows large libraries to be a file, or user defined key press, to any pin. The execu-
used efficiently in many different applications. tion can be performed in Single-Step, Execute Until
The object linker/library features include: Break or Trace mode.
• Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic
smaller files debugging using the MPLAB C17 and MPLAB C18
• Enhanced code maintainability by grouping C Compilers, as well as the MPASM assembler. The
related modules together software simulator offers the flexibility to develop and
• Flexible creation of libraries with easy module debug code outside of the laboratory environment,
listing, replacement, deletion and extraction making it an excellent, economical software
development tool.
16.5 MPLAB C30 C Compiler
16.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard The MPLAB SIM30 software simulator allows code
ANSI C programs into dsPIC30F assembly language development in a PC hosted environment by simulating
source. The compiler also supports many command the dsPIC30F series microcontrollers on an instruction
line options and language extensions to take full level. On any given instruction, the data areas can be
advantage of the dsPIC30F device hardware capabili- examined or modified and stimuli can be applied from
ties and afford fine control of the compiler code a file, or user defined key press, to any of the pins.
generator. The MPLAB SIM30 simulator fully supports symbolic
MPLAB C30 is distributed with a complete ANSI C debugging using the MPLAB C30 C Compiler and
standard library. All library functions have been MPLAB ASM30 assembler. The simulator runs in either
validated and conform to the ANSI C library standard. a Command Line mode for automated tasks, or from
The library includes functions for string manipulation, MPLAB IDE. This high-speed simulator is designed to
dynamic memory allocation, data conversion, time- debug, analyze and optimize time intensive DSP
keeping and math functions (trigonometric, exponential routines.
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.


PIC16F627A/628A/648A
16.9 MPLAB ICE 2000 16.11 MPLAB ICD 2 In-Circuit Debugger
High-Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 universal in-circuit emulator is connecting to the host PC via an RS-232 or high-speed
intended to provide the product development engineer USB interface. This tool is based on the Flash
with a complete microcontroller design tool set for PICmicro MCUs and can be used to develop for these
PICmicro microcontrollers. Software control of the and other PICmicro microcontrollers. The MPLAB
MPLAB ICE 2000 in-circuit emulator is advanced by ICD 2 utilizes the in-circuit debugging capability built
the MPLAB Integrated Development Environment, into the Flash devices. This feature, along with
which allows editing, building, downloading and source Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
debugging from a single environment. protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
The MPLAB ICE 2000 is a full-featured emulator sys- Integrated Development Environment. This enables a
tem with enhanced trace, trigger and data monitoring designer to develop and debug source code by setting
features. Interchangeable processor modules allow the breakpoints, single-stepping and watching variables,
system to be easily reconfigured for emulation of differ- CPU status and peripheral registers. Running at full
ent processors. The universal architecture of the speed enables testing hardware and applications in
MPLAB ICE in-circuit emulator allows expansion to real-time. MPLAB ICD 2 also serves as a development
support new PICmicro microcontrollers. programmer for selected PICmicro devices.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with 16.12 PRO MATE II Universal Device
advanced features that are typically found on more Programmer
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device
chosen to best make these features available in a programmer with programmable voltage verification at
simple, unified application. VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
16.10 MPLAB ICE 4000 and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
High-Performance Universal
PRO MATE II device programmer can read, verify and
In-Circuit Emulator program PICmicro devices without a PC connection. It
The MPLAB ICE 4000 universal in-circuit emulator is can also set code protection in this mode.
intended to provide the product development engineer
with a complete microcontroller design tool set for high- 16.13 MPLAB PM3 Device Programmer
end PICmicro microcontrollers. Software control of the
The MPLAB PM3 is a universal, CE compliant device
MPLAB ICE in-circuit emulator is provided by the
programmer with programmable voltage verification at
MPLAB Integrated Development Environment, which
VDDMIN and VDDMAX for maximum reliability. It features
allows editing, building, downloading and source
a large LCD display (128 x 64) for menus and error
debugging from a single environment.
messages and a modular detachable socket assembly
The MPLAB ICD 4000 is a premium emulator system, to support various package types. The ICSP™ cable
providing the features of MPLAB ICE 2000, but with assembly is included as a standard item. In Stand-
increased emulation memory and high-speed perfor- Alone mode, the MPLAB PM3 device programmer can
mance for dsPIC30F and PIC18XXXX devices. Its read, verify and program PICmicro devices without a
advanced emulator features include complex triggering PC connection. It can also set code protection in this
and timing, up to 2 Mb of emulation memory and the mode. MPLAB PM3 connects to the host PC via an
ability to view variables in real-time. RS-232 or USB cable. MPLAB PM3 has high-speed
The MPLAB ICE 4000 in-circuit emulator system has communications and optimized algorithms for quick
been designed as a real-time emulation system with programming of large memory devices and incorpo-
advanced features that are typically found on more rates an SD/MMC card for file storage and secure data
expensive development tools. The PC platform and applications.
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.


PIC16F627A/628A/648A
16.14 PICSTART Plus Development 16.17 PICDEM 2 Plus
Programmer Demonstration Board
The PICSTART Plus development programmer is an The PICDEM 2 Plus demonstration board supports
easy-to-use, low-cost, prototype programmer. It many 18, 28 and 40-pin microcontrollers, including
connects to the PC via a COM (RS-232) port. MPLAB PIC16F87X and PIC18FXX2 devices. All the neces-
Integrated Development Environment software makes sary hardware and software is included to run the dem-
using the programmer simple and efficient. The onstration programs. The sample microcontrollers
PICSTART Plus development programmer supports provided with the PICDEM 2 demonstration board can
most PICmicro devices up to 40 pins. Larger pin count be programmed with a PRO MATE II device program-
devices, such as the PIC16C92X and PIC17C76X, mer, PICSTART Plus development programmer, or
may be supported with an adapter socket. The MPLAB ICD 2 with a Universal Programmer Adapter.
PICSTART Plus development programmer is CE The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
compliant. may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
16.15 PICDEM 1 PICmicro circuitry for additional application components. Some
Demonstration Board of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
The PICDEM 1 demonstration board demonstrates the sensor, four LEDs and sample PIC18F452 and
capabilities of the PIC16C5X (PIC16C54 to PIC16F877 Flash microcontrollers.
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All 16.18 PICDEM 3 PIC16C92X
necessary hardware and software is included to run Demonstration Board
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can The PICDEM 3 demonstration board supports the
be programmed with a PRO MATE II device program- PIC16C923 and PIC16C924 in the PLCC package. All
mer or a PICSTART Plus development programmer. the necessary hardware and software is included to run
The PICDEM 1 demonstration board can be connected the demonstration programs.
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional appli- 16.19 PICDEM 4 8/14/18-Pin
cation components. Features include an RS-232 Demonstration Board
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs. The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
16.16 PICDEM.net Internet/Ethernet PIC18XXXX MCUs, including the PIC16F818/819,
Demonstration Board PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
The PICDEM.net demonstration board is an Internet/ showcase the many features of these low pin count
Ethernet demonstration board using the PIC18F452 parts, including LIN and Motor Control using ECCP.
microcontroller and TCP/IP firmware. The board Special provisions are made for low-power operation
supports any 40-pin DIP device that conforms to the with the supercapacitor circuit and jumpers allow on-
standard pinout used by the PIC16F877 or board hardware to be disabled to eliminate current
PIC18C452. This kit features a user friendly TCP/IP draw in this mode. Included on the demo board are pro-
stack, web server with HTML, a 24L256 Serial visions for Crystal, RC or Canned Oscillator modes, a
EEPROM for Xmodem download to web pages into five volt regulator for use with a nine volt wall adapter
Serial EEPROM, ICSP/MPLAB ICD 2 interface con- or battery, DB-9 RS-232 interface, ICD connector for
nector, an Ethernet interface, RS-232 interface and a programming via ICSP and development with MPLAB
16 x 2 LCD display. Also included is the book and ICD 2, 2 x 16 liquid crystal display, PCB footprints for
CD-ROM “TCP/IP Lean, Web Servers for Embedded H-Bridge motor driver, LIN transceiver and EEPROM.
Systems,” by Jeremy Bentham Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along with
the User’s Guide.


PIC16F627A/628A/648A
16.20 PICDEM 17 Demonstration Board 16.24 PICDEM USB PIC16C7X5
The PICDEM 17 demonstration board is an evaluation
Demonstration Board
board that demonstrates the capabilities of several The PICDEM USB Demonstration Board shows off the
Microchip microcontrollers, including PIC17C752, capabilities of the PIC16C745 and PIC16C765 USB
PIC17C756A, PIC17C762 and PIC17C766. A microcontrollers. This board provides the basis for
programmed sample is included. The PRO MATE II future USB products.
device programmer, or the PICSTART Plus develop-
ment programmer, can be used to reprogram the 16.25 Evaluation and
device for user tailored application development. The Programming Tools
PICDEM 17 demonstration board supports program
download and execution from external on-board Flash In addition to the PICDEM series of circuits, Microchip
memory. A generous prototype area is available for has a line of evaluation kits and demonstration software
user hardware expansion. for these products.
• KEELOQ evaluation and programming tools for
16.21 PICDEM 18R PIC18C601/801 Microchip’s HCS Secure Data Products
Demonstration Board • CAN developers kit for automotive network
The PICDEM 18R demonstration board serves to assist applications
development of the PIC18C601/801 family of Microchip • Analog design boards and filter design software
microcontrollers. It provides hardware implementation • PowerSmart battery charging evaluation/
of both 8-bit Multiplexed/Demultiplexed and 16-bit calibration kits
Memory modes. The board includes 2 Mb external • IrDA® development kit
Flash memory and 128 Kb SRAM memory, as well as
• microID development and rfLabTM development
serial EEPROM, allowing access to the wide range of
software
memory types supported by the PIC18C601/801.
• SEEVAL® designer kit for memory evaluation and
16.22 PICDEM LIN PIC16C43X endurance calculations
Demonstration Board • PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
The powerful LIN hardware and software kit includes a ADC and flow rate sensor
series of boards and three PICmicro microcontrollers.
Check the Microchip web page and the latest Product
The small footprint PIC16C432 and PIC16C433 are
Selector Guide for the complete list of demonstration
used as slaves in the LIN communication and feature
and evaluation kits.
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.

16.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the User’s Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB® IDE
(Integrated Development Environment) software,
software and hardware “Tips 'n Tricks for 8-pin Flash
PIC® Microcontrollers” Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias................................................................................................................. -40 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +14V
Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V
Total power dissipation(1) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)............................................................................................................... ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (Combined)................................................................................200 mA
Maximum current sourced by PORTA and PORTB (Combined)...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.


PIC16F627A/628A/648A
FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

6.0

5.5

5.0

4.5
VDD
(VOLTS)
4.0

3.5

3.0

2.5

0 4 10 20 25
FREQUENCY (MHz)

Note: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
6.0

5.5

5.0

4.5
VDD
(VOLTS)
4.0

3.5

3.0

2.5

2.0
0 4 10 20 25
FREQUENCY (MHz)

Note: The shaded region indicates the permissible combinations of voltage and frequency.


PIC16F627A/628A/648A
17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
PIC16LF627A/628A/648A Standard Operating Conditions (unless otherwise stated)
(Industrial) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)
PIC16F627A/628A/648A
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and
(Industrial, Extended)
-40°C ≤ Ta ≤ +125°C for extended

Param
Sym Characteristic/Device Min Typ† Max Units Conditions
No.
VDD Supply Voltage
D001 PIC16LF627A/628A/648A 2.0 — 5.5 V
PIC16F627A/628A/648A 3.0 — 5.5 V
D002 VDR RAM Data Retention — 1.5* — V Device in Sleep mode
Voltage(1)
D003 VPOR VDD Start Voltage — VSS — V See Section 14.4 on Power-on
to ensure Power-on Reset Reset for details
D004 SVDD VDD Rise Rate 0.05* — — V/ms See Section 14.4 on Power-on
to ensure Power-on Reset Reset for details
D005 VBOR Brown-out Reset Voltage 3.65 4.0 4.35 V BOREN configuration bit is set
3.65 4.0 4.4 V BOREN configuration bit is set,
Extended
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0 V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.


PIC16F627A/628A/648A
17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial)
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

Param LF and F Device Conditions
Min† Typ Max Units
No. Characteristics VDD Note
Supply Voltage (VDD)
LF 2.0 — 5.5 V —
D001
LF/F 3.0 — 5.5 V —
Power-down Base Current (IPD)
LF — 0.1 0.80 µA 2.0 WDT, BOR, Comparators, VREF, and
T1OSC: disabled
D020 — 0.1 0.85 µA 3.0
LF/F
— 0.2 2.7 µA 5.0
Peripheral Module Current (∆IMOD)(1)
LF — 1 2.0 µA 2.0 WDT Current
D021 — 2 3.4 µA 3.0
LF/F
— 9 17.0 µA 5.0
— 32 TBD µA 4.5 BOR Current
D022 LF/F
— 33 TBD µA 5.0
LF — 15 TBD µA 2.0 Comparator Current
D023 — 27 TBD µA 3.0
LF/F
— 49 TBD µA 5.0
LF — 34 TBD µA 2.0 VREF Current
D024 — 50 TBD µA 3.0
LF/F
— 80 TBD µA 5.0
LF — 1.2 2.0 µA 2.0 T1OSC Current
D025 — 1.3 2.2 µA 3.0
LF/F
— 1.8 2.9 µA 5.0
Supply Current (IDD)
LF — 12 15 µA 2.0 FOSC = 32 kHz
LP Oscillator Mode
D010 — 21 25 µA 3.0
LF/F
— 38 48 µA 5.0
LF — 130 190 µA 2.0 FOSC = 1 MHz
D011 — 220 340 µA 3.0 XT Oscillator Mode
LF/F
— 370 520 µA 5.0
LF — 270 350 µA 2.0 FOSC = 4 MHz
XT Oscillator Mode
D012 — 430 600 µA 3.0
LF/F
— 780 995 µA 5.0
— 2.6 2.9 mA 4.5 FOSC = 20 MHz
D013 LF/F HS Oscillator Mode
— 3 3.3 mA 5.0
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement. Max values should be used when calculating total current consumption.


PIC16F627A/628A/648A
17.3 DC Characteristics: PIC16F627A/628A/648A (Extended)
Operating temperature -40°C ≤ Ta ≤ +125°C for extended

Param Conditions
Device Characteristics Min† Typ Max Units
No. VDD Note
Supply Voltage (VDD)
D001 — 3.0 — 5.5 V —
Power-down Base Current (IPD)
— 0.1 TBD µA 3.0 WDT, BOR, Comparators, VREF, and
D020E — T1OSC: disabled
— 0.2 TBD µA 5.0
Peripheral Module Current (∆IMOD)(1)
— 2 TBD µA 3.0 WDT Current
D021E —
— 9 TBD µA 5.0
— 32 TBD µA 4.5 BOR Current
D022E —
— 33 TBD µA 5.0
— 27 TBD µA 3.0 Comparator Current
D023E —
— 49 TBD µA 5.0
— 50 TBD µA 3.0 VREF Current
D024E —
— 83 TBD µA 5.0
— 1.3 TBD µA 3.0 T1OSC Current
D025E —
— 1.8 TBD µA 5.0
Supply Current (IDD)
— 21 TBD µA 3.0 FOSC = 32 kHz
D010E — LP Oscillator Mode
— 38 TBD µA 5.0
— 220 TBD µA 3.0 FOSC = 1 MHz
D011E — XT Oscillator Mode
— 370 TBD µA 5.0
— 430 TBD µA 3.0 FOSC = 4 MHz
D012E — XT Oscillator Mode
— 780 TBD µA 5.0
— 2.6 TBD mA 4.5 FOSC = 20 MHz
D013E — HS Oscillator Mode
— 3 TBD mA 5.0
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement. Max values should be used when calculating total current consumption.


PIC16F627A/628A/648A
17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3

Param.
Sym Characteristic/Device Min Typ† Max Unit Conditions
No.
VIL Input Low Voltage
I/O ports
D030 with TTL buffer VSS — 0.8 V VDD = 4.5V to 5.5V
VSS — 0.15 VDD V otherwise
D031 with Schmitt Triggerinput(4) VSS — 0.2 VDD V
D032 MCLR, RA4/T0CKI,OSC1 VSS — 0.2 VDD V (Note1)
(in RC mode)
D033 OSC1 (in HS) VSS — 0.3 VDD V
OSC1 (in LP and XT) VSS — 0.8 V
VIH Input High Voltage
I/O ports
D040 with TTL buffer 2.0 V — VDD V VDD = 4.5V to 5.5V
.25 VDD + 0.8 V — VDD V otherwise
D041 with Schmitt Trigger input(4) 0.8 VDD — VDD V
D042 MCLR RA4/T0CKI 0.8 VDD — VDD V
D043 OSC1 (XT, HS and LP) 0.7 VDD — VDD V
D043A OSC1 (in RC mode) 0.9 VDD — VDD V (Note1)
D070 IPURB PORTB weak pull-up 50 200 400 µA VDD = 5.0V, VPIN = VSS
current
IIL Input Leakage Current(2), (3)
I/O ports (Except PORTA) — — ±1.0 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
D060 PORTA(4) — — ±0.5 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
D061 RA4/T0CKI — — ±1.0 µA VSS ≤ VPIN ≤ VDD
D063 OSC1, MCLR — — ±5.0 µA VSS ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
— — 0.6 V IOL=8.5 mA, VDD=4.5 V, -40° to +85°C
D080 I/O ports(4)
— — 0.6 V IOL=7.0 mA, VDD=4.5 V, +85° to +125°C
VOH Output High Voltage(3)
D090 I/O ports (Except RA4(4) VDD-0.7 — — V IOH=-3.0 mA, VDD=4.5 V, -40° to +85°C
VDD-0.7 — — V IOH=-2.5 mA, VDD=4.5 V, +85° to
+125°C
D150 VOD Open-Drain High Voltage — — 8.5* V RA4 pin PIC16F627A/628A/648A,
PIC16LF627A/628A/648A
Capacitive Loading Specs on Output Pins
D100* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external
clock used to drive OSC1.
D101* Cio All I/O pins/OSC2 (in RC mode) — — 50 pF
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F627A/628A/648A be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Includes OSC1 and OSC2 when configured as I/O pins, CLKIN, or CLKOUT.


PIC16F627A/628A/648A
TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
DC Characteristics Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3

Parameter
Sym Characteristic Min Typ† Max Units Conditions
No.
Data EEPROM Memory
D120 ED Endurance 100K 1M — E/W -40°C ≤ TA ≤ 85°C
D120A ED Endurance 10K 100K E/W 85°C ≤ TA ≤ 125°C
D121 VDRW VDD for read/write VMIN — 5.5 V VMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time — 4 8* ms
D123 TRETD Characteristic Retention 100 — — Year Provided no other
specifications are violated
D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C
Cycles before Refresh(1)
Program Flash Memory
D130 EP Endurance 10K 100K — E/W -40°C ≤ TA ≤ 85°C
D130A EP Endurance 1000 10K — E/W 85°C ≤ TA ≤ 125°C
D131 VPR VDD for read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VIE VDD for Block erase 4.5 — 5.5 V
D132A VPEW VDD for write VMIN — 5.5 V VMIN = Minimum operating
voltage
D133 TIE Block Erase cycle time — 4 8* ms VDD > 4.5V
D133A TPEW Write cycle time — 2 4* ms
D134 TRETP Characteristic Retention 100 — — year Provided no other
specifications are violated
† Data in “Typ” column is at 5.0 V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Refer to Section 13.7 "Using the Data EEPROM" for a more detailed discussion on data EEPROM
endurance.


PIC16F627A/628A/648A
TABLE 17-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.

Param
Characteristics Sym Min Typ Max Units Comments
No.

D300 Input Offset Voltage VIOFF — ±5.0 ±10 mV
D301 Input Common Mode Voltage VICM 0 — VDD - 1.5* V
D302 Common Mode Rejection Ratio CMRR 55* — — db
D303 Response Time(1) TRESP — 300 400* ns VDD = 3.0V to 5.5V
-40° to +85°C
— 400 600* ns VDD = 3.0V to 5.5V
-85° to +125°C
— 400 600* ns VDD = 2.0V to 3.0V
-40° to +85°C
D304 Comparator Mode Change to TMC2OV — 300 10* µs
Output Valid
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.

TABLE 17-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.

Spec
Characteristics Sym Min Typ Max Units Comments
No.
D310 Resolution VRES — — VDD/24 LSb Low Range (VRR = 1)
VDD/32 LSb High Range (VRR = 0)
D311 Absolute Accuracy VRAA — — 1/4(2)* LSb Low Range (VRR = 1)
— — 1/2(2)* LSb High Range (VRR = 0)
D312 Unit Resistor Value (R) VRUR — 2k* — Ω
(1)
D313 Settling Time TSET — — 10* µs
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
2: When VDD is between 2.0V and 3.0V the VREF output voltage levels on RA2 described by the
equation:[VDD/2 ± (3-VDD)/2] may cause the Absolute Accuracy (VRAA) of the VREF output signal on RA2 to
be greater than the stated max.


PIC16F627A/628A/648A
17.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT osc OSC1
io I/O port t0 T0CKI
mc MCLR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-Impedance

FIGURE 17-3: LOAD CONDITIONS

LOAD CONDITION 1 LOAD CONDITION 2

VDD/2

RL

CL CL
PIN PIN

VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output


PIC16F627A/628A/648A
17.6 Timing Diagrams and Specifications

FIGURE 17-4: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1

OSC1
1 3 3
4 4
2

CLKOUT

TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Fosc External CLKIN Frequency(1) DC — 4 MHz XT and RC Osc mode,
VDD = 5.0 V
DC — 20 MHz HS, EC Osc mode
DC — 200 kHz LP Osc mode
Oscillator Frequency(1) — — 4 MHz RC Osc mode, VDD = 5.0V
0.1 — 4 MHz XT Osc mode
1 — 20 MHz HS Osc mode
— — 200 kHz LP Osc mode
— 4 — MHz INTOSC mode (fast)
— 37 — kHz INTOSC mode (slow)
1 Tosc External CLKIN Period(1) 250 — — ns XT and RC Osc mode
50 — — ns HS, EC Osc mode
5 — — µs LP Osc mode
Oscillator Period(1) 250 — — ns RC Osc mode
250 — 10,000 ns XT Osc mode
50 — 1,000 ns HS Osc mode
5 — — µs LP Osc mode
— 250 — ns INTOSC mode (fast)
— 27 — µs INTOSC mode (slow)
2 Tcy Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC
3 TosL, External CLKIN (OSC1) High 100* — — ns XT oscillator, TOSC L/H duty
TosH External CLKIN Low cycle
4 RC External Biased RC Fre- 10 kHz* — 4 MHz — VDD = 5.0V
quency
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note: Instruction cycle period (Tcy) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max” cycle time
limit is “DC” (no clock) for all devices.


PIC16F627A/628A/648A
TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS
Parameter
Sym Characteristic Min Typ Max Units Conditions
No.

F10 FIOSC Oscillator Center frequency — 4 — MHz
F13 ∆IOSC Oscillator Stability (jitter) — — ±1 % VDD = 3.5 V, 25°C
— — ±2 % 2.0 V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
— — ±5 % 2.0 V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (IND)
-40°C ≤ TA ≤ +125°C (EXT)
F14 TIOSCST Oscillator Wake-up from Sleep — 6 TBD µs VDD = 2.0V, -40°C to +85°C
start-up time — 4 TBD µs VDD = 3.0V, -40°C to +85°C
— 3 TBD µs VDD = 5.0V, -40°C to +85°C

FIGURE 17-5: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3

OSC1
11
10
22
CLKOUT 23

13 12
19 18
14 16

I/O PIN
(INPUT)

17 15

I/O PIN NEW VALUE
OLD VALUE
(OUTPUT)

20, 21


PIC16F627A/628A/648A
TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
Sym Characteristic Min Typ† Max Units
No.

10 TosH2ckL OSC1↑ to CLKOUT↓ PIC16F62X — 75 200* ns
10A PIC16LF62X — — 400* ns
11 TosH2ckH OSC1↑ to CLKOUT↑ PIC16F62X — 75 200* ns
11A PIC16LF62X — — 400* ns
12 TckR CLKOUT rise time PIC16F62X — 35 100* ns
12A PIC16LF62X — — 200* ns
13 TckF CLKOUT fall time PIC16F62X — 35 100* ns
13A PIC16LF62X — — 200* ns
14 TckL2ioV CLKOUT ↓ to Port out valid — — 20* ns
15 TioV2ckH Port in valid before CLKOUT ↑ PIC16F62X Tosc+200 ns* — — ns
PIC16LF62X Tosc+400 ns* — — ns
16 TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns
17 TosH2ioV OSC1↑ (Q1 cycle) to PIC16F62X — 50 150* ns
Port out valid PIC16LF62X — — 300* ns
18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid 100* — — ns
(I/O in hold time) 200*
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD

MCLR

30
Internal
POR

33
PWRT
Time out
32

OST
Time out

Internal
RESET

Watchdog
Timer
RESET
31
34 34

I/O Pins


PIC16F627A/628A/648A
FIGURE 17-7: BROWN-OUT DETECT TIMING

VDD VBOR

35

TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.

30 TmcL MCLR Pulse Width (low) 2000 — — ns VDD = 5V, -40°C to +85°C
TBD TBD TBD ms Extended temperature
31 Twdt Watchdog Timer Time out Period 7* 18 33* ms VDD = 5V, -40°C to +85°C
(No Prescaler) TBD TBD TBD ms Extended temperature
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5V, -40°C to +85°C
TBD TBD TBD ms Extended temperature

34 TIOZ I/O Hi-impedance from MCLR Low — — 2.0* µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100* — — µs VDD ≤ VBOR (D005)
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

40 41

42

RB6/T1OSO/T1CKI

45 46

47 48

TMR0 OR
TMR1


PIC16F627A/628A/648A
TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns
42 Tt0P T0CKI Period Greater of: — — ns N = prescale
TCY + 40* value (2, 4, ...,
N 256)
45 Tt1H T1CKI High Synchronous, No Prescaler 0.5TCY + 20* — — ns
Time Synchronous, PIC16F62X 15* — — ns
with Prescaler PIC16LF62X 25* — — ns
Asynchronous PIC16F62X 30* — — ns
PIC16LF62X 50* — — ns
46 Tt1L T1CKI Low Synchronous, No Prescaler 0.5TCY + 20* — — ns
Time Synchronous, PIC16F62X 15* — — ns
with Prescaler PIC16LF62X 25* — — ns
PIC16LF62X 50* — — ns
47 Tt1P T1CKI input Synchronous PIC16F62X Greater of: — — ns N = prescale
period TCY + 40* value (1, 2, 4, 8)
N
PIC16LF62X Greater of: — — —
TCY + 40*
N
PIC16LF62X 100* — — ns
Ft1 Timer1 oscillator input frequency range — 32.7(1) — kHz
(oscillator enabled by setting bit T1OSCEN)
48 TCKEZt Delay from external clock edge to timer 2Tosc — 7Tosc —
mr1 increment
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This oscillator is intended to work only with 32.768 kHz watch crystals and their manufactured tolerances.
Higher value crystal frequencies may not be compatible with this crystal driver.

FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS

RB3/CCP1

(CAPTURE MODE)

50 51

52

RB3/CCP1

(COMPARE OR PWM MODE)

53 54


PIC16F627A/628A/648A
TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
50 TccL CCP No Prescaler 0.5TCY + 20* — — ns
input low time PIC16F62X 10* — — ns
With Prescaler PIC16LF62X 20* — — ns
51 TccH CCP No Prescaler 0.5TCY + 20* — — ns
input high time PIC16F62X 10* — — ns
With Prescaler PIC16LF62X 20* — — ns
52 TccP CCP input period 3TCY + 40* — — ns N = prescale
N value (1,4 or 16)
53 TccR CCP output rise time PIC16F62X 10 25* ns
PIC16LF62X 25 45* ns
54 TccF CCP output fall time PIC16F62X 10 25* ns
PIC16LF62X 25 45* ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

FIGURE 17-10: TIMER0 CLOCK TIMING

RA4/T0CKI

40 41

42

TMR0

TABLE 17-10: TIMER0 CLOCK REQUIREMENTS
Parameter
No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns
42 Tt0P T0CKI Period TCY + 40* — — ns N = prescale value
N (1, 2, 4, ..., 256)
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Not Available at this time.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
19.0 PACKAGING INFORMATION
19.1 Package Marking Information

18-LEAD PDIP (.300") EXAMPLE

XXXXXXXXXXXXXX PIC16F627A-I/P
XXXXXXXXXXXXXX
YYWWNNN 0210017

18-LEAD SOIC (.300") EXAMPLE
XXXXXXXXXXXX PIC16F628A
XXXXXXXXXXXX -E/SO
XXXXXXXXXXXX
YYWWNNN 0210017

20-LEAD SSOP EXAMPLE
XXXXXXXXXXX PIC16F648A
XXXXXXXXXXX -I/SS
YYWWNNN 0210017

28-LEAD QFN EXAMPLE

XXXXXXXX 16F628A
XXXXXXXX -I/ML
YYWWNNN 0210017

Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried
over to the next line thus limiting the number of available characters for customer specific
information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code.
For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.


PIC16F627A/628A/648A
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n 1 α

E A2

A

c L

A1
B1
β
B p
eB

Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 18 18
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .890 .898 .905 22.61 22.80 22.99
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007


PIC16F627A/628A/648A
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E
p
E1

D

2
B n 1

h
α

45°

c
A A2

φ
β L A1

Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Overall Length D .446 .454 .462 11.33 11.53 11.73
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .012 0.23 0.27 0.30
Lead Width B .014 .017 .020 0.36 0.42 0.51
Notes:
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051


PIC16F627A/628A/648A
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

E

E1
p

D

B 2
n 1

α

c
A A2

φ

L A1
β

Pitch p .026 0.65
Overall Height A .068 .073 .078 1.73 1.85 1.98
Standoff § A1 .002 .006 .010 0.05 0.15 0.25
Overall Width E .299 .309 .322 7.59 7.85 8.18
Overall Length D .278 .284 .289 7.06 7.20 7.34
Foot Length L .022 .030 .037 0.56 0.75 0.94
Lead Thickness c .004 .007 .010 0.10 0.18 0.25
Foot Angle φ 0 4 8 0.00 101.60 203.20
Lead Width B .010 .013 .015 0.25 0.32 0.38
Notes:
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072


PIC16F627A/628A/648A
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN)

E EXPOSED
METAL
E1 PADS

Q

D1 D D2
p

2
1 B

n
R
E2
CH x 45 L
TOP VIEW BOTTOM VIEW

α

A2
A
A1

A3

Units INCHES MILLIMETERS*
Pitch p .026 BSC 0.65 BSC
Overall Height A .033 .039 0.85 1.00
Molded Package Thickness A2 .026 .031 0.65 0.80
Standoff A1 .000 .0004 .002 0.00 0.01 0.05
Base Thickness A3 .008 REF. 0.20 REF.
Overall Width E .236 BSC 6.00 BSC
Molded Package Width E1 .226 BSC 5.75 BSC
Exposed Pad Width E2 .140 .146 .152 3.55 3.70 3.85
Overall Length D .236 BSC 6.00 BSC
Molded Package Length D1 .226 BSC 5.75 BSC
Exposed Pad Length D2 .140 .146 .152 3.55 3.70 3.85
Lead Width B .009 .011 .014 0.23 0.28 0.35
Lead Length L .020 .024 .030 0.50 0.60 0.75
Tie Bar Width R .005 .007 .010 0.13 0.17 0.23
Tie Bar Length Q .012 .016 .026 0.30 0.40 0.65
Chamfer CH .009 .017 .024 0.24 0.42 0.60
Mold Draft Angle Top α 12 12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: M0-220
Drawing No. C04-114


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
APPENDIX A: DATA SHEET APPENDIX B: DEVICE
REVISION HISTORY DIFFERENCES
Revision A The differences between the PIC16F627A/628A/648A
devices listed in this data sheet are shown in Table B-1.
This is a new data sheet.
TABLE B-1: DEVICE DIFFERENCES
Revision B
Memory
Revised 28-Pin QFN Pin Diagram
Revised Figure 5-4 Block Diagram Device Flash RAM EEPROM
Revised Register 7-1 TMR1ON Program Data Data
Revised Example 13-4 Data EEPROM Refresh
Routine PIC16F627A 1024 x 14 224 x 8 128 x 8
Revised Instruction Set SUBWF, Example 1 PIC16F628A 2048 x 14 224 x 8 128 x 8
Revised DC Characteristics 17-2 and 17-3 PIC16F648A 4096 x 14 256 x 8 256 x 8
Revised Tables 17-4 and 17-6
Corrected Table and Figure numbering in Section 17.0


PIC16F627A/628A/648A
APPENDIX C: DEVICE MIGRATIONS APPENDIX D: MIGRATING FROM
This section describes the functional and electrical OTHER PICmicro
specification differences when migrating between DEVICES
functionally similar devices. (such as from a
This discusses some of the issues in migrating from
PIC16F627 to a PIC16F627A).
other PICmicro devices to the PIC16F627A/628A/648A
C.1 PIC16F627/628 to a PIC16F627A/628A family of devices.
1. ER mode is now RC mode. D.1 PIC16C62X/CE62X to PIC16F627A/628A/
2. Code Protection for the Program Memory has 648A Migration
changed from Code Protect sections of memory
to Code Protect of the whole memory. The See Microchip web site for availability
Configuration bits CP0 and CP1 in the (www.microchip.com).
PIC16F627/628 do not exist in the PIC16F627A/ D.2 PIC16C622A to PIC16F627A/628A/648A
628A. They have been replaced with one Migration
Configuration bit<13> CP.
See Microchip web site for availability
3. “Brown-out Detect (BOD)” terminology has
(www.microchip.com).
changed to “Brown-out Reset (BOR)” to better
represent the function of the Brown-out circuitry.
4. Enabling Brown-out Reset (BOR) does not Note: This device has been designed to perform
automatically enable the Power-up Timer to the parameters of its data sheet. It has
(PWRT) the way it did in the PIC16F627/628. been tested to an electrical specification
5. INTRC is now called INTOSC. designed to determine its conformance
6. Timer1 Oscillator is now designed for with these parameters. Due to process
32.768 kHz operation. In the PIC16F627/628 differences in the manufacture of this
the Timer1 Oscillator was designed to run up to device, this device may have different
200 kHz. performance characteristics than its earlier
7. The Dual Speed Oscillator mode only works in version. These differences may cause this
the INTOSC Oscillator mode. In the PIC16F627/ device to perform differently in your
628 the Dual Speed Oscillator mode worked in application than the earlier version of this
both the INTRC and ER Oscillator modes. device.


PIC16F627A/628A/648A
APPENDIX E: DEVELOPMENT
TOOL VERSION
REQUIREMENTS
This lists the minimum requirements (software/
firmware) of the specified development tool to support
the devices listed in this data sheet.
MPLAB® IDE: TBD
MPLAB® SIMULATOR: TBD
MPLAB® ICE 3000:
PIC16F627A/628A/648A Processor Module:
Part Number - TBD
PIC16F627A/628A/648A Device Adapter:
Socket Part Number
18-pin PDIP TBD
18-pin SOIC TBD
20-pin SSOP TBD
28-pin QFN TBD
MPLAB® ICD: TBD
PRO MATE® II: TBD
PICSTART® Plus: TBD
TM
MPASM Assembler: TBD
MPLAB® C18 C Compiler: TBD

Note: Please read all associated README.TXT
files that are supplied with the develop-
ment tools. These “read me” files will
discuss product support and any known
limitations.


PIC16F627A/628A/648A
NOTES:


PIC16F627A/628A/648A
ON-LINE SUPPORT SYSTEMS INFORMATION AND
Microchip provides on-line support on the Microchip
UPGRADE HOT LINE
World Wide Web site. The Systems Information and Upgrade Line provides
The web site is used by Microchip as a means to make system users a listing of the latest versions of all of
files and information easily available to customers. To Microchip's development systems software products.
view the site, the user must have access to the Internet Plus, this line provides information on how customers
and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line
Internet Explorer. Files are also available for FTP Numbers are:
download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and
Connecting to the Microchip Internet Web Site 1-480-792-7302 for the rest of the world.
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events


PIC16F627A/628A/648A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

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Device: PIC16F627A/628A/648A Literature Number: DS40044B

Questions:

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6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?


PIC16F627A/628A/648A
INDEX CCP1X:CCP1Y Bits.................................................... 55
CCP2CON Register
A CCP2M3:CCP2M0 Bits .............................................. 55
A/D CCP2X:CCP2Y Bits.................................................... 55
Special Event Trigger (CCP)....................................... 57 Clocking Scheme/Instruction Cycle .................................... 13
Absolute Maximum Ratings .............................................. 131 CLRF Instruction............................................................... 115
ADDLW Instruction ........................................................... 113 CLRW Instruction.............................................................. 116
ADDWF Instruction ........................................................... 113 CLRWDT Instruction......................................................... 116
ANDLW Instruction ........................................................... 113 Code Examples
ANDWF Instruction ........................................................... 113 Data EEPROM Refresh Routine ................................ 92
Architectural Overview .......................................................... 9 Code Protection ................................................................ 108
Assembler COMF Instruction.............................................................. 116
MPASM Assembler ................................................... 125 Comparator
Block Diagrams
B I/O Operating Modes .......................................... 62
Baud Rate Error .................................................................. 71 Modified Comparator Output .............................. 64
Baud Rate Formula ............................................................. 71 Comparator Module.................................................... 61
BCF Instruction ................................................................. 114 Configuration .............................................................. 62
Block Diagrams Interrupts .................................................................... 65
Comparator Operation.................................................................... 63
I/O Operating Modes .......................................... 62 Reference ................................................................... 63
Modified Comparator Output .............................. 64 Compare (CCP Module) ..................................................... 56
I/O Ports Block Diagram ............................................................ 56
RB0/INT Pin ........................................................ 37 CCP Pin Configuration ............................................... 57
RB1/RX/DT Pin ................................................... 37 CCPR1H:CCPR1L Registers ..................................... 56
RB2/TX/CK Pin ................................................... 38 Software Interrupt ....................................................... 57
RB3/CCP1 Pin .................................................... 38 Special Event Trigger ................................................. 57
RB4/PGM Pin ..................................................... 39 Timer1 Mode Selection............................................... 57
RB5 Pin............................................................... 40 Configuration Bits ............................................................... 93
RB6/T1OSO/T1CKI Pin ...................................... 41 Crystal Operation................................................................ 95
RB7/T1OSI Pin ................................................... 42
RC Oscillator Mode..................................................... 96 D
USART Receive.......................................................... 79 Data EEPROM Memory...................................................... 89
USART Transmit ......................................................... 77 EECON1 Register ...................................................... 89
BRGH bit ............................................................................. 71 EECON2 Register ...................................................... 89
Brown-Out Detect (BOD) .................................................... 98 Operation During Code Protection ............................. 92
BSF Instruction ................................................................. 114 Reading ...................................................................... 91
BTFSC Instruction............................................................. 114 Spurious Write Protection ........................................... 91
BTFSS Instruction ............................................................. 115 Using .......................................................................... 92
Write Verify ................................................................. 91
C Writing to .................................................................... 91
C Compilers Data Memory Organization................................................. 15
MPLAB C17 .............................................................. 126 DECF Instruction .............................................................. 116
MPLAB C18 .............................................................. 126 DECFSZ Instruction.......................................................... 117
MPLAB C30 .............................................................. 126 Demonstration Boards
CALL Instruction ............................................................... 115 PICDEM 1................................................................. 128
Capture (CCP Module) ....................................................... 56 PICDEM 17............................................................... 129
Block Diagram............................................................. 56 PICDEM 18R ............................................................ 129
CCP Pin Configuration................................................ 56 PICDEM 2 Plus......................................................... 128
CCPR1H:CCPR1L Registers...................................... 56 PICDEM 3................................................................. 128
Changing Between Capture Prescalers...................... 56 PICDEM 4................................................................. 128
Prescaler..................................................................... 56 PICDEM LIN ............................................................. 129
Software Interrupt ....................................................... 56 PICDEM USB ........................................................... 129
Timer1 Mode Selection ............................................... 56 PICDEM.net Internet/Ethernet .................................. 128
Capture/Compare/PWM (CCP)........................................... 55 Development Support ....................................................... 125
Capture Mode. See Capture Development Tool Version Requirements ........................ 157
CCP1 .......................................................................... 55 Device Differences............................................................ 155
CCPR1H Register............................................... 55 Device Migrations ............................................................. 156
CCPR1L Register ............................................... 55 Dual-speed Oscillator Modes.............................................. 97
CCP2 .......................................................................... 55
Compare Mode. See Compare
PWM Mode. See PWM
Timer Resources......................................................... 55
CCP1CON Register
CCP1M3:CCP1M0 Bits ............................................... 55


PIC16F627A/628A/648A
E RRF .......................................................................... 122
EECON1 register ................................................................ 90 SLEEP ...................................................................... 122
EECON2 register ................................................................ 90 SUBLW ..................................................................... 122
SUBWF..................................................................... 123
Errata .................................................................................... 3
Evaluation and Programming Tools .................................. 129 SWAPF ..................................................................... 123
External Crystal Oscillator Circuit........................................ 95 TRIS ......................................................................... 123
XORLW..................................................................... 124
G XORWF .................................................................... 124
General-Purpose Register File............................................ 15 Instruction Set Summary .................................................. 111
INT Interrupt...................................................................... 105
GOTO Instruction .............................................................. 117
INTCON Register................................................................ 24
I Interrupt Sources
Capture Complete (CCP)............................................ 56
I/O Ports .............................................................................. 31
Bi-Directional............................................................... 44 Compare Complete (CCP).......................................... 57
Block Diagrams TMR2 to PR2 Match (PWM) ....................................... 58
Interrupts........................................................................... 104
RB0/INT Pin ........................................................ 37
RB1/RX/DT Pin ................................................... 37 Interrupts, Enable Bits
RB2/TX/CK Pin ................................................... 38 CCP1 Enable (CCP1IE Bit) ........................................ 56
RB3/CCP1 Pin .................................................... 38 Interrupts, Flag Bits
RB4/PGM Pin...................................................... 39 CCP1 Flag (CCP1IF Bit)............................................. 56
RB5 Pin............................................................... 40 IORLW Instruction ............................................................ 119
RB6/T1OSO/T1CKI Pin ...................................... 41 IORWF Instruction ............................................................ 119
RB7/T1OSI Pin ................................................... 42
M
PORTA ........................................................................ 31
PORTB........................................................................ 36 Memory Organization
Programming Considerations ..................................... 44 Data EEPROM Memory.................................. 89, 91, 92
Successive Operations ............................................... 44 Migrating from other PICmicro Devices ............................ 156
TRISA ......................................................................... 31 MOVF Instruction.............................................................. 119
TRISB ......................................................................... 36 MOVLW Instruction........................................................... 119
ID Locations ...................................................................... 108 MOVWF Instruction .......................................................... 120
INCF Instruction ................................................................ 118 MPLAB ASM30 Assembler, Linker, Librarian ................... 126
INCFSZ Instruction............................................................ 118 MPLAB ICD 2 In-Circuit Debugger ................................... 127
In-Circuit Serial Programming ........................................... 109 MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
Indirect Addressing, INDF and FSR Registers.................... 28 ulator................................................................................. 127
Instruction Flow/Pipelining .................................................. 13 MPLAB ICE 4000 High-Performance Universal In-Circuit Em-
Instruction Set ulator................................................................................. 127
ADDLW ..................................................................... 113 MPLAB Integrated Development Environment Software.. 125
ADDWF ..................................................................... 113 MPLAB PM3 Device Programmer .................................... 127
ANDLW ..................................................................... 113 MPLINK Object Linker/MPLIB Object Librarian ................ 126
ANDWF ..................................................................... 113
N
BCF ........................................................................... 114
BSF ........................................................................... 114 NOP Instruction ................................................................ 120
BTFSC ...................................................................... 114
O
BTFSS ...................................................................... 115
CALL ......................................................................... 115 OPTION Instruction .......................................................... 120
CLRF......................................................................... 115 OPTION Register................................................................ 23
CLRW........................................................................ 116 Oscillator Configurations..................................................... 95
CLRWDT................................................................... 116 Oscillator Start-up Timer (OST) .......................................... 98
COMF ....................................................................... 116
P
DECF ........................................................................ 116
DECFSZ.................................................................... 117 Package Marking Information ........................................... 149
GOTO........................................................................ 117 Packaging Information ...................................................... 149
INCF.......................................................................... 118 PCL and PCLATH............................................................... 28
INCFSZ ..................................................................... 118 Stack ........................................................................... 28
IORLW....................................................................... 119 PCON Register ................................................................... 27
IORWF ...................................................................... 119 PICkit 1 Flash Starter Kit .................................................. 129
MOVF........................................................................ 119 PICSTART Plus Development Programmer..................... 128
MOVLW..................................................................... 119 PIE1 Register...................................................................... 25
MOVWF .................................................................... 120 Pin Functions
NOP .......................................................................... 120 RC6/TX/CK ........................................................... 69–86
OPTION .................................................................... 120 RC7/RX/DT........................................................... 69–86
RETFIE ..................................................................... 120 PIR1 Register ..................................................................... 26
RETLW...................................................................... 121 Port RB Interrupt............................................................... 105
RETURN ................................................................... 121 PORTA ............................................................................... 31
RLF ........................................................................... 121 PORTB ............................................................................... 36


PIC16F627A/628A/648A
Power Control/Status Register (PCON) .............................. 99 Timer0 Module............................................................ 45
Power-Down Mode (SLEEP) ............................................ 107 Timer1
Power-On Reset (POR) ...................................................... 98 Asynchronous Counter Mode ..................................... 50
Power-up Timer (PWRT) .................................................... 98 Capacitor Selection .................................................... 51
PR2 Register................................................................. 52, 58 External Clock Input ................................................... 49
PRO MATE II Universal Device Programmer ................... 127 External Clock Input Timing........................................ 50
Program Memory Organization ........................................... 15 Oscillator..................................................................... 51
PWM (CCP Module) ........................................................... 58 Prescaler .............................................................. 49, 51
Block Diagram............................................................. 58 Resetting Timer1 ........................................................ 51
Simplified PWM .................................................. 58 Resetting Timer1 Registers ........................................ 51
CCPR1H:CCPR1L Registers...................................... 58 Special Event Trigger (CCP) ...................................... 57
Duty Cycle................................................................... 59 Synchronized Counter Mode ...................................... 49
Example Frequencies/Resolutions ............................. 59 Timer Mode................................................................. 49
Period.......................................................................... 58 TMR1H ....................................................................... 50
Set-Up for PWM Operation ......................................... 59 TMR1L........................................................................ 50
TMR2 to PR2 Match ................................................... 58 Timer2
Block Diagram ............................................................ 52
Q Postscaler ................................................................... 52
Q-Clock ............................................................................... 59 PR2 register................................................................ 52
Quick-Turnaround-Production (QTP) Devices ...................... 7 Prescaler .............................................................. 52, 59
Timer2 Module............................................................ 52
R TMR2 output ............................................................... 52
RC Oscillator ....................................................................... 96 TMR2 to PR2 Match Interrupt..................................... 58
RC Oscillator Mode Timing Diagrams
Block Diagram............................................................. 96 Timer0....................................................................... 143
Registers Timer1....................................................................... 143
Maps USART
PIC16F627A ................................................. 16, 17 Asynchronous Receiver...................................... 80
PIC16F628A ................................................. 16, 17 USART Asynchronous Master Transmission ............. 77
Reset................................................................................... 97 USART Asynchronous Reception .............................. 80
RETFIE Instruction............................................................ 120 USART RX Pin Sampling ..................................... 75, 76
RETLW Instruction ............................................................ 121 USART Synchronous Reception ................................ 86
RETURN Instruction ......................................................... 121 USART Synchronous Transmission ........................... 84
Revision History ................................................................ 155 Timing Diagrams and Specifications ................................ 140
RLF Instruction.................................................................. 121 TMR0 Interrupt.................................................................. 105
RRF Instruction ................................................................. 122 TMR1CS bit ........................................................................ 48
TMR1ON bit........................................................................ 48
S TMR2ON bit........................................................................ 53
Serial Communication Interface (SCI) Module, See USART TOUTPS0 bit ...................................................................... 53
Serialized Quick-Turnaround-Production (SQTP) Devices ... 7 TOUTPS1 bit ...................................................................... 53
SLEEP Instruction ............................................................. 122 TOUTPS2 bit ...................................................................... 53
Software Simulator (MPLAB SIM)..................................... 126 TOUTPS3 bit ...................................................................... 53
Software Simulator (MPLAB SIM30)................................. 126 TRIS Instruction ................................................................ 123
Special Event Trigger. See Compare TRISA ................................................................................. 31
Special Features of the CPU .............................................. 93 TRISB ................................................................................. 36
Special Function Registers ................................................. 18
Status Register ................................................................... 22 U
SUBLW Instruction............................................................ 122 Universal Synchronous Asynchronous Receiver Transmitter
SUBWF Instruction ........................................................... 123 (USART) ............................................................................. 69
SWAPF Instruction............................................................ 123 Asynchronous Receiver
Setting Up Reception.......................................... 82
T Asynchronous Receiver Mode
T1CKPS0 bit ....................................................................... 48 Address Detect ................................................... 82
T1CKPS1 bit ....................................................................... 48 Block Diagram .................................................... 82
T1OSCEN bit ...................................................................... 48 USART
T1SYNC bit ......................................................................... 48 Asynchronous Mode................................................... 76
T2CKPS0 bit ....................................................................... 53 Asynchronous Receiver.............................................. 79
T2CKPS1 bit ....................................................................... 53 Asynchronous Reception............................................ 81
Timer0 Asynchronous Transmission....................................... 77
Block Diagrams Asynchronous Transmitter.......................................... 76
Timer0/WDT ....................................................... 46 Baud Rate Generator (BRG) ...................................... 71
External Clock Input.................................................... 45 Block Diagrams
Interrupt....................................................................... 45 Transmit.............................................................. 77
Prescaler..................................................................... 46 USART Receive ................................................. 79
Switching Prescaler Assignment................................. 47 BRGH bit .................................................................... 71


PIC16F627A/628A/648A
Sampling ......................................................... 72, 73, 74
Synchronous Master Mode ......................................... 83
Synchronous Master Reception .................................. 85
Synchronous Master Transmission............................. 83
Synchronous Slave Mode ........................................... 86
Synchronous Slave Reception .................................... 87
Synchronous Slave Transmit ...................................... 86

V
Voltage Reference
Configuration............................................................... 67
Voltage Reference Module.......................................... 67

W
Watchdog Timer (WDT) .................................................... 106
WWW, On-Line Support........................................................ 3

X
XORLW Instruction ........................................................... 124
XORWF Instruction ........................................................... 124


PIC16F627A/628A/648A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC16F627A - E/P 301 = Extended Temp.,
Range PDIP package, 20 MHz, normal VDD limits,
QTP pattern #301.
b) PIC16LF627A - I/SO = Industrial Temp.,
Device PIC16F627A/628A/648A:Standard VDD range 3.0V to 5.5V SOIC package, 20 MHz, extended VDD limits.
PIC16F627A/628A/648ATVDD range 3.0V to 5.5V (Tape
and Reel)
PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V
PIC16LF627A/628A/648AT:VDD range 2.0V to 5.5V (Tape
and Reel)

Temperature Range I = -40°C to +85°C
E = -40°C to +125°C

Package P = PDIP
SO = SOIC (Gull Wing, 300 mil body)
SS = SSOP (209 mil)
ML = QFN (28 Lead)

Pattern 3-Digit Pattern Code for QTP (blank otherwise).

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.

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Data Sheets
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2 Lan Drive, Suite 120 Unit 28F, World Trade Plaza Kaohsiung 806, Taiwan
Westford, MA 01886 No. 71 Wusi Road Tel: 886-7-536-4818
Tel: 978-692-3848 Fuzhou 350001, China Fax: 886-7-536-4803
Fax: 978-692-3821 Tel: 86-591-7503506 Taiwan
Chicago Fax: 86-591-7503521 Taiwan Branch
333 Pierce Road, Suite 180 China - Hong Kong SAR 11F-3, No. 207
Itasca, IL 60143 Unit 901-6, Tower 2, Metroplaza Tung Hua North Road
Tel: 630-285-0071 223 Hing Fong Road Taipei, 105, Taiwan
Fax: 630-285-0075 Kwai Fong, N.T., Hong Kong Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Dallas Tel: 852-2401-1200
Fax: 852-2401-3431
EUROPE
4570 Westgrove Drive, Suite 160
China - Shanghai Austria
Addison, TX 75001
Tel: 972-818-7423 Room 701, Bldg. B Durisolstrasse 2
Fax: 972-818-2924 Far East International Plaza A-4600 Wels
No. 317 Xian Xia Road Austria
Detroit Shanghai, 200051 Tel: 43-7242-2244-399
Tri-Atria Office Building Tel: 86-21-6275-5700 Fax: 43-7242-2244-393
32255 Northwestern Highway, Suite 190 Fax: 86-21-6275-5060 Denmark
Farmington Hills, MI 48334 Regus Business Centre
Tel: 248-538-2250 China - Shenzhen
Lautrup hoj 1-3
Fax: 248-538-2260 Rm. 1812, 18/F, Building A, United Plaza
Ballerup DK-2750 Denmark
No. 5022 Binhe Road, Futian District
Kokomo Tel: 45-4420-9895 Fax: 45-4420-9910
Shenzhen 518033, China
2767 S. Albright Road Tel: 86-755-82901380 France
Kokomo, IN 46902 Fax: 86-755-8295-1393 Parc d’Activite du Moulin de Massy
Tel: 765-864-8360 China - Shunde 43 Rue du Saule Trapu
Fax: 765-864-8387 Batiment A - ler Etage
Room 401, Hongjian Building, No. 2
91300 Massy, France
Los Angeles Fengxiangnan Road, Ronggui Town, Shunde
Tel: 33-1-69-53-63-20
18201 Von Karman, Suite 1090 District, Foshan City, Guangdong 528303, China
Fax: 33-1-69-30-90-79
Irvine, CA 92612 Tel: 86-757-28395507 Fax: 86-757-28395571
Tel: 949-263-1888 Germany
China - Qingdao
Fax: 949-263-1338 Steinheilstrasse 10
Rm. B505A, Fullhope Plaza, D-85737 Ismaning, Germany
San Jose No. 12 Hong Kong Central Rd. Tel: 49-89-627-144-0
1300 Terra Bella Avenue Qingdao 266071, China Fax: 49-89-627-144-44
Mountain View, CA 94043 Tel: 86-532-5027355 Fax: 86-532-5027205
Italy
Tel: 650-215-1444 India Via Quasimodo, 12
Fax: 650-961-0286 Divyasree Chambers 20025 Legnano (MI)
1 Floor, Wing A (A3/A4) Milan, Italy
Toronto No. 11, O’Shaugnessey Road
6285 Northam Drive, Suite 108 Tel: 39-0331-742611
Bangalore, 560 025, India Fax: 39-0331-466781
Mississauga, Ontario L4V 1X5, Canada Tel: 91-80-2290061 Fax: 91-80-2290062
Tel: 905-673-0699 Netherlands
Japan
Fax: 905-673-6509 P. A. De Biesbosch 14
Benex S-1 6F NL-5152 SC Drunen, Netherlands
3-18-20, Shinyokohama Tel: 31-416-690399
ASIA/PACIFIC Kohoku-Ku, Yokohama-shi Fax: 31-416-690340
Australia Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122 United Kingdom
Suite 22, 41 Rawson Street 505 Eskdale Road
Epping 2121, NSW Winnersh Triangle
Australia Wokingham
Tel: 61-2-9868-6733 Berkshire, England RG41 5TU
Fax: 61-2-9868-6755 Tel: 44-118-921-5869
Fax: 44-118-921-5820

01/26/04


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