Pic18f458
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This document provides details on the PIC18FXX8 microcontroller family, including its high-performance RISC CPU, advanced analog and peripheral features, CAN bus module, and special microcontroller features such as code protection, sleep mode, and oscillator options. It highlights specifications such as its 10 MIPS operation, 10-bit A/D converter, programmable timers and PWM, MSSP, and compliance with ISO CAN standards. The document is a data sheet that concisely outlines the technical specifications and capabilities of the PIC18FXX8 microcontroller family.
![PIC18FXX8
15.4 PWM Mode 15.4.1 PWM PERIOD
In Pulse-Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2
produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the
the CCP1 pin is multiplexed with the PORTC data latch, following formula.
the TRISC<2> bit must be cleared to make the CCP1
pin an output. EQUATION 15-1:
Note: Clearing the CCP1CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC •
the CCP1 PWM output latch to the default (TMR2 Prescale Value)
low level. This is not the PORTC I/O data
latch. PWM frequency is defined as 1/[PWM period].
Figure 15-3 shows a simplified block diagram of the When TMR2 is equal to PR2, the following three events
CCP module in PWM mode. occur on the next increment cycle:
For a step-by-step procedure on how to set up the CCP • TMR2 is cleared
module for PWM operation, see Section 15.4.3
• The CCP1 pin is set (exception: if PWM duty
“Setup for PWM Operation”.
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
FIGURE 15-3: SIMPLIFIED PWM BLOCK
CCPR1H
DIAGRAM
Note: The Timer2 postscaler (see Section 13.0
Duty Cycle Registers CCP1CON<5:4> “Timer2 Module”) is not used in the
determination of the PWM frequency. The
CCPR1L (Master) postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCPR1H (Slave) 15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
Comparator R Q
CCPR1L register and to the CCP1CON<5:4> bits. Up
RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains
TMR2 (Note 1) the eight MSbs and the CCP1CON<5:4> contains the
S two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
Comparator TRISC<2>
used to calculate the PWM duty cycle in time.
Clear Timer,
set CCP1 pin and
latch D.C.
PR2 EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, TOSC • (TMR2 Prescale Value)
or 2 bits of the prescaler, to create 10-bit time base.
A PWM output (Figure 15-4) has a time base (period) CCPR1L and CCP1CON<5:4> can be written to at any
and a time that the output stays high (duty cycle). The time, but the duty cycle value is not latched into
frequency of the PWM is the inverse of the period CCPR1H until after a match between PR2 and TMR2
(1/period). occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
FIGURE 15-4: PWM OUTPUT The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
Period double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
Duty Cycle
the TMR2 prescaler, the CCP1 pin is cleared.
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS41159D-page 128 2004 Microchip Technology Inc.](https://image.slidesharecdn.com/pic18f458-120328115312-phpapp01/85/Pic18f458-130-320.jpg)
![PIC18FXX8
18.1 USART Baud Rate Generator Example 18-1 shows the calculation of the baud rate
(BRG) error for the following conditions:
FOSC = 16 MHz
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated Desired Baud Rate = 9600
8-bit Baud Rate Generator. The SPBRG register BRGH = 0
controls the period of a free running, 8-bit timer. In SYNC = 0
Asynchronous mode, bit BRGH (TXSTA register) also It may be advantageous to use the high baud rate
controls the baud rate. In Synchronous mode, bit (BRGH = 1) even for slower baud clocks. This is
BRGH is ignored. Table 18-1 shows the formula for because the FOSC/(16(X + 1)) equation can reduce the
computation of the baud rate for different USART baud rate error in some cases.
modes which only apply in Master mode (internal
clock). Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
Given the desired baud rate and FOSC, the nearest BRG does not wait for a timer overflow before
integer value for the SPBRG register can be calculated outputting the new baud rate.
using the formula in Table 18-1. From this, the error in
baud rate can be determined. 18.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
Desired Baud Rate = FOSC/(64 (X + 1))
Solving for X:
X = ((FOSC/Desired Baud Rate)/64) – 1
X = ((16000000/9600)/64) – 1
X = [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
TABLE 18-1: BAUD RATE FORMULA
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0 (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) Baud Rate = FOSC/(16 (X + 1))
1 (Synchronous) Baud Rate = FOSC/(4 (X + 1)) NA
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
2004 Microchip Technology Inc. DS41159D-page 185](https://image.slidesharecdn.com/pic18f458-120328115312-phpapp01/85/Pic18f458-187-320.jpg)
![PIC18FXX8
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 20-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
• CHOLD = 120 pF
• Rs = 2.5 kΩ
• Conversion Error ≤ 1/2 LSb
• VDD = 5V → Rss = 7 kΩ
• Temperature = 50°C (system max.)
• VHOLD = 0V @ time = 0
EQUATION 20-1: ACQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
EQUATION 20-2: A/D MINIMUM CHARGING TIME
VHOLD = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS)))
or
Tc = -(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 20-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ = 2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]
TC = -CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ = 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
Note: When using external voltage references with the A/D converter, the source impedance of the external
voltage references must be less than 20Ω to obtain the specified A/D resolution. Higher reference source
impedances will increase both offset and gain errors. Resistive voltage dividers will not provide a sufficiently
low source impedance.
To maintain the best possible performance in A/D conversions, external VREF inputs should be buffered with
an operational amplifier or other low output impedance circuit.
2004 Microchip Technology Inc. DS41159D-page 245](https://image.slidesharecdn.com/pic18f458-120328115312-phpapp01/85/Pic18f458-247-320.jpg)
Pic18f458
- 1. PIC18FXX8 Data Sheet 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module 2004 Microchip Technology Inc. DS41159D
- 2. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, SmartSensor and The Embedded Control Solutions Company MERCHANTABILITY OR FITNESS FOR PURPOSE. are registered trademarks of Microchip Technology Microchip disclaims all liability arising from this information and Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, Migratable Memory, MPASM, rights. MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41159D-page ii 2004 Microchip Technology Inc.
- 3. PIC18FXX8 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN High-Performance RISC CPU: Advanced Analog Features: • Linear program memory addressing up to • 10-bit, up to 8-channel Analog-to-Digital Converter 2 Mbytes module (A/D) with: • Linear data memory addressing to 4 Kbytes - Conversion available during Sleep • Up to 10 MIPS operation - Up to 8 channels available • DC – 40 MHz clock input • Analog Comparator module: • 4 MHz-10 MHz oscillator/clock input with - Programmable input and output multiplexing PLL active • Comparator Voltage Reference module • 16-bit wide instructions, 8-bit wide data path • Programmable Low-Voltage Detection (LVD) module: • Priority levels for interrupts - Supports interrupt-on-Low-Voltage Detection • 8 x 8 Single-Cycle Hardware Multiplier • Programmable Brown-out Reset (BOR) Peripheral Features: CAN bus Module Features: • High current sink/source 25 mA/25 mA • Complies with ISO CAN Conformance Test • Three external interrupt pins • Message bit rates up to 1 Mbps • Timer0 module: 8-bit/16-bit timer/counter with • Conforms to CAN 2.0B Active Spec with: 8-bit programmable prescaler - 29-bit Identifier Fields • Timer1 module: 16-bit timer/counter - 8-byte message length • Timer2 module: 8-bit timer/counter with 8-bit - 3 Transmit Message Buffers with prioritization period register (time base for PWM) - 2 Receive Message Buffers • Timer3 module: 16-bit timer/counter - 6 full, 29-bit Acceptance Filters • Secondary oscillator clock option – Timer1/Timer3 - Prioritization of Acceptance Filters • Capture/Compare/PWM (CCP) modules; - Multiple Receive Buffers for High Priority CCP pins can be configured as: Messages to prevent loss due to overflow - Capture input: 16-bit, max resolution 6.25 ns - Advanced Error Management Features - Compare: 16-bit, max resolution 100 ns (TCY) - PWM output: PWM resolution is 1 to 10-bit Special Microcontroller Features: Max. PWM freq. @:8-bit resolution = 156 kHz • Power-on Reset (POR), Power-up Timer (PWRT) 10-bit resolution = 39 kHz and Oscillator Start-up Timer (OST) • Enhanced CCP module which has all the features • Watchdog Timer (WDT) with its own on-chip RC of the standard CCP module, but also has the oscillator following features for advanced motor control: • Programmable code protection - 1, 2 or 4 PWM outputs • Power-saving Sleep mode - Selectable PWM polarity • Selectable oscillator options, including: - Programmable PWM dead time - 4x Phase Lock Loop (PLL) of primary oscillator • Master Synchronous Serial Port (MSSP) with two - Secondary Oscillator (32 kHz) clock input modes of operation: • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins - 3-wire SPI™ (Supports all 4 SPI modes) - I2C™ Master and Slave mode Flash Technology: • Addressable USART module: • Low-power, high-speed Enhanced Flash technology - Supports interrupt-on-address bit • Fully static design • Wide operating voltage range (2.0V to 5.5V) • Industrial and Extended temperature ranges 2004 Microchip Technology Inc. DS41159D-page 1
- 4. PIC18FXX8 Comparators Program Memory Data Memory MSSP 10-bit CCP/ Timers Device Flash # Single-Word SRAM EEPROM I/O A/D ECCP Master USART SPI™ 8/16-bit (bytes) Instructions (bytes) (bytes) (ch) (PWM) I2C™ PIC18F248 16K 8192 768 256 22 5 — 1/0 Y Y Y 1/3 PIC18F258 32K 16384 1536 256 22 5 — 1/0 Y Y Y 1/3 PIC18F448 16K 8192 768 256 33 8 2 1/1 Y Y Y 1/3 PIC18F458 32K 16384 1536 256 33 8 2 1/1 Y Y Y 1/3 Pin Diagrams PDIP MCLR/VPP 1 40 RB7/PGD RA0/AN0/CVREF 2 39 RB6/PGC RA1/AN1 3 38 RB5/PGM RA2/AN2/VREF- 4 37 RB4 RA3/AN3/VREF+ 5 36 RB3/CANRX RA4/T0CKI 6 35 RB2/CANTX/INT2 RA5/AN4/SS/LVDIN 7 34 RB1/INT1 PIC18F458 RE0/AN5/RD 8 PIC18F448 33 RB0/INT0 RE1/AN6/WR/C1OUT 9 32 VDD RE2/AN7/CS/C2OUT 10 31 VSS VDD 11 30 RD7/PSP7/P1D VSS 12 29 RD6/PSP6/P1C OSC1/CLKI 13 28 RD5/PSP5/P1B OSC2/CLKO/RA6 14 27 RD4/PSP4/ECCP1/P1A RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0/C1IN+ 19 22 RD3/PSP3/C2IN- RD1/PSP1/C1IN- 20 21 RD2/PSP2/C2IN+ RA0/AN0/CVREF PLCC RA3/AN3/VREF+ RA2/AN2/VREF- MCLR/VPP RB5/PGM RB7/PGD RB6/PGC RA1/AN1 RB4 NC NC 6 5 4 3 2 1 44 43 42 41 40 RA4/T0CKI 7 39 RB3/CANRX RA5/AN4/SS/LVDIN 8 38 RB2/CANTX/INT2 RE0/AN5/RD 9 37 RB1/INT1 RE1/AN6/WR/C1OUT 10 36 RB0/INT0 RE2/AN7/CS/C2OUT 11 PIC18F448 35 VDD VDD 12 34 VSS VSS 13 PIC18F458 33 RD7/PSP7/P1D OSC1/CLKI 14 32 RD6/PSP6/P1C OSC2/CLKO/RA6 15 31 RD5/PSP5/P1B RC0/T1OSO/T1CK1 16 30 RD4/PSP4/ECCP1/P1A NC 17 29 RC7/RX/DT 20 21 22 23 26 24 27 18 25 28 19 RC1/T1OSI RD0/PSP0/C1IN+ RD2/PSP2/C2IN+ NC RC4/SDI/SDA RC6/TX/CK RD1/PSP1/C1IN- RD3/PSP3/C2IN- RC2/CCP1 RC3/SCK/SCL RC5/SDO DS41159D-page 2 2004 Microchip Technology Inc.
- 5. PIC18FXX8 Pin Diagrams (Continued) TQFP RD2/PSP2/C2IN+ RD0/PSP0/C1IN+ RD1/PSP1/C1IN- RD3/PSP3/C2IN- RC3/SCK/SCL RC4/SDI/SDA RC6/TX/CK RC1/T1OSI RC2/CCP1 RC5/SDO NC 44 43 42 41 40 39 38 37 36 35 34 RC7/RX/DT 1 33 NC RD4/PSP4/ECCP1/P1A 2 32 RC0/T1OSO/T1CKI RD5/PSP5/P1B 3 31 OSC2/CLKO/RA6 RD6/PSP6/P1C 4 30 OSC1/CLKI RD7/PSP7/P1D 5 PIC18F448 29 VSS VSS 6 28 VDD VDD 7 PIC18F458 27 RE2/AN7/CS/C2OUT RB0/INT0 8 26 RE1/AN6/WR/C1OUT RB1/INT1 9 25 RE0//AN5/RD RB2/CANTX/INT2 10 24 RA5/AN4/SS/LVDIN RB3/CANRX 11 23 RA4/T0CKI 21 22 14 15 17 20 13 16 18 12 19 RA0/AN0/CVREF RA3/AN3/VREF+ RB5/PGM RB4 RA1/AN1 RA2/AN2/VREF- NC NC RB6/PGC RB7/PGD MCLR/VPP SPDIP, SOIC MCLR/VPP 1 28 RB7/PGD RA0/AN0/CVREF 2 27 RB6/PGC RA1/AN1 3 26 RB5/PGM RA2/AN2/VREF- 4 25 RB4 RA3/AN3/VREF+ 5 24 RB3/CANRX PIC18F258 PIC18F248 RA4/T0CKI 6 23 RB2/CANTX/INT2 RA5/AN4/SS/LVDIN 7 22 RB1/INT1 VSS 8 21 RB0/INT0 OSC1/CLKI 9 20 VDD OSC2/CLKO/RA6 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 2004 Microchip Technology Inc. DS41159D-page 3
- 6. PIC18FXX8 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 17 3.0 Reset .......................................................................................................................................................................................... 25 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Data EEPROM Memory ............................................................................................................................................................ 59 6.0 Flash Program Memory .............................................................................................................................................................. 65 7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 75 8.0 Interrupts .................................................................................................................................................................................... 77 9.0 I/O Ports ..................................................................................................................................................................................... 93 10.0 Parallel Slave Port .................................................................................................................................................................... 107 11.0 Timer0 Module ......................................................................................................................................................................... 109 12.0 Timer1 Module ......................................................................................................................................................................... 113 13.0 Timer2 Module ......................................................................................................................................................................... 117 14.0 Timer3 Module ......................................................................................................................................................................... 119 15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 123 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 131 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 143 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 183 19.0 CAN Module ............................................................................................................................................................................. 199 20.0 Compatible 10-Bit Analog-to-Digital Converter (A/D) Module .................................................................................................. 241 21.0 Comparator Module.................................................................................................................................................................. 249 22.0 Comparator Voltage Reference Module ................................................................................................................................... 255 23.0 Low-Voltage Detect .................................................................................................................................................................. 259 24.0 Special Features of the CPU .................................................................................................................................................... 265 25.0 Instruction Set Summary .......................................................................................................................................................... 281 26.0 Development Support............................................................................................................................................................... 323 27.0 Electrical Characteristics .......................................................................................................................................................... 329 28.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 361 29.0 Packaging Information.............................................................................................................................................................. 377 Appendix A: Data Sheet Revision History.......................................................................................................................................... 385 Appendix B: Device Differences......................................................................................................................................................... 385 Appendix C: Device Migrations .......................................................................................................................................................... 386 Appendix D: Migrating From Other PICmicro® Devices ..................................................................................................................... 386 Index .................................................................................................................................................................................................. 387 On-Line Support................................................................................................................................................................................. 397 Systems Information and Upgrade Hot Line ...................................................................................................................................... 397 Reader Response .............................................................................................................................................................................. 398 PIC18FXX8 Product Identification System......................................................................................................................................... 399 DS41159D-page 4 2004 Microchip Technology Inc.
- 7. PIC18FXX8 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2004 Microchip Technology Inc. DS41159D-page 5
- 8. PIC18FXX8 NOTES: DS41159D-page 6 2004 Microchip Technology Inc.
- 9. PIC18FXX8 1.0 DEVICE OVERVIEW 2. PIC18F2X8 devices implement 5 A/D channels, as opposed to 8 for PIC18F4X8 devices. This document contains device specific information for 3. PIC18F2X8 devices implement 3 I/O ports, the following devices: while PIC18F4X8 devices implement 5. • PIC18F248 4. Only PIC18F4X8 devices implement the • PIC18F258 Enhanced CCP module, analog comparators • PIC18F448 and the Parallel Slave Port. • PIC18F458 All other features for devices in the PIC18FXX8 family, These devices are available in 28-pin, 40-pin and including the serial communications modules, are 44-pin packages. They are differentiated from each identical. These are summarized in Table 1-1. other in four ways: Block diagrams of the PIC18F2X8 and PIC18F4X8 1. PIC18FX58 devices have twice the Flash devices are provided in Figure 1-1 and Figure 1-2, program memory and data RAM of PIC18FX48 respectively. The pinouts for these device families are devices (32 Kbytes and 1536 bytes vs. listed in Table 1-2. 16 Kbytes and 768 bytes, respectively). TABLE 1-1: PIC18FXX8 DEVICE FEATURES Features PIC18F248 PIC18F258 PIC18F448 PIC18F458 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Internal Bytes 16K 32K 16K 32K Program # of Single-Word 8192 16384 8192 16384 Memory Instructions Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 17 17 21 21 I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 1 1 1 1 Enhanced Capture/Compare/ — — 1 1 PWM Modules Serial Communications MSSP, CAN, MSSP, CAN, MSSP, CAN, MSSP, CAN, Addressable USART Addressable USART Addressable USART Addressable USART Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Converter 5 input channels 5 input channels 8 input channels 8 input channels Analog Comparators No No 2 2 Analog Comparators VREF Output N/A N/A Yes Yes Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes CAN Module Yes Yes Yes Yes In-Circuit Serial Programming™ Yes Yes Yes Yes (ICSP™) Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin PLCC 44-pin PLCC 44-pin TQFP 44-pin TQFP 2004 Microchip Technology Inc. DS41159D-page 7
- 10. PIC18FXX8 FIGURE 1-1: PIC18F248/258 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0/CVREF 21 Table Pointer<21> Data Latch RA1/AN1 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ 21 inc/dec logic up to 1536 bytes RA4/T0CKI RA5/AN4/SS/LVDIN Address Latch OSC2/CLKO/RA6 21 PCLATU PCLATH 12 PORTB Address<12> RB0/INT0 PCU PCH PCL RB1/INT1 Program Counter 4 12 4 RB2/CANTX/INT2 RB3/CANRX Address Latch BSR FSR0 Bank0, F RB4 Program Memory 31 Level Stack FSR1 RB5/PGM up to 32 Kbytes FSR2 12 RB6/PGC Data Latch RB7/PGD Decode inc/dec Table Latch logic PORTC RC0/T1OSO/T1CKI 8 RC1/T1OSI 16 ROM Latch RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO IR RC6/TX/CK RC7/RX/DT 8 PRODH PRODL Instruction Decode & 8 x 8 Multiply Control 8 3 OSC2/CLKO/RA6 W BITOP OSC1/CLKI 8 Power-up 8 8 Timer Timing Oscillator Generation 8 T1OSI Start-up Timer T1OSO Power-on ALU<8> Reset 8 4X PLL Watchdog Timer Brown-out Precision Reset Band Gap Test Mode Reference Select Band Gap MCLR VDD, VSS PBOR 10-bit Timer0 Timer1 Timer2 Timer3 PLVD ADC Data EEPROM Synchronous CCP1 USART CAN Module Serial Port DS41159D-page 8 2004 Microchip Technology Inc.
- 11. PIC18FXX8 FIGURE 1-2: PIC18F448/458 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0/CVREF 21 Table Pointer<21> Data Latch RA1/AN1 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ 21 inc/dec logic up to 1536 Kbytes RA4/T0CKI RA5/AN4/SS/LVDIN Address Latch OSC2/CLKO/RA6 21 PCLATU PCLATH 12 PORTB Address<12> RB0/INT0 PCU PCH PCL RB1/INT1 Program Counter 4 12 4 RB2/CANTX/INT2 Address Latch BSR FSR0 Bank0, F RB3/CANRX RB4 Program Memory 31 Level Stack FSR1 RB5/PGM up to 32 Kbytes FSR2 12 RB6/PGC Data Latch RB7/PGD inc/dec Decode logic PORTC Table Latch RC0/T1OSO/T1CKI 8 RC1/T1OSI 16 ROM Latch RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO IR RC6/TX/CK RC7/RX/DT 8 PORTD RD0/PSP0/C1IN+ PRODH PRODL RD1/PSP1/C1IN- Instruction RD2/PSP2/C2IN+ Decode & 8 x 8 Multiply RD3/PSP3/C2IN- Control 8 3 RD4/PSP4/ECCP1/P1A OSC2/CLKO/RA6 RD5/PSP5/P1B OSC1/CLKI BITOP W 8 RD6/PSP6/P1C Power-up 8 8 Timer RD7/PSP7/P1D Timing Oscillator PORTE 8 Generation Start-up Timer T1OSI RE0/AN5/RD Power-on ALU<8> T1OSO RE1/AN6/WR//C1OUT 4X Reset RE2/AN7/CS/C2OUT PLL 8 Watchdog Timer Precision Band Gap Brown-out Reference Reset Test Mode Select Band Gap MCLR VDD, VSS USART PBOR 10-bit Parallel Timer0 Timer1 Timer2 Timer3 PLVD ADC Slave Port Data EEPROM Enhanced USART Synchronous Comparators CCP1 CAN Module CCP Serial Port 2004 Microchip Technology Inc. DS41159D-page 9
- 12. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC MCLR/VPP 1 1 18 2 Master Clear (input) or programming voltage (output). MCLR I ST Master Clear (Reset) input. This pin is an active low Reset to the device. VPP P — Programming voltage input. NC — — 12, 13, 1, 17, — — These pins should be left 33, 34 28, 40 unconnected. OSC1/CLKI 9 13 30 14 Oscillator crystal or external clock input. OSC1 I CMOS/ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise, CMOS. CLKI I CMOS External clock source input. Always associated with pin function OSC1 (see OSC1/ CLKI, OSC2/CLKO pins). OSC2/CLKO/RA6 10 14 31 15 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS41159D-page 10 2004 Microchip Technology Inc.
- 13. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC PORTA is a bidirectional I/O port. RA0/AN0/CVREF 2 2 19 3 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. CVREF O Analog Comparator voltage reference output. RA1/AN1 3 3 20 4 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 4 4 21 5 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (Low) input. RA3/AN3/VREF+ 5 5 22 6 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (High) input. RA4/T0CKI 6 6 23 7 RA4 I/O TTL/OD Digital I/O – open-drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/SS/LVDIN 7 7 24 8 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I ST SPI™ slave select input. LVDIN I Analog Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) 2004 Microchip Technology Inc. DS41159D-page 11
- 14. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 21 33 8 36 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. RB1/INT1 22 34 9 37 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/CANTX/INT2 23 35 10 38 RB2 I/O TTL Digital I/O. CANTX O TTL Transmit signal for CAN bus. INT2 I ST External interrupt 2. RB3/CANRX 24 36 11 39 RB3 I/O TTL Digital I/O. CANRX I TTL Receive signal for CAN bus. RB4 25 37 14 41 I/O TTL Digital I/O. Interrupt-on-change pin. RB5/PGM 26 38 15 42 RB5 I/O TTL Digital I/O. Interrupt-on-change pin. PGM I ST Low-voltage ICSP™ programming enable. RB6/PGC 27 39 16 43 RB6 I/O TTL Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. PGC I ST ICSP programming clock. RB7/PGD 28 40 17 44 RB7 I/O TTL Digital I/O. In-Circuit Debugger pin. Interrupt-on-change pin. PGD I/O ST ICSP programming data. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS41159D-page 12 2004 Microchip Technology Inc.
- 15. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 11 15 32 16 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI 12 16 35 18 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. RC2/CCP1 13 17 36 19 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 14 18 37 20 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI™ mode. SCL I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 15 23 42 25 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O ST I2C data I/O. RC5/SDO 16 24 43 26 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 17 25 44 27 RC6 I/O ST Digital I/O. TX O — USART asynchronous transmit. CK I/O ST USART synchronous clock (see RX/DT). RC7/RX/DT 18 26 1 29 RC7 I/O ST Digital I/O. RX I ST USART asynchronous receive. DT I/O ST USART synchronous data (see TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) 2004 Microchip Technology Inc. DS41159D-page 13
- 16. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0/C1IN+ — 19 38 21 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. C1IN+ I Analog Comparator 1 input. RD1/PSP1/C1IN- — 20 39 22 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. C1IN- I Analog Comparator 1 input. RD2/PSP2/C2IN+ — 21 40 23 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. C2IN+ I Analog Comparator 2 input. RD3/PSP3/C2IN- — 22 41 24 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. C2IN- I Analog Comparator 2 input. RD4/PSP4/ECCP1/ — 27 2 30 P1A RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. ECCP1 I/O ST ECCP1 capture/compare. P1A O — ECCP1 PWM output A. RD5/PSP5/P1B — 28 3 31 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O — ECCP1 PWM output B. RD6/PSP6/P1C — 29 4 32 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O — ECCP1 PWM output C. RD7/PSP7/P1D — 30 5 33 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O — ECCP1 PWM output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DS41159D-page 14 2004 Microchip Technology Inc.
- 17. PIC18FXX8 TABLE 1-2: PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F248/258 PIC18F448/458 Description Type Type SPDIP, SOIC PDIP TQFP PLCC PORTE is a bidirectional I/O port. RE0/AN5/RD — 8 25 9 RE0 I/O ST Digital I/O. AN5 I Analog Analog input 5. RD I TTL Read control for Parallel Slave Port (see WR and CS pins). RE1/AN6/WR/C1OUT — 9 26 10 RE1 I/O ST Digital I/O. AN6 I Analog Analog input 6. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). C1OUT O Analog Comparator 1 output. RE2/AN7/CS/C2OUT — 10 27 11 RE2 I/O ST Digital I/O. AN7 I Analog Analog input 7. CS I TTL Chip select control for Parallel Slave Port (see RD and WR pins). C2OUT O Analog Comparator 2 output. VSS 19, 8 12, 31 6, 29 13, 34 — — Ground reference for logic and I/O pins. VDD 20 11, 32 7, 28 12, 35 — — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) 2004 Microchip Technology Inc. DS41159D-page 15
- 18. PIC18FXX8 NOTES: DS41159D-page 16 2004 Microchip Technology Inc.
- 19. PIC18FXX8 2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (HS, XT OR LP OSC 2.1 Oscillator Types CONFIGURATION) The PIC18FXX8 can be operated in one of eight oscil- C1(1) OSC1 lator modes, programmable by three configuration bits To (FOSC2, FOSC1 and FOSC0). Internal XTAL Logic 1. LP Low-Power Crystal RF(3) 2. XT Crystal/Resonator Sleep RS(2) 3. HS High-Speed Crystal/Resonator PIC18FXX8 C2(1) OSC2 4. HS4 High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2. 6. RCIO External Resistor/Capacitor with I/O pin enabled 2: A series resistor (RS) may be required for AT strip cut crystals. 7. EC External Clock 3: RF varies with the crystal chosen. 8. ECIO External Clock with I/O pin enabled 2.2 Crystal Oscillator/Ceramic TABLE 2-1: CERAMIC RESONATORS Resonators Ranges Tested: In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal Mode Freq OSC1 OSC2 or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows XT 455 kHz 68-100 pF 68-100 pF the pin connections. An external clock source may also 2.0 MHz 15-68 pF 15-68 pF be connected to the OSC1 pin, as shown in Figure 2-3 4.0 MHz 15-68 pF 15-68 pF and Figure 2-4. HS 8.0 MHz 10-68 pF 10-68 pF The PIC18FXX8 oscillator design requires the use of a 16.0 MHz 10-22 pF 10-22 pF parallel cut crystal. These values are for design guidance only. See notes following Table 2-2. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s Resonators Used: specifications. 455 kHz Panasonic EFO-A455K04B ±0.3% 2.0 MHz Murata Erie CSA2.00MG ±0.5% 4.0 MHz Murata Erie CSA4.00MG ±0.5% 8.0 MHz Murata Erie CSA8.00MT ±0.5% 16.0 MHz Murata Erie CSA16.00MX ±0.5% All resonators used did not have built-in capacitors. 2004 Microchip Technology Inc. DS41159D-page 17
- 20. PIC18FXX8 TABLE 2-2: CAPACITOR SELECTION FOR 2.3 RC Oscillator CRYSTAL OSCILLATOR For timing insensitive applications, the “RC” and “RCIO” Crystal Cap. Range Cap. Range device options offer additional cost savings. The RC Osc Type Freq C1 C2 oscillator frequency is a function of the supply voltage, LP 32.0 kHz 33 pF 33 pF the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator 200 kHz 15 pF 15 pF frequency will vary from unit to unit due to normal XT 200 kHz 47-68 pF 47-68 pF process parameter variation. Furthermore, the differ- 1.0 MHz 15 pF 15 pF ence in lead frame capacitance between package types will also affect the oscillation frequency, especially for 4.0 MHz 15 pF 15 pF low CEXT values. The user also needs to take into HS 4.0 MHz 15 pF 15 pF account variation due to tolerance of external R and C 8.0 MHz 15-33 pF 15-33 pF components used. Figure 2-2 shows how the RC 20.0 MHz 15-33 pF 15-33 pF combination is connected. 25.0 MHz 15-33 pF 15-33 pF In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal These values are for design guidance only. may be used for test purposes or to synchronize other See notes on this page. logic. Crystals Used Note: If the oscillator frequency divided by 4 32.0 kHz Epson C-001R32.768K-A ±20 PPM signal is not required in the application, it 200 kHz STD XTL 200.000KHz ±20 PPM is recommended to use RCIO mode to 1.0 MHz ECS ECS-10-13-1 ±50 PPM save current. 4.0 MHz ECS ECS-40-20-1 ±50 PPM FIGURE 2-2: RC OSCILLATOR MODE 8.0 MHz EPSON CA-301 8.000M-C ±30 PPM 20.0 MHz EPSON CA-301 20.000M-C ±30 PPM VDD REXT PIC18FXX8 Note 1: Recommended values of C1 and C2 are Internal identical to the ranges tested (Table 2-1). OSC1 Clock 2: Higher capacitance increases the stability CEXT of the oscillator but also increases the start-up time. VSS OSC2/CLKO 3: Since each resonator/crystal has its own FOSC/4 characteristics, the user should consult the resonator/crystal manufacturer for Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ appropriate values of external CEXT > 20 pF components. 4: Rs may be required in HS mode, as well The RCIO Oscillator mode functions like the RC mode, as XT mode, to avoid overdriving crystals except that the OSC2 pin becomes an additional with low drive level specification. general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). DS41159D-page 18 2004 Microchip Technology Inc.
- 21. PIC18FXX8 2.4 External Clock Input FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO The EC and ECIO Oscillator modes require an external CONFIGURATION) clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscilla- OSC1 PIC18FXX8 Clock from tor start-up time required after a Power-on Reset or Ext. System after a recovery from Sleep mode. I/O (OSC2) In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC 2.5 HS4 (PLL) Oscillator mode. A Phase Locked Loop circuit is provided as a program- mable option for users that want to multiply the FIGURE 2-3: EXTERNAL CLOCK INPUT frequency of the incoming crystal oscillator signal by 4. OPERATION (EC OSC For an input clock frequency of 10 MHz, the internal CONFIGURATION) clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due OSC1 PIC18FXX8 to high-frequency crystals. Clock from Ext. System The PLL can only be enabled when the oscillator FOSC/4 OSC2 configuration bits are programmed for HS mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from The ECIO Oscillator mode functions like the EC mode, OSC1. except that the OSC2 pin becomes an additional The PLL is one of the modes of the FOSC2:FOSC0 general purpose I/O pin. Figure 2-4 shows the pin configuration bits. The oscillator mode is specified connections for the ECIO Oscillator mode. during device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred to as TPLL. FIGURE 2-5: PLL BLOCK DIAGRAM FOSC2:FOSC0 = 110 OSC2 Phase Comparator FIN Loop VCO Crystal Filter FOUT Osc SYSCLK MUX OSC1 Divide by 4 2004 Microchip Technology Inc. DS41159D-page 19
- 22. PIC18FXX8 2.6 Oscillator Switching Feature 2.6.1 SYSTEM CLOCK SWITCH BIT The PIC18FXX8 devices include a feature that allows The system clock source switching is performed under the system clock source to be switched from the main software control. The system clock switch bit, SCS oscillator to an alternate low-frequency clock source. (OSCCON register), controls the clock switching. When For the PIC18FXX8 devices, this alternate clock source the SCS bit is ‘0’, the system clock source comes from is the Timer1 oscillator. If a low-frequency crystal the main oscillator selected by the FOSC2:FOSC0 (32 kHz, for example) has been attached to the Timer1 configuration bits. When the SCS bit is set, the system oscillator pins and the Timer1 oscillator has been clock source comes from the Timer1 oscillator. The SCS enabled, the device can switch to a Low-Power Execu- bit is cleared on all forms of Reset. tion mode. Figure 2-6 shows a block diagram of the Note: The Timer1 oscillator must be enabled to system clock sources. The clock switching feature is switch the system clock source. The enabled by programming the Oscillator Switching Timer1 oscillator is enabled by setting the Enable (OSCSEN) bit in Configuration register, T1OSCEN bit in the Timer1 Control regis- CONFIG1H, to a ‘0’. Clock switching is disabled in an ter (T1CON). If the Timer1 oscillator is not erased device. See Section 12.2 “Timer1 Oscillator” enabled, any write to the SCS bit will be for further details of the Timer1 oscillator and ignored (SCS bit forced cleared) and the Section 24.1 “Configuration Bits” for Configuration main oscillator continues to be the system register details. clock source. FIGURE 2-6: DEVICE CLOCK SOURCES PIC18FXX8 Main Oscillator OSC2 TOSC/4 Sleep 4 x PLL TOSC TSCLK MUX OSC1 Timer 1 Oscillator T T 1P T1OSO T1OSCEN Enable Clock T1OSI Oscillator Source Clock Source Option for Other Modules Note: I/O pins have diode protection to VDD and VSS. REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — SCS bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SCS: System Clock Switch bit When OSCSEN configuration bit = 0 and T1OSCEN bit is set: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN is clear or T1OSCEN is clear: Bit is forced clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 20 2004 Microchip Technology Inc.
- 23. PIC18FXX8 2.6.2 OSCILLATOR TRANSITIONS The sequence of events that takes place when switch- ing from the Timer1 oscillator to the main oscillator will The PIC18FXX8 devices contain circuitry to prevent depend on the mode of the main oscillator. In addition “glitches” when switching between oscillator sources. to eight clock cycles of the main oscillator, additional Essentially, the circuitry waits for eight rising edges of delays may take place. the clock source that the processor is switching to. This ensures that the new clock source is stable and that its If the main oscillator is configured for an external pulse width will not be less than the shortest pulse crystal (HS, XT, LP), the transition will take place after width of the two clock sources. an oscillator start-up time (TOST) has occurred. A timing diagram indicating the transition from the Timer1 Figure 2-7 shows a timing diagram indicating the tran- oscillator to the main oscillator for HS, XT and LP sition from the main oscillator to the Timer1 oscillator. modes is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TT1P T1OSI 1 2 3 4 5 6 7 8 Tscs OSC1 Internal TOSC System Clock TDLY SCS (OSCCON<0>) Program PC PC + 2 PC + 4 Counter Note 1: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 1 2 3 4 5 6 7 8 TOST TSCS OSC2 TOSC Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note 1: TOST = 1024 TOSC (drawing not to scale). 2004 Microchip Technology Inc. DS41159D-page 21
- 24. PIC18FXX8 If the main oscillator is configured for HS4 (PLL) mode, If the main oscillator is configured in the RC, RCIO, EC an oscillator start-up time (TOST) plus an additional PLL or ECIO modes, there is no oscillator start-up time-out. time-out (TPLL) will occur. The PLL time-out is typically Operation will resume after eight cycles of the main 2 ms and allows the PLL to lock to the main oscillator oscillator have been counted. A timing diagram indicat- frequency. A timing diagram indicating the transition ing the transition from the Timer1 oscillator to the main from the Timer1 oscillator to the main oscillator for HS4 oscillator for RC, RCIO, EC and ECIO modes is shown mode is shown in Figure 2-9. in Figure 2-10. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL OSC2 TOSC TSCS PLL Clock Input 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note 1: TOST = 1024 TOSC (drawing not to scale). FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TT1P T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 OSC2 Internal System Clock SCS (OSCCON<0>) TSCS Program PC PC + 2 PC + 4 Counter Note 1: RC Oscillator mode assumed. DS41159D-page 22 2004 Microchip Technology Inc.
- 25. PIC18FXX8 2.7 Effects of Sleep Mode on the Reset until the device power supply and clock are On-Chip Oscillator stable. For additional information on Reset operation, see Section 3.0 “Reset”. When the device executes a SLEEP instruction, the The first timer is the Power-up Timer (PWRT), which on-chip clocks and oscillator are turned off and the optionally provides a fixed delay of TPWRT (parameter device is held at the beginning of an instruction cycle #D033) on power-up only (POR and BOR). The second (Q1 state). With the oscillator off, the OSC1 and OSC2 timer is the Oscillator Start-up Timer (OST), intended to signals will stop oscillating. Since all the transistor keep the chip in Reset until the crystal oscillator is switching currents have been removed, Sleep mode stable. achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature With the PLL enabled (HS4 Oscillator mode), the time- that will operate during Sleep will increase the current out sequence following a Power-on Reset is different consumed during Sleep. The user can wake from from other oscillator modes. The time-out sequence is Sleep through external Reset, Watchdog Timer Reset as follows: the PWRT time-out is invoked after a POR or through an interrupt. time delay has expired, then the Oscillator Start-up Timer (OST) is invoked. However, this is still not a 2.8 Power-up Delays sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an Power-up delays are controlled by two timers so that no additional fixed 2 ms (nominal) to allow the PLL ample external Reset circuitry is required for most applica- time to lock to the incoming clock frequency. tions. The delays ensure that the device is kept in TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2004 Microchip Technology Inc. DS41159D-page 23
- 26. PIC18FXX8 NOTES: DS41159D-page 24 2004 Microchip Technology Inc.
- 27. PIC18FXX8 3.0 RESET state on Power-on Reset, MCLR, WDT Reset, Brown- out Reset, MCLR Reset during Sleep and by the The PIC18FXX8 differentiates between various kinds RESET instruction. of RESET: Most registers are not affected by a WDT wake-up, a) Power-on Reset (POR) since this is viewed as the resumption of normal oper- b) MCLR Reset during normal operation ation. Status bits from the RCON register, RI, TO, PD, c) MCLR Reset during Sleep POR and BOR are set or cleared differently in different d) Watchdog Timer (WDT) Reset during normal Reset situations, as indicated in Table 3-2. These bits operation are used in software to determine the nature of the Reset. See Table 3-3 for a full description of the Reset e) Programmable Brown-out Reset (PBOR) states of all registers. f) RESET Instruction A simplified block diagram of the On-Chip Reset Circuit g) Stack Full Reset is shown in Figure 3-1. h) Stack Underflow Reset The Enhanced MCU devices have a MCLR noise filter Most registers are unaffected by a Reset. Their status in the MCLR Reset path. The filter will detect and is unknown on POR and unchanged by all other ignore small pulses. Resets. The other registers are forced to a “Reset” A WDT Reset does not drive MCLR pin low. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLR Sleep WDT WDT Module Time-out Reset VDD Rise Detect VDD Power-on Reset Brown-out Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter Q R OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2004 Microchip Technology Inc. DS41159D-page 25
- 28. PIC18FXX8 3.1 Power-on Reset (POR) 3.3 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when a The Power-up Timer provides a fixed nominal time-out VDD rise is detected. To take advantage of the POR (parameter #33), only on power-up from the POR. The circuitry, connect the MCLR pin directly (or through a Power-up Timer operates on an internal RC oscillator. resistor) to VDD. This eliminates external RC compo- The chip is kept in Reset as long as the PWRT is active. nents usually needed to create a Power-on Reset The PWRT’s time delay allows VDD to rise to an accept- delay. A minimum rise rate for VDD is specified (refer to able level. A configuration bit (PWRTEN in CONFIG2L parameter D004). For a slow rise time, see Figure 3-2. register) is provided to enable/disable the PWRT. When the device starts normal operation (exits the The power-up time delay will vary from chip to chip due Reset condition), device operating parameters to VDD, temperature and process variation. See DC (voltage, frequency, temperature, etc.) must be met to parameter #33 for details. ensure operation. If these conditions are not met, the device must be held in Reset until the operating condi- 3.4 Oscillator Start-up Timer (OST) tions are met. Brown-out Reset may be used to meet the voltage start-up condition. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the 3.2 MCLR PWRT delay is over (parameter #32). This additional delay ensures that the crystal oscillator or resonator PIC18FXX8 devices have a noise filter in the MCLR has started and stabilized. Reset path. The filter will detect and ignore small The OST time-out is invoked only for XT, LP, HS and pulses. HS4 modes and only on Power-on Reset or wake-up It should be noted that a WDT Reset does not drive from Sleep. MCLR pin low. The behavior of the ESD protection on the MCLR pin 3.5 PLL Lock Time-out differs from previous devices of this family. Voltages With the PLL enabled, the time-out sequence following applied to the pin that exceed its specification can a Power-on Reset is different from other oscillator result in both Resets and current draws outside of modes. A portion of the Power-up Timer is used to pro- device specification during the Reset event. For this vide a fixed time-out that is sufficient for the PLL to lock reason, Microchip recommends that the MCLR pin no to the main oscillator frequency. This PLL lock time-out longer be tied directly to VDD. The use of an RC (TPLL) is typically 2 ms and follows the oscillator network, as shown in Figure 3-2, is suggested. start-up time-out (OST). FIGURE 3-2: EXTERNAL POWER-ON 3.6 Brown-out Reset (BOR) RESET CIRCUIT (FOR SLOW VDD POWER-UP) A configuration bit, BOREN, can disable (if clear/ programmed), or enable (if set), the Brown-out Reset VDD circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation resets the D chip. A Reset may not occur if VDD falls below param- R eter D005 for less than parameter #35. The chip will R1 MCLR remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep C PIC18FXXX the chip in Reset an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Note 1: External Power-on Reset circuit is required Reset and the Power-up Timer will be initialized. Once only if the VDD power-up slope is too slow. VDD rises above BVDD, the Power-up Timer will The diode D helps discharge the capacitor execute the additional time delay. quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1 = 100Ω to 1 kΩ will limit any current flow- ing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). DS41159D-page 26 2004 Microchip Technology Inc.
- 29. PIC18FXX8 3.7 Time-out Sequence Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. On power-up, the time-out sequence is as follows: Bringing MCLR high will begin execution immediately First, PWRT time-out is invoked after the POR time (Figure 3-5). This is useful for testing purposes or to delay has expired, then OST is activated. The total synchronize more than one PIC18FXX8 device time-out will vary based on oscillator configuration and operating in parallel. the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Table 3-2 shows the Reset conditions for some Special Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Function Registers, while Table 3-3 shows the Reset Figure 3-7 depict time-out sequences on power-up. conditions for all registers. TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Wake-up from Oscillator Brown-out(2) Sleep or Configuration PWRTEN = 0 PWRTEN = 1 Oscillator Switch HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC EC 72 ms — 72 ms — External RC 72 ms — 72 ms — Note 1: 2 ms = Nominal time required for the 4x PLL to lock. 2: 72 ms is the nominal Power-up Timer delay. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 IPEN — — RI TO PD POR BOR bit 7 bit 0 TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Condition RI TO PD POR BOR STKFUL STKUNF Counter Register Power-on Reset 0000h 0--1 110q 1 1 1 0 0 u u MCLR Reset during normal 0000h 0--0 011q u u u u u u u operation Software Reset during normal 0000h 0--0 011q 0 u u u u u u operation Stack Full Reset during normal 0000h 0--0 011q u u u 1 1 u 1 operation Stack Underflow Reset during 0000h 0--0 011q u u u 1 1 1 u normal operation MCLR Reset during Sleep 0000h 0--0 011q u 1 0 u u u u WDT Reset 0000h 0--0 011q u 0 1 u u u u WDT Wake-up PC + 2 0--1 101q u 0 0 u u u u Brown-out Reset 0000h 0--1 110q 1 1 1 u 0 u u Interrupt wake-up from Sleep PC + 2(1) 0--1 101q u 1 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). 2004 Microchip Technology Inc. DS41159D-page 27
- 30. PIC18FXX8 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41159D-page 28 2004 Microchip Technology Inc.
- 31. PIC18FXX8 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. 2004 Microchip Technology Inc. DS41159D-page 29
- 32. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2X8 PIC18F4X8 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F2X8 PIC18F4X8 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2X8 PIC18F4X8 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2X8 PIC18F4X8 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F2X8 PIC18F4X8 111- -1-1 111- -1-1 uuu- -u-u(1) INTCON3 PIC18F2X8 PIC18F4X8 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC0 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW0 PIC18F2X8 PIC18F4X8 N/A N/A N/A FSR0H PIC18F2X8 PIC18F4X8 ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC1 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW1 PIC18F2X8 PIC18F4X8 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). DS41159D-page 30 2004 Microchip Technology Inc.
- 33. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets FSR1H PIC18F2X8 PIC18F4X8 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2X8 PIC18F4X8 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTINC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A POSTDEC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A PREINC2 PIC18F2X8 PIC18F4X8 N/A N/A N/A PLUSW2 PIC18F2X8 PIC18F4X8 N/A N/A N/A FSR2H PIC18F2X8 PIC18F4X8 ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2X8 PIC18F4X8 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2X8 PIC18F4X8 ---- ---0 ---- ---0 ---- ---u LVDCON PIC18F2X8 PIC18F4X8 --00 0101 --00 0101 --uu uuuu WDTCON PIC18F2X8 PIC18F4X8 ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F2X8 PIC18F4X8 0--1 110q 0--0 011q 0--1 101q TMR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2X8 PIC18F4X8 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 1111 1111 T2CON PIC18F2X8 PIC18F4X8 -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2X8 PIC18F4X8 0000 00-0 0000 00-0 uuuu uu-u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). 2004 Microchip Technology Inc. DS41159D-page 31
- 34. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ADCON1 PIC18F2X8 PIC18F4X8 00-- 0000 00-- 0000 uu-- uuuu CCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2X8 PIC18F4X8 --00 0000 --00 0000 --uu uuuu ECCPR1H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ECCPR1L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu ECCP1CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 ECCP1DEL PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 ECCPAS PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 0000 0000 CVRCON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2X8 PIC18F4X8 0000 0000 uuuu uuuu uuuu uuuu SPBRG PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu RCREG PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXREG PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXSTA PIC18F2X8 PIC18F4X8 0000 -010 0000 -010 uuuu -uuu RCSTA PIC18F2X8 PIC18F4X8 0000 000x 0000 000u uuuu uuuu EEADR PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EEDATA PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EECON2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu EECON1 PIC18F2X8 PIC18F4X8 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu PIE3 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F2X8 PIC18F4X8 -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F2X8 PIC18F4X8 -0-0 0000 -0-0 0000 -u-u uuuu(1) PIE2 PIC18F2X8 PIC18F4X8 -0-0 0000 -0-0 0000 -u-u uuuu IPR1 PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu(1) PIE1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). DS41159D-page 32 2004 Microchip Technology Inc.
- 35. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TRISE PIC18F2X8 PIC18F4X8 0000 -111 0000 -111 uuuu -uuu TRISD PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2X8 PIC18F4X8 1111 1111 1111 1111 uuuu uuuu (5) (5) (5) TRISA PIC18F2X8 PIC18F4X8 -111 1111 -111 1111 -uuu uuuu(5) LATE PIC18F2X8 PIC18F4X8 ---- -xxx ---- -uuu ---- -uuu LATD PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) PIC18F2X8 PIC18F4X8 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) PORTE PIC18F2X8 PIC18F4X8 ---- -xxx ---- -000 ---- -uuu PORTD PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu (5) PORTA PIC18F2X8 PIC18F4X8 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) TXERRCNT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu RXERRCNT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu COMSTAT PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CIOCON PIC18F2X8 PIC18F4X8 --00 ---- --00 ---- --uu ---- BRGCON3 PIC18F2X8 PIC18F4X8 -0-- -000 -0-- -000 -u-- -uuu BRGCON2 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu BRGCON1 PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu CANCON PIC18F2X8 PIC18F4X8 xxxx xxx- uuuu uuu- uuuu uuu- CANSTAT(6) PIC18F2X8 PIC18F4X8 xxx- xxx- uuu- uuu- uuu- uuu- RXB0D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). 2004 Microchip Technology Inc. DS41159D-page 33
- 36. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXB0DLC PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON PIC18F2X8 PIC18F4X8 000- 0000 000- 0000 uuu- uuuu RXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC PIC18F2X8 PIC18F4X8 -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F2X8 PIC18F4X8 xxxx x-xx uuuu u-uu uuuu u-uu RXB1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON PIC18F2X8 PIC18F4X8 000- 0000 000- 0000 uuu- uuuu TXB0D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC PIC18F2X8 PIC18F4X8 -x-- xxxx -u-- uuuu -u-- uuuu TXB0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). DS41159D-page 34 2004 Microchip Technology Inc.
- 37. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TXB0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON PIC18F2X8 PIC18F4X8 -000 0-00 -000 0-00 -uuu u-uu TXB1D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC PIC18F2X8 PIC18F4X8 -x-- xxxx -u-- uuuu -u-- uuuu TXB1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu TXB1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON PIC18F2X8 PIC18F4X8 0000 0000 0000 0000 uuuu uuuu TXB2D7 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D6 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D5 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D4 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D3 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D2 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D1 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D0 PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2DLC PIC18F2X8 PIC18F4X8 -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu TXB2SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu TXB2CON PIC18F2X8 PIC18F4X8 -000 0-00 -000 0-00 -uuu u-uu RXM1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). 2004 Microchip Technology Inc. DS41159D-page 35
- 38. PIC18FXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Reset Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXM1SIDL PIC18F2X8 PIC18F4X8 xxx- --xx uuu- --uu uuu- --uu RXM1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL PIC18F2X8 PIC18F4X8 xxx- --xx uuu- --uu uuu- --uu RXM0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL PIC18F2X8 PIC18F4X8 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH PIC18F2X8 PIC18F4X8 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4). DS41159D-page 36 2004 Microchip Technology Inc.
- 39. PIC18FXX8 4.0 MEMORY ORGANIZATION Figure 4-1 shows the diagram for program memory map and stack for the PIC18F248 and PIC18F448. There are three memory blocks in Enhanced MCU Figure 4-2 shows the diagram for the program memory devices. These memory blocks are: map and stack for the PIC18F258 and PIC18F458. • Enhanced Flash Program Memory • Data Memory 4.1.1 INTERNAL PROGRAM MEMORY • EEPROM Data Memory OPERATION Data and program memory use separate busses, The PIC18F258 and the PIC18F458 have 32 Kbytes of which allows concurrent access of these blocks. internal Enhanced Flash program memory. This means Additional detailed information on data EEPROM and that the PIC18F258 and the PIC18F458 can store up to Flash program memory is provided in Section 5.0 16K of single-word instructions. The PIC18F248 and “Data EEPROM Memory” and Section 6.0 “Flash PIC18F448 have 16 Kbytes of Enhanced Flash Program Memory”, respectively. program memory. This translates into 8192 single-word instructions, which can be stored in the program 4.1 Program Memory Organization memory. Accessing a location between the physically implemented memory and the 2-Mbyte address will The PIC18F258/458 devices have a 21-bit program cause a read of all ‘0’s (a NOP instruction). counter that is capable of addressing a 2-Mbyte program memory space. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. FIGURE 4-1: PROGRAM MEMORY MAP FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC18F248/448 PIC18F258/458 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1 • • • • • • Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h On-Chip User Memory Space Program Memory User Memory Space 7FFFh Read ‘0’ 8000h Read ‘0’ 1FFFFFh 1FFFFFh 200000h 200000h 2004 Microchip Technology Inc. DS41159D-page 37
- 40. PIC18FXX8 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC The STKPTR register contains the Stack Pointer value, (Program Counter) is pushed onto the stack when a the STKFUL (Stack Full) status bit and the STKUNF PUSH, CALL or RCALL instruction is executed, or an (Stack Underflow) status bits. Register 4-1 shows the interrupt is Acknowledged. The PC value is pulled off STKPTR register. The value of the Stack Pointer can be the stack on a RETURN, RETLW or a RETFIE instruc- 0 through 31. The Stack Pointer increments when val- tion. PCLATU and PCLATH are not affected by any of ues are pushed onto the stack and decrements when the RETURN instructions. values are popped off the stack. At Reset, the Stack Pointer value will be ‘0’. The user may read and write The stack operates as a 31-word by 21-bit stack the Stack Pointer value. This feature can be used by a memory and a 5-bit Stack Pointer register, with the Real-Time Operating System for return stack Stack Pointer initialized to 00000b after all Resets. maintenance. There is no RAM associated with Stack Pointer 00000b. This is only a Reset value. During a CALL type After the PC is pushed onto the stack 31 times (without instruction, causing a push onto the stack, the Stack popping any values off the stack), the STKFUL bit is Pointer is first incremented and the RAM location set. The STKFUL bit can only be cleared in software or pointed to by the Stack Pointer is written with the con- by a POR. tents of the PC. During a RETURN type instruction, The action that takes place when the stack becomes causing a pop from the stack, the contents of the RAM full depends on the state of the STVREN (Stack Over- location indicated by the STKPTR are transferred to the flow Reset Enable) configuration bit. Refer to PC and then the Stack Pointer is decremented. Section 21.0 “Comparator Module” for a description The stack space is not part of either program or data of the device configuration bits. If STVREN is set space. The Stack Pointer is readable and writable and (default), the 31st push will push the (PC + 2) value the data on the top of the stack is readable and writable onto the stack, set the STKFUL bit and reset the through SFR registers. Status bits indicate if the stack device. The STKFUL bit will remain set and the Stack pointer is at or beyond the 31 levels provided. Pointer will be set to ‘0’. If STVREN is cleared, the STKFUL bit will be set on the 4.2.1 TOP-OF-STACK ACCESS 31st push and the Stack Pointer will increment to 31. The top of the stack is readable and writable. Three The 32nd push will overwrite the 31st push (and so on), register locations, TOSU, TOSH and TOSL allow while STKPTR remains at 31. access to the contents of the stack location indicated by When the stack has been popped enough times to the STKPTR register. This allows users to implement a unload the stack, the next pop will return a value of zero software stack, if necessary. After a CALL, RCALL or to the PC and sets the STKUNF bit, while the stack interrupt, the software can read the pushed value by pointer remains at ‘0’. The STKUNF bit will remain set reading the TOSU, TOSH and TOSL registers. These until cleared in software or a POR occurs. values can be placed on a user defined software stack. At return time, the software can replace the TOSU, Note: Returning a value of zero to the PC on an TOSH and TOSL and do a return. underflow has the effect of vectoring the program to the Reset vector, where the The user should disable the global interrupt enable bits stack conditions can be verified and during this time to prevent inadvertent stack appropriate actions can be taken. operations. DS41159D-page 38 2004 Microchip Technology Inc.
- 41. PIC18FXX8 REGISTER 4-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note: Bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 000000h 00000(1) Note 1: No RAM associated with this address; always maintained ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 39
- 42. PIC18FXX8 4.2.3 PUSH AND POP INSTRUCTIONS EXAMPLE 4-1: FAST REGISTER STACK Since the Top-of-Stack (TOS) is readable and writable, CODE EXAMPLE the ability to push values onto the stack and pull values CALL SUB1, FAST ;STATUS, WREG, BSR off the stack, without disturbing normal program execu- ;SAVED IN FAST REGISTER tion, is a desirable option. To push the current PC value ;STACK onto the stack, a PUSH instruction can be executed. • • This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and SUB1 • TOSL can then be modified to place a return address • on the stack. • The POP instruction discards the current TOS by decre- RETURN FAST ;RESTORE VALUES SAVED menting the Stack Pointer. The previous value pushed ;IN FAST REGISTER STACK onto the stack then becomes the TOS value. 4.2.4 STACK FULL/UNDERFLOW RESETS 4.4 PCL, PCLATH and PCLATU These Resets are enabled by programming the The Program Counter (PC) specifies the address of the STVREN configuration bit. When the STVREN bit is instruction to fetch for execution. The PC is 21 bits disabled, a full or underflow condition will set the appro- wide. The low byte is called the PCL register. This reg- priate STKFUL or STKUNF bit, but not cause a device ister is readable and writable. The high byte is called Reset. When the STVREN bit is enabled, a full or the PCH register. This register contains the PC<15:8> underflow condition will set the appropriate STKFUL or bits and is not directly readable or writable. Updates to STKUNF bit and then cause a device Reset. The the PCH register may be performed through the STKFUL or STKUNF bits are only cleared by the user PCLATH register. The upper byte is called PCU. This software or a POR. register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may 4.3 Fast Register Stack be performed through the PCLATU register. A “fast return” option is available for interrupts and The PC addresses bytes in the program memory. To calls. A fast register stack is provided for the Status, prevent the PC from becoming misaligned with word WREG and BSR registers and is only one layer in instructions, the LSb of PCL is fixed to a value of ‘0’. depth. The stack is not readable or writable and is The PC increments by 2 to address sequential loaded with the current value of the corresponding instructions in the program memory. register when the processor vectors for an interrupt. The CALL, RCALL, GOTO and program branch The values in the fast register stack are then loaded instructions write to the program counter directly. For back into the working registers if the FAST RETURN these instructions, the contents of PCLATH and instruction is used to return from the interrupt. PCLATU are not transferred to the program counter. A low or high priority interrupt source will push values The contents of PCLATH and PCLATU will be into the stack registers. If both low and high priority transferred to the program counter by an operation that interrupts are enabled, the stack registers cannot be writes PCL. Similarly, the upper two bytes of the used reliably for low priority interrupts. If a high priority program counter will be transferred to PCLATH and interrupt occurs while servicing a low priority interrupt, PCLATU by an operation that reads PCL. This is useful the stack register values stored by the low priority for computed offsets to the PC (see Section 4.8.1 interrupt will be overwritten. “Computed GOTO”). If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a FAST CALL instruction must be executed. Example 4-1 shows a source code example that uses the fast register stack. DS41159D-page 40 2004 Microchip Technology Inc.
- 43. PIC18FXX8 4.5 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruc- tion is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-4. FIGURE 4-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC Mode) Fetch INST (PC) Execute INST (PC – 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory An “Instruction Cycle” consists of four Q cycles (Q1, The program memory is addressed in bytes. Instruc- Q2, Q3 and Q4). The instruction fetch and execute are tions are stored as two bytes or four bytes in program pipelined such that fetch takes one instruction cycle, memory. The Least Significant Byte of an instruction while decode and execute take another instruction word is always stored in a program memory location cycle. However, due to the pipelining, each instruction with an even address (LSB = 0). Figure 4-3 shows an effectively executes in one cycle. If an instruction example of how instruction words are stored in the causes the program counter to change (e.g., GOTO), program memory. To maintain alignment with instruc- two cycles are required to complete the instruction tion boundaries, the PC increments in steps of 2 and (Example 4-2). the LSB will always read ‘0’ (see Section 4.4 “PCL, A fetch cycle begins with the Program Counter (PC) PCLATH and PCLATU”). incrementing in Q1. The CALL and GOTO instructions have an absolute In the execution cycle, the fetched instruction is latched program memory address embedded into the instruc- into the “Instruction Register” (IR) in cycle Q1. This tion. Since instructions are always stored on word instruction is then decoded and executed during the boundaries, the data contained in the instruction is a Q2, Q3 and Q4 cycles. Data memory is read during Q2 word address. The word address is written to PC<20:1>, (operand read) and written during Q4 (destination which accesses the desired byte address in program write). memory. Instruction #2 in Example 4-3 shows how the instruction “GOTO 000006h” is encoded in the program memory. Program branch instructions that encode a relative address offset operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions by which the PC will be offset. Section 25.0 “Instruction Set Summary” provides further details of the instruction set. 2004 Microchip Technology Inc. DS41159D-page 41
- 44. PIC18FXX8 EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. EXAMPLE 4-3: INSTRUCTIONS IN PROGRAM MEMORY Instruction Opcode Memory Address — 000007h MOVLW 055h 0E55h 55h 000008h 0Eh 000009h GOTO 000006h 0EF03h, 0F000h 03h 00000Ah 0EFh 00000Bh 00h 00000Ch 0F0h 00000Dh MOVFF 123h, 456h 0C123h, 0F456h 23h 00000Eh 0C1h 00000Fh 56h 000010h 0F4h 000011h — 000012h DS41159D-page 42 2004 Microchip Technology Inc.
- 45. PIC18FXX8 4.7.1 TWO-WORD INSTRUCTIONS instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling The PIC18FXX8 devices have 4 two-word instructions: function. MOVFF, CALL, GOTO and LFSR. The 4 Most Signifi- cant bits of the second word are set to ‘1’s and indicate The offset value (value in WREG) specifies the number a special NOP instruction. The lower 12 bits of the of bytes that the program counter should advance. second word contain the data to be used by the In this method, only one data byte may be stored in instruction. If the first word of the instruction is executed, each instruction location and room on the return the data in the second word is accessed. If the second address stack is required. word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is Note 1: The LSb of PCL is fixed to a value of ‘0’. necessary when the two-word instruction is preceded by Hence, computed GOTO to an odd address a conditional instruction that changes the PC. A program is not possible. example that demonstrates this concept is shown in 2: The ADDWF PCL instruction does not Example 4-4. Refer to Section 25.0 “Instruction Set update PCLATH/PCLATU. A read opera- Summary” for further details of the instruction set. tion on PCL must be performed to update PCLATH and PCLATU. 4.8 Look-up Tables 4.8.2 TABLE READS/TABLE WRITES Look-up tables are implemented two ways. These are: A better method of storing data in program memory • Computed GOTO allows 2 bytes of data to be stored in each instruction • Table Reads location. Look-up table data may be stored as 2 bytes per 4.8.1 COMPUTED GOTO program word by using table reads and writes. The A computed GOTO is accomplished by adding an offset Table Pointer (TBLPTR) specifies the byte address and to the program counter (ADDWF PCL). the Table Latch (TABLAT) contains the data that is read A look-up table can be formed with an ADDWF PCL from, or written to, program memory. Data is instruction and a group of RETLW 0xnn instructions. transferred to/from program memory, one byte at a WREG is loaded with an offset into the table before time. executing a call to that table. The first instruction of the A description of the table read/table write operation is called routine is the ADDWF PCL instruction. The next shown in Section 6.1 “Table Reads and Table Writes”. EXAMPLE 4-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code 2004 Microchip Technology Inc. DS41159D-page 43
- 46. PIC18FXX8 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, The register file can be accessed either directly or allowing up to 4096 bytes of data memory. Figure 4-6 indirectly. Indirect addressing operates through the File shows the data memory organization for the Select Registers (FSR). The operation of indirect PIC18FXX8 devices. addressing is shown in Section 4.12 “Indirect Addressing, INDF and FSR Registers”. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits Enhanced MCU devices may have banked memory in of the Bank Select Register (BSR<3:0>) select which the GPR area. GPRs are not initialized by a Power-on bank will be accessed. The upper 4 bits for the BSR are Reset and are unchanged on all other Resets. not implemented. Data RAM is available for use as GPR registers by all The data memory contains Special Function Registers instructions. Bank 15 (F00h to FFFh) contains SFRs. (SFRs) and General Purpose Registers (GPRs). The All other banks of data memory contain GPR registers, SFRs are used for control and status of the controller starting with Bank 0. and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s appli- 4.9.2 SPECIAL FUNCTION REGISTERS cation. The SFRs start at the last location of Bank 15 The Special Function Registers (SFRs) are registers (FFFh) and grow downwards. GPRs start at the first used by the CPU and peripheral modules for controlling location of Bank 0 and grow upwards. Any read of an the desired operation of the device. These registers are unimplemented location will read as ‘0’s. implemented as static RAM. A list of these registers is The entire data memory may be accessed directly or given in Table 4-1. indirectly. Direct addressing may require the use of the The SFRs can be classified into two sets: those asso- BSR register. Indirect addressing requires the use of ciated with the “core” function and those related to the the File Select Register (FSR). Each FSR holds a peripheral functions. Those registers related to the 12-bit address value that can be used to access any “core” are described in this section, while those related location in the data memory map without banking. to the operation of the peripheral features are The instruction set and architecture allow operations described in the section of that peripheral feature. across all banks. This may be accomplished by indirect The SFRs are typically distributed among the addressing or by the use of the MOVFF instruction. The peripherals whose functions they control. MOVFF instruction is a two-word/two-cycle instruction, The unused SFR locations will be unimplemented and that moves a value from one register to another. read as ‘0’s. See Table 4-1 for addresses for the SFRs. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 “Access Bank” provides a detailed description of the Access RAM. DS41159D-page 44 2004 Microchip Technology Inc.
- 47. PIC18FXX8 FIGURE 4-5: DATA MEMORY MAP FOR PIC18F248/448 BSR<3:0> Data Memory Map 00h Access RAM 000h = 0000 05Fh Bank 0 060h FFh GPR 0FFh 00h 100h = 0001 GPR Bank 1 FFh 1FFh 00h 200h = 0010 Bank 2 GPR FFh 300h Access Bank 00h Access Bank Low (GPR) 5Fh = 0011 60h Bank 3 Access Bank High Unused (SFR) = 1110 to Read ‘00h’ FFh Bank 14 When a = 0, the BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The next 160 bytes are Special Function Registers (from Bank 15). EFFh When a = 1, 00h F00h the BSR is used to specify = 1111 Unused F5Fh Bank 15 the RAM location that the SFR F60h FFh FFFh instruction uses. 2004 Microchip Technology Inc. DS41159D-page 45
- 48. PIC18FXX8 FIGURE 4-6: DATA MEMORY MAP FOR PIC18F258/458 BSR<3:0> Data Memory Map 00h Access RAM 000h = 0000 05Fh Bank 0 060h FFh GPR 0FFh 00h 100h = 0001 GPR Bank 1 FFh 1FFh = 0010 00h 200h Bank 2 GPR FFh 2FFh 00h 300h = 0011 Bank 3 GPR FFh 3FFh 400h = 0100 Access Bank Bank 4 GPR 4FFh 00h 00h 500h Access Bank low = 0101 Bank 5 GPR (GPR) 5Fh FFh 5FFh 60h 600h Access Bank high (SFR) FFh = 0110 Bank 6 Unused When a = 0, = 1110 to Read ‘00h’ the BSR is ignored and the Bank 14 Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). EFFh F00h The next 160 bytes are 00h SFR = 1111 F5Fh Special Function Registers Bank 15 SFR F60h (from Bank 15). FFh FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS41159D-page 46 2004 Microchip Technology Inc.
- 49. PIC18FXX8 TABLE 4-1: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(2) FBFh CCPR1H F9Fh IPR1 (2) FFEh TOSH FDEh POSTINC2 FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(2) FBCh ECCPR1H(5) F9Ch — (2) FFBh PCLATU FDBh PLUSW2 FBBh ECCPR1L(5) F9Bh — (5) FFAh PCLATH FDAh FSR2H FBAh ECCP1CON F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — FF8h TBLPTRU FD8h STATUS FB8h — F98h — FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL(5) F97h — FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS(5) F96h TRISE(5) FF5h TABLAT FD5h T0CON FB5h CVRCON(5) F95h TRISD(5) FF4h PRODH FD4h — FB4h CMCON(5) F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h — FF0h INTCON3 FD0h RCON FB0h — F90h — FEFh INDF0(2) FCFh TMR1H FAFh SPBRG F8Fh — (2) FEEh POSTINC0 FCEh TMR1L FAEh RCREG F8Eh — FEDh POSTDEC0(2) FCDh T1CON FADh TXREG F8Dh LATE(5) FECh PREINC0(2) FCCh TMR2 FACh TXSTA F8Ch LATD(5) (2) FEBh PLUSW0 FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h — FE7h INDF1(2) FC7h SSPSTAT FA7h EECON2 F87h — FE6h POSTINC1(2) FC6h SSPCON1 FA6h EECON1 F86h — FE5h POSTDEC1(2) FC5h SSPCON2 FA5h IPR3 F85h — FE4h PREINC1(2) FC4h ADRESH FA4h PIR3 F84h PORTE(5) FE3h PLUSW1(2) FC3h ADRESL FA3h PIE3 F83h PORTD(5) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h — FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ‘0’. 2: This is not a physical register. 3: Contents of register are dependent on WIN2:WIN0 bits in the CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip header file requirement. 5: These registers are not implemented on the PIC18F248 and PIC18F258. 2004 Microchip Technology Inc. DS41159D-page 47
- 50. PIC18FXX8 TABLE 4-1: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name F7Fh — F5Fh — F3Fh — F1Fh RXM1EIDL (4) (4) F7Eh — F5Eh CANSTATRO1 F3Eh CANSTATRO3 F1Eh RXM1EIDH F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h — F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h — F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh — F2Fh — F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTATRO2(4) F2Eh CANSTATRO4(4) F0Eh RXF3EIDH F6Dh RXB0D7(3) F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6(3) F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5(3) F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4(3) F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3(3) F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2(3) F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1(3) F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL (3) F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC(3) F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL(3) F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH(3) F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL(3) F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH(3) F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL (3) F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note: Shaded registers are available in Bank 15, while the rest are in Access Bank low. Note 1: Unimplemented registers are read as ‘0’. 2: This is not a physical register. 3: Contents of register are dependent on WIN2:WIN0 bits in the CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip header file requirement. 5: These registers are not implemented on the PIC18F248 and PIC18F258. DS41159D-page 48 2004 Microchip Technology Inc.
- 51. PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 30, 38 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 30, 38 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 30, 38 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 30, 39 PCLATU — — bit 21(2) Holding Register for PC<20:16> ---0 0000 30, 40 PCLATH Holding Register for PC<15:8> 0000 0000 30, 40 PCL PC Low Byte (PC<7:0>) 0000 0000 30, 40 TBLPTRU — — bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 30, 68 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 30, 68 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 30, 68 TABLAT Program Memory Table Latch 0000 0000 30, 68 PRODH Product Register High Byte xxxx xxxx 30, 75 PRODL Product Register Low Byte xxxx xxxx 30, 75 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 30, 79 INTCON2 RBPU INTEDG0 INTEDG1 — — TMR0IP — RBIP 111- -1-1 30, 80 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 30, 81 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 30, 55 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 30, 55 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 30, 55 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 30, 55 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 30, 55 FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 30, 55 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 30, 55 WREG Working Register xxxx xxxx 30, 55 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 30, 55 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 30, 55 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 30, 55 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 30, 55 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 30, 55 FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 31, 55 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 31, 55 BSR — — — — Bank Select Register ---- 0000 31, 54 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 31, 55 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 31, 55 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 31, 55 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 31, 55 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 31, 55 FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 31, 55 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 31, 55 STATUS — — — N OV Z DC C ---x xxxx 31, 57 TMR0H Timer0 Register High Byte 0000 0000 31, 111 TMR0L Timer0 Register Low Byte xxxx xxxx 31, 111 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 31, 109 OSCCON — — — — — — — SCS ---- ---0 31, 20 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 31, 261 WDTCON — — — — — — — SWDTEN ---- ---0 31, 272 RCON IPEN — — RI TO PD POR BOR 0--1 110q 31, 58, 91 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2004 Microchip Technology Inc. DS41159D-page 49
- 52. PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: TMR1H Timer1 Register High Byte xxxx xxxx 31, 116 TMR1L Timer1 Register Low Byte xxxx xxxx 31, 116 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 31, 113 TMR2 Timer2 Register 0000 0000 31, 118 PR2 Timer2 Period Register 1111 1111 31, 118 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 31, 117 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 31, 146 SSPADD SSP Address Register in I2C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 31, 152 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 31, 144, 153 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 31, 145, 145 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 31, 155 ADRESH A/D Result Register High Byte xxxx xxxx 31, 243 ADRESL A/D Result Register Low Byte xxxx xxxx 31, 243 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 31, 241 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 32, 242 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 32, 124 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 32, 124 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 32, 123 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 32, 133 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 32, 133 ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 32, 131 ECCP1DEL(1) EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 32, 140 ECCPAS(1) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 32, 142 CVRCON(1) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 32, 255 CMCON(1) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 32, 249 TMR3H Timer3 Register High Byte xxxx xxxx 32, 121 TMR3L Timer3 Register Low Byte xxxx xxxx 32, 121 T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 32, 119 SPBRG USART Baud Rate Generator 0000 0000 32, 185 RCREG USART Receive Register 0000 0000 32, 191 TXREG USART Transmit Register 0000 0000 32, 189 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 32, 183 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 32, 184 EEADR EEPROM Address Register xxxx xxxx 32, 59 EEDATA EEPROM Data Register xxxx xxxx 32, 59 EECON2 EEPROM Control Register 2 (not a physical register) xxxx xxxx 32, 59 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 32, 60, 67 IPR3 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 32, 90 PIR3 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 32, 84 PIE3 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 32, 87 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 32, 89 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 32, 83 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 32, 86 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. DS41159D-page 50 2004 Microchip Technology Inc.
- 53. PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 32, 88 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 32, 82 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 32, 85 TRISE(1) IBF OBF IBOV PSPMODE — Data Direction bits for PORTE(1) 0000 -111 33, 105 TRISD(1) Data Direction Control Register for PORTD(1) 1111 1111 33, 102 TRISC Data Direction Control Register for PORTC 1111 1111 33, 100 TRISB Data Direction Control Register for PORTB 1111 1111 33, 96 TRISA(3) — Data Direction Control Register for PORTA -111 1111 33, 93 LATE(1) — — — — — Read PORTE Data Latch, Write ---- -xxx 33, 104 PORTE Data Latch(1) LATD(1) Read PORTD Data Latch, Write PORTD Data Latch(1) xxxx xxxx 33, 102 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 33, 100 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 33, 96 LATA(3) — Read PORTA Data Latch, Write PORTA Data Latch -xxx xxxx 33, 93 PORTE(1) — — — — — Read PORTE pins, Write PORTE Data ---- -xxx 33, 104 Latch(1) PORTD(1) Read PORTD pins, Write PORTD Data Latch(1) xxxx xxxx 33, 102 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 33, 100 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 33, 96 PORTA(3) — Read PORTA pins, Write PORTA Data Latch -x0x 0000 33, 93 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 33, 209 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 33, 214 COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 33, 205 CIOCON — — ENDRHI CANCAP — — — — --00 ---- 33, 221 BRGCON3 — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 -0-- -000 33, 220 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 33, 219 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 33, 218 CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — xxxx xxx- 33, 201 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 33, 214 RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 33, 214 RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx 33, 214 RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 33, 214 RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 33, 214 RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 33, 214 RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 33, 214 RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 33, 214 RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 34, 213 RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 34, 213 RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 34, 212 RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 34, 212 RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 34, 212 RXB0CON RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 000- 0000 34, 210 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2004 Microchip Technology Inc. DS41159D-page 51
- 54. PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: CANSTATRO1 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 34, 214 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 34, 214 RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 34, 214 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 34, 214 RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 34, 214 RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 34, 214 RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx 34, 214 RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx 34, 214 RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 34, 213 RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 34, 213 RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 34, 212 RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 34, 212 RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 34, 212 RXB1CON RXFUL RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 000- 0000 34, 211 CANSTATRO2 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 34, 208 TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 34, 208 TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 34, 208 TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 34, 208 TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 34, 208 TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 34, 208 TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 34, 208 TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 34, 208 TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 34, 209 TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 34, 208 TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 34, 207 TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 34, 207 TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 35, 207 TXB0CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 35, 206 CANSTATRO3 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 35, 208 TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 35, 208 TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 35, 208 TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 35, 208 TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 35, 208 TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 35, 208 TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 35, 208 TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 35, 208 TXB1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 35, 209 TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 35, 208 TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 35, 207 TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 35, 207 TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 35, 207 TXB1CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0000 35, 206 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. DS41159D-page 52 2004 Microchip Technology Inc.
- 55. PIC18FXX8 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: CANSTATRO4 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — xxx- xxx- 33, 202 TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 35, 208 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 35, 208 TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 35, 208 TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 35, 208 TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 35, 208 TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 35, 208 TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 35, 208 TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 35, 208 TXB2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 35, 209 TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 35, 208 TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 35, 207 TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 35, 207 TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 35, 207 TXB2CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 35, 206 RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 35, 217 RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 35, 217 RXM1SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx 36, 217 RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 216 RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 217 RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 217 RXM0SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx 36, 217 RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 216 RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF4SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF3SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 36, 216 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 36, 216 RXF0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 36, 215 RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 36, 215 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2004 Microchip Technology Inc. DS41159D-page 53
- 56. PIC18FXX8 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement that The need for a large general purpose memory space is very useful for C compiler code optimization. The dictates a RAM banking scheme. The data memory is techniques used by the C compiler are also useful for partitioned into sixteen banks. When using direct programs written in assembly. addressing, the BSR should be configured for the This data memory region can be used for: desired bank. • Intermediate computational values BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read ‘0’s and • Local variables of subroutines writes will have no effect. • Faster context saving/switching of variables A MOVLB instruction has been provided in the • Common variables instruction set to assist in selecting banks. • Faster evaluation/control of SFRs (no banking) If the currently selected bank is not implemented, any The Access Bank is comprised of the upper 160 bytes read will return all ‘0’s and all writes are ignored. The in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. Status register bits will be set/cleared as appropriate for These two sections will be referred to as Access Bank the instruction performed. High and Access Bank Low, respectively. Figure 4-6 indicates the Access Bank areas. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in A MOVFF instruction ignores the BSR since the 12-bit the Access Bank. addresses are embedded into the instruction word. When forced in the Access Bank (a = 0), the last Section 4.12 “Indirect Addressing, INDF and FSR address in Access Bank Low is followed by the first Registers” provides a description of indirect address- address in Access Bank High. Access Bank High maps ing, which allows linear addressing of the entire RAM most of the Special Function Registers so that these space. registers can be accessed without any software overhead. FIGURE 4-7: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 From Opcode(3) 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h 0E00h 0F00h Data Memory(1) 0FFh 1FFh 0EFFh 0FFFh Bank 0 Bank 1 Bank 14 Bank 15 Note 1: For register file map detail, see Table 4-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS41159D-page 54 2004 Microchip Technology Inc.
- 57. PIC18FXX8 4.12 Indirect Addressing, INDF and If INDF0, INDF1 or INDF2 are read indirectly via an FSR Registers FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the Indirect addressing is a mode of addressing data mem- operation will be equivalent to a NOP instruction and the ory where the data memory address in the instruction Status bits are not affected. is not fixed. A SFR register is used as a pointer to the data memory location that is to be read or written. Since 4.12.1 INDIRECT ADDRESSING this pointer is in RAM, the contents can be modified by OPERATION the program. This can be useful for data tables in the Each FSR register has an INDF register associated with data memory and for software stacks. Figure 4-8 it, plus four additional register addresses. Performing an shows the operation of indirect addressing. This shows operation on one of these five registers determines how the moving of the value to the data memory address the FSR will be modified during indirect addressing. specified by the value of the FSR register. • When data access is done to one of the five Indirect addressing is possible by using one of the INDF INDFn locations, the address selected will registers. Any instruction using the INDF register actually configure the FSRn register to: accesses the register indicated by the File Select Regis- ter, FSR. Reading the INDF register itself, indirectly - Do nothing to FSRn after an indirect access (FSR = 0), will read 00h. Writing to the INDF register (no change) – INDFn indirectly, results in a no operation. The FSR register - Auto-decrement FSRn after an indirect contains a 12-bit address which is shown in Figure 4-8. access (post-decrement) – POSTDECn The INDFn (0 ≤ n ≤ 2) register is not a physical register. - Auto-increment FSRn after an indirect Addressing INDFn actually addresses the register access (post-increment) – POSTINCn whose address is contained in the FSRn register - Auto-increment FSRn before an indirect (FSRn is a pointer). This is indirect addressing. access (pre-increment) – PREINCn Example 4-5 shows a simple use of indirect addressing - Use the value in the WREG register as an to clear the RAM in Bank 1 (locations 100h-1FFh) in a offset to FSRn. Do not modify the value of the minimum number of instructions. WREG or the FSRn register after an indirect access (no change) – PLUSWn EXAMPLE 4-5: HOW TO CLEAR RAM When using the auto-increment or auto-decrement (BANK 1) USING features, the effect on the FSR is not reflected in the INDIRECT ADDRESSING Status register. For example, if the indirect address LFSR FSR0, 100h ; causes the FSR to equal ‘0’, the Z bit will not be set. NEXT CLRF POSTINC0 ; Clear INDF Incrementing or decrementing an FSR affects all ; register 12 bits. That is, when FSRnL overflows from an ; & inc pointer increment, FSRnH will be incremented automatically. BTFSS FSR0H, 1 ; All done ; w/ Bank1? Adding these features allows the FSRn to be used as a BRA NEXT ; NO, clear next software stack pointer in addition to its uses for table CONTINUE ; operations in data memory. : ; YES, continue Each FSR has an address associated with it that There are three indirect addressing registers. To performs an indexed indirect access. When a data address the entire data memory space (4096 bytes), access to this INDFn location (PLUSWn) occurs, the these registers are 12 bits wide. To store the 12 bits of FSRn is configured to add the 2’s complement value in addressing information, two 8-bit registers are the WREG register and the value in FSR to form the required. These indirect addressing registers are: address before an indirect access. The FSR value is not changed. 1. FSR0: composed of FSR0H:FSR0L 2. FSR1: composed of FSR1H:FSR1L If an FSR register contains a value that indicates one of 3. FSR2: composed of FSR2H:FSR2L the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP In addition, there are registers INDF0, INDF1 and (Status bits are not affected). INDF2, which are not physically implemented. Reading or writing to these registers activates indirect address- If an indirect addressing operation is done where the ing, with the value in the corresponding FSR register target address is an FSRnH or FSRnL register, the being the address of the data. write operation will dominate over the pre- or post-increment/decrement functions. If an instruction writes a value to INDF0, the value will be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2004 Microchip Technology Inc. DS41159D-page 55
- 58. PIC18FXX8 FIGURE 4-8: INDIRECT ADDRESSING Indirect Addressing FSR Register 11 8 7 0 FSRnH FSRnL Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-1. DS41159D-page 56 2004 Microchip Technology Inc.
- 59. PIC18FXX8 4.13 Status Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as The Status register, shown in Register 4-2, contains the 000u u1uu (where u = unchanged). arithmetic status of the ALU. The Status register can be the destination for any instruction, as with any other It is recommended, therefore, that only BCF, BSF, register. If the Status register is the destination for an SWAPF, MOVFF and MOVWF instructions are used to instruction that affects the Z, DC, C, OV or N bits, then alter the Status register, because these instructions do the write to these five bits is disabled. These bits are set not affect the Z, C, DC, OV or N bits from the Status or cleared according to the device logic. Therefore, the register. For other instructions which do not affect the result of an instruction with the Status register as status bits, see Table 25-2. destination may be different than intended. Note: The C and DC bits operate as a Borrow and Digit Borrow bit respectively, in subtraction. REGISTER 4-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU operation was negative (ALU MSb = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRCF, RRNCF, RLCF and RLNCF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 C: Carry/Borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 57
- 60. PIC18FXX8 4.14 RCON Register Note 1: If the BOREN configuration bit is set, The Reset Control (RCON) register contains flag bits BOR is ‘1’ on Power-on Reset. If the that allow differentiation between the sources of a BOREN configuration bit is clear, BOR is device Reset. These flags include the TO, PD, POR, unknown on Power-on Reset. BOR and RI bits. This register is readable and writable. The BOR status bit is a “don’t care” and is not necessarily predictable if the brown- out circuit is disabled (the BOREN config- uration bit is clear). BOR must then be set by the user and checked on subsequent Resets to see if it is clear, indicating a brown-out has occurred. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 4-3: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R/W R/W R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 58 2004 Microchip Technology Inc.
- 61. PIC18FXX8 5.0 DATA EEPROM MEMORY 5.1 EEADR Register The data EEPROM is readable and writable during The address register can address up to a maximum of normal operation over the entire VDD range. The data 256 bytes of data EEPROM. memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the 5.2 EECON1 and EECON2 Registers Special Function Registers (SFR). EECON1 is the control register for EEPROM memory There are four SFRs used to read and write the accesses. program and data EEPROM memory. These registers are: EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used • EECON1 exclusively in the EEPROM write sequence. • EECON2 Control bits, RD and WR, initiate read and write opera- • EEDATA tions, respectively. These bits cannot be cleared, only • EEADR set, in software. They are cleared in hardware at the The EEPROM data memory allows byte read and write. completion of the read or write operation. The inability When interfacing to the data memory block, EEDATA to clear the WR bit in software prevents the accidental holds the 8-bit data for read/write and EEADR holds the or premature termination of a write operation. address of the EEPROM location being accessed. The The WREN bit, when set, will allow a write operation. PIC18FXX8 devices have 256 bytes of data EEPROM On power-up, the WREN bit is clear. The WRERR bit is with an address range from 00h to FFh. set when a write operation is interrupted by a MCLR The EEPROM data memory is rated for high erase/ Reset, or a WDT Time-out Reset, during normal oper- write cycles. A byte write automatically erases the loca- ation. In these situations, the user can check the tion and writes the new data (erase-before-write). The WRERR bit and rewrite the location. It is necessary to write time is controlled by an on-chip timer. The write reload the data and address registers (EEDATA and time will vary with voltage and temperature, as well as EEADR) due to the Reset condition forcing the from chip-to-chip. Please refer to the specifications for contents of the registers to zero. exact limits. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. 2004 Microchip Technology Inc. DS41159D-page 59
- 62. PIC18FXX8 REGISTER 5-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (reset by hardware) 0 = Perform write only bit 3 WRERR: Write Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM or Flash memory bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Settable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 60 2004 Microchip Technology Inc.
- 63. PIC18FXX8 5.3 Reading the Data EEPROM 5.4 Writing to the Data EEPROM Memory Memory To read a data memory location, the user must write the To write an EEPROM data location, the address must address to the EEADR register, clear the EEPGD and first be written to the EEADR register and the data writ- CFGS control bits (EECON1<7:6>) and then set ten to the EEDATA register. Then, the sequence in control bit RD (EECON1<0>). The data is available in Example 5-2 must be followed to initiate the write cycle. the very next instruction cycle of the EEDATA register; The write will not initiate if the above sequence is not therefore, it can be read by the next instruction. exactly followed (write 55h to EECON2, write 0AAh to EEDATA will hold this value until another read EECON2, then set WR bit) for each byte. It is strongly operation or until it is written to by the user (during a recommended that interrupts be disabled during this write operation). code segment. Additionally, the WREN bit in EECON1 must be set to EXAMPLE 5-1: DATA EEPROM READ enable writes. This mechanism prevents accidental MOVLW DATA_EE_ADDR ; writes to data EEPROM due to unexpected code exe- MOVWF EEADR ;Data Memory Address cution (i.e., runaway programs). The WREN bit should ;to read be kept clear at all times, except when updating the BCF EECON1, EEPGD ;Point to DATA memory EEPROM. The WREN bit is not cleared by hardware. BCS EECON1, CFGS ; BSF EECON1, RD ;EEPROM Read After a write sequence has been initiated, clearing the MOVF EEDATA, W ;W = EEDATA WREN bit will not affect the current write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Write Complete Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or roll this bit. EEIF must be cleared by software. EXAMPLE 5-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access program FLASH or Data EEPROM memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable interrupts Required MOVLW 55h ; Sequence MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable interrupts . ; user code execution . . BCF EECON1, WREN ; Disable writes on write complete (EEIF set) 2004 Microchip Technology Inc. DS41159D-page 61
- 64. PIC18FXX8 5.5 Write Verify 5.7 Operation During Code-Protect Depending on the application, good programming Data EEPROM memory has its own code-protect practice may dictate that the value written to the mechanism. External read and write operations are memory should be verified against the original value. disabled if either of these mechanisms are enabled. This should be used in applications where excessive The microcontroller itself can both read and write to the writes can stress bits near the specification limit. internal data EEPROM, regardless of the state of the Generally, a write failure will be a bit which was written code-protect configuration bit. Refer to Section 24.0 as a ‘1’, but reads back as a ‘0’ (due to leakage off the “Special Features of the CPU” for additional cell). information. 5.6 Protection Against Spurious Write 5.8 Using the Data EEPROM There are conditions when the device may not want to The data EEPROM is a high-endurance, byte address- write to the data EEPROM memory. To protect against able array that has been optimized for the storage of spurious EEPROM writes, various mechanisms have frequently changing information (e.g., program been built-in. On power-up, the WREN bit is cleared. variables or other data that are updated often). Also, the Power-up Timer (72 ms duration) prevents Frequently changing values will typically be updated EEPROM write. more often than specification D124 or D124A. If this is The write initiate sequence and the WREN bit together not the case, an array refresh must be performed. For reduce the probability of an accidental write during this reason, variables that change infrequently (such as brown-out, power glitch or software malfunction. constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 5-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A. EXAMPLE 5-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA Loop ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS41159D-page 62 2004 Microchip Technology Inc.
- 65. PIC18FXX8 TABLE 5-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u EEADR EEPROM Address Register xxxx xxxx uuuu uuuu EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 63
- 66. PIC18FXX8 NOTES: DS41159D-page 64 2004 Microchip Technology Inc.
- 67. PIC18FXX8 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on • Table Read (TBLRD) blocks of 8 bytes at a time. Program memory is erased • Table Write (TBLWT) in blocks of 64 bytes at a time. A bulk erase operation The program memory space is 16 bits wide, while the may not be issued from user code. data RAM space is 8 bits wide. Table reads and table Writing or erasing program memory will cease instruc- writes move data between these two memory spaces tion fetches until the operation is complete. The through an 8-bit register (TABLAT). program memory cannot be accessed during the write Table read operations retrieve data from program or erase, therefore, code cannot execute. An internal memory and place it into the data RAM space. programming timer terminates program memory writes Figure 6-1 shows the operation of a table read with and erases. program memory and data RAM. A value written to program memory does not need to be Table write operations store data from the data memory a valid instruction. Executing a program memory space into holding registers in program memory. The location that forms an invalid instruction results in a procedure to write the contents of the holding registers NOP. into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2004 Microchip Technology Inc. DS41159D-page 65
- 68. PIC18FXX8 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. 6.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set when a write operation is interrupted by a MCLR • TBLPTR registers Reset or a WDT Time-out Reset during normal opera- tion. In these situations, the user can check the 6.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EECON1 is the control register for memory accesses. EEADR) due to Reset values of zero. EECON2 is not a physical register. Reading EECON2 Control bits, RD and WR, initiate read and write opera- will read all ‘0’s. The EECON2 register is used tions, respectively. These bits cannot be cleared, only exclusively in the memory write and erase sequences. set, in software. They are cleared in hardware at the Control bit EEPGD determines if the access will be a completion of the read or write operation. The inability program or data EEPROM memory access. When to clear the WR bit in software prevents the accidental clear, any subsequent operations will operate on the or premature termination of a write operation. The RD data EEPROM memory. When set, any subsequent bit cannot be set when accessing program memory operations will operate on the program memory. (EEPGD = 1). Control bit CFGS determines if the access will be to the Note: Interrupt flag bit, EEIF in the PIR2 register, Configuration/Calibration registers or to program is set when write is complete. It must be memory/data EEPROM memory. When set, cleared in software. subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 24.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS41159D-page 66 2004 Microchip Technology Inc.
- 69. PIC18FXX8 REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access Configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Write Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM or Flash memory bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Settable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 67
- 70. PIC18FXX8 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch is used to hold Flash program memory. 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the Table memory and data RAM. Pointer determine which byte is read from program memory into TABLAT. 6.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight The Table Pointer (TBLPTR) addresses a byte within program memory holding registers is written to. When the program memory. The TBLPTR is comprised of the timed write to program memory (long write) begins, three SFR registers: Table Pointer Upper Byte, Table the 19 MSbs of the Table Pointer, TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:3>), will determine which program (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- memory block of 8 bytes is written to. For more detail, ters join to form a 22-bit wide pointer. The low-order see Section 6.5 “Writing to Flash Program Memory”. 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the device ID, the user ID and the configuration bits. 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table Figure 6-3 describes the relevant boundaries of operation. These operations are shown in Table 6-1. TBLPTR based on Flash program memory operations. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE – TBLPTR<21:6> WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> DS41159D-page 68 2004 Microchip Technology Inc.
- 71. PIC18FXX8 6.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_LSB TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_MSB 2004 Microchip Technology Inc. DS41159D-page 69
- 72. PIC18FXX8 6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer with address of row being supported. erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase operation: controller itself, a block of 64 bytes of program memory • set the EEPGD bit to point to program memory; is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. • set the WREN bit to enable writes; TBLPTR<5:0> are ignored. • set the FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable 4. Write 55h to EECON2. write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the row erase For protection, the write initiate sequence for EECON2 cycle. must be used. 7. The CPU will stall for duration of the erase (about 2 ms using internal timer). A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write 8. Re-enable interrupts. cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW upper (CODE_ADDR) ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high (CODE_ADDR) MOVWF TBLPTRH MOVLW low (CODE_ADDR) MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to FLASH program memory BCF EECON1, CFGS ; access FLASH program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW 0AAh Sequence MOVWF EECON2 ; write 0AAH BSF EECON1, WR ; start erase (CPU stall) NOP ; NOP needed for proper code execution BSF INTCON, GIE ; re-enable interrupts DS41159D-page 70 2004 Microchip Technology Inc.
- 73. PIC18FXX8 6.5 Writing to Flash Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. The sequence of events for programming an internal program memory location should be: Table writes are used internally to load the holding registers needed to program the Flash memory. There 1. Read 64 bytes into RAM. are 8 holding registers used by the table writes for 2. Update data values in RAM as necessary. programming. 3. Load Table Pointer with address being erased. Since the Table Latch (TABLAT) is only a single byte, 4. Do the row erase procedure. the TBLWT instruction has to be executed 8 times for 5. Load Table Pointer with address of first byte each programming operation. All of the table write being written. operations will essentially be short writes, because only 6. Write the first 8 bytes into the holding registers the holding registers are written. At the end of updating using the TBLWT instruction, auto-increment 8 registers, the EECON1 register must be written to, to may be used. start the programming operation with a long write. 7. Set the EECON1 register for the write operation: The long write is necessary for programming the inter- • set the EEPGD bit to point to program memory; nal Flash. Instruction execution is halted while in a long • clear the CFGS bit to access program memory; write cycle. The long write will be terminated by the internal programming timer. • set the WREN to enable byte writes. 8. Disable interrupts. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip 9. Write 55h to EECON2. charge pump rated to operate over the voltage range of 10. Write AAh to EECON2. the device for byte or word operations. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Repeat steps 6-14 seven times to write 64 bytes. 15. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 8 bytes in the holding registers. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxx7 Holding Register Holding Register Holding Register Holding Register Program Memory 2004 Microchip Technology Inc. DS41159D-page 71
- 74. PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW high (BUFFER_ADDR) ; point to buffer MOVWF FSR0H MOVLW low (BUFFER_ADDR) MOVWF FSR0L MOVLW upper (CODE_ADDR) ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high (CODE_ADDR) MOVWF TBLPTRH MOVLW low (CODE_ADDR) MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW upper (CODE_ADDR) ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high (CODE_ADDR) MOVWF TBLPTRH MOVLW low (CODE_ADDR) MOVWF TBLPTRL BSF EECON1, EEPGD ; point to FLASH program memory BCF EECON1, CFGS ; access FLASH program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55H Sequence MOVLW 0AAh MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW high (BUFFER_ADDR) ; point to buffer MOVWF FSR0H MOVLW low (BUFFER_ADDR) MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER WRITE_WORD_TO_HREGS MOVFW POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS DS41159D-page 72 2004 Microchip Technology Inc.
- 75. PIC18FXX8 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) WRITE_WORD_TO_HREGS MOVFW POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, EEPGD ; point to FLASH program memory BCF EECON1, CFGS ; access FLASH program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h ; write 55h Required MOVWF EECON2 Sequence MOVLW 0AAh ; write 0AAh MOVWF EECON2 ; start program (CPU stall) BSF EECON1, WR NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done BRA PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory 6.5.2 WRITE VERIFY 6.5.4 PROTECTION AGAINST SPURIOUS Depending on the application, good programming WRITES practice may dictate that the value written to the To reduce the probability against spurious writes to memory should be verified against the original value. Flash program memory, the write initiate sequence This should be used in applications where excessive must also be followed. See Section 24.0 “Special writes can stress bits near the specification limit. Features of the CPU” for more detail. 6.5.3 UNEXPECTED TERMINATION OF 6.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section 24.0 “Special Features of the CPU” for location just programmed should be verified and repro- details on code protection of Flash program memory. grammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. 2004 Microchip Technology Inc. DS41159D-page 73
- 76. PIC18FXX8 TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte --00 0000 --00 0000 (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/ TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u GIEL EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000 (1) PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. DS41159D-page 74 2004 Microchip Technology Inc.
- 77. PIC18FXX8 7.0 8 x 8 HARDWARE MULTIPLIER 7.2 Operation Example 7-1 shows the sequence to do an 8 x 8 7.1 Introduction unsigned multiply. Only one instruction is required An 8 x 8 hardware multiplier is included in the ALU of when one argument of the multiply is already loaded in the PIC18FXX8 devices. By making the multiply a the WREG register. hardware operation, it completes in a single instruction Example 7-2 shows the sequence to do an 8 x 8 signed cycle. This is an unsigned multiply that gives a 16-bit multiply. To account for the sign bits of the arguments, result. The result is stored in the 16-bit product register each argument’s Most Significant bit (MSb) is tested pair (PRODH:PRODL). The multiplier does not affect and the appropriate subtractions are done. any flags in the ALUSTA register. Making the 8 x 8 multiplier execute in a single cycle EXAMPLE 7-1: 8 x 8 UNSIGNED gives the following advantages: MULTIPLY ROUTINE • Higher computational throughput MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> • Reduces code size requirements for multiply ; PRODH:PRODL algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY Table 7-1 shows a performance comparison between ROUTINE Enhanced devices using the single-cycle hardware MOVF ARG1, W multiply and performing the same function without the MULWF ARG2 ; ARG1 * ARG2 -> hardware multiply. ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG1 MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG2 TABLE 7-1: PERFORMANCE COMPARISON Program Time Cycles Routine Multiply Method Memory (Max) @ 40 MHz @ 10 MHz @ 4 MHz (Words) Without hardware multiply 13 69 6.9 µs 27.6 µs 69 µs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 µs Without hardware multiply 33 91 9.1 µs 36.4 µs 91 µs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 µs 6 µs Without hardware multiply 21 242 24.2 µs 96.8 µs 242 µs 16 x 16 unsigned Hardware multiply 24 24 2.4 µs 9.6 µs 24 µs Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs 16 x 16 signed Hardware multiply 36 36 3.6 µs 14.4 µs 36 µs 2004 Microchip Technology Inc. DS41159D-page 75
- 78. PIC18FXX8 Example 7-3 shows the sequence to do a 16 x 16 EQUATION 7-2: 16 x 16 SIGNED unsigned multiply. Equation 7-1 shows the algorithm MULTIPLICATION that is used. The 32-bit result is stored in four registers, ALGORITHM RES3:RES0. RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L EQUATION 7-1: 16 x 16 UNSIGNED = (ARG1H • ARG2H • 216) + MULTIPLICATION (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L)+ RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + = (ARG1H • ARG2H • 216) + (-1 • ARG1H<7> • ARG2H:ARG2L • 216) (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) EXAMPLE 7-4: 16 x 16 SIGNED MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 7-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES1 ; MULWF ARG2L ; ARG1L * ARG2L -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES1 ; MOVF ARG1H, W MOVFF PRODL, RES0 ; MULWF ARG2H ; ARG1H * ARG2H -> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1L, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1L * ARG2H -> ; ; PRODH:PRODL MOVF ARG1L, W MOVF PRODL, W ; MULWF ARG2H ; ARG1L * ARG2H -> ADDWF RES1 ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2 ; ADDWF RES1 ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3 ; ADDWFC RES2 ; ; CLRF WREG ; MOVF ARG1H, W ; ADDWFC RES3 ; MULWF ARG2L ; ARG1H * ARG2L -> ; ; PRODH:PRODL MOVF ARG1H, W ; MOVF PRODL, W ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWF RES1 ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2 ; ADDWF RES1 ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3 ; ADDWFC RES2 ; ; CLRF WREG ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES3 ; BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; Example 7-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation 7-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers, ; RES3:RES0. To account for the sign bits of the argu- SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? ments, each argument pair’s Most Significant bit (MSb) BRA CONT_CODE ; no, done is tested and the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS41159D-page 76 2004 Microchip Technology Inc.
- 79. PIC18FXX8 8.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18FXX8 devices have multiple interrupt compatible with PICmicro® mid-range devices. In sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each each interrupt source to be assigned a high priority source have no effect. The PEIE bit (INTCON register) level or a low priority level. The high priority interrupt enables/disables all peripheral interrupt sources. The vector is at 000008h and the low priority interrupt vector GIE bit (INTCON register) enables/disables all interrupt is at 000018h. High priority interrupt events will sources. All interrupts branch to address 000008h in override any low priority interrupts that may be in Compatibility mode. progress. When an interrupt is responded to, the global interrupt There are 13 registers that are used to control interrupt enable bit is cleared to disable further interrupts. If the operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. • INTCON High priority interrupt sources can interrupt a low priority interrupt. • INTCON2 • INTCON3 The return address is pushed onto the stack and the PC is loaded with the interrupt vector address • PIR1, PIR2, PIR3 (000008h or 000018h). Once in the Interrupt Service • PIE1, PIE2, PIE3 Routine, the source(s) of the interrupt can be deter- • IPR1, IPR2, IPR3 mined by polling the interrupt flag bits. The interrupt It is recommended that the Microchip header files, flag bits must be cleared in software before re-enabling supplied with MPLAB® IDE, be used for the symbolic bit interrupts to avoid recursive interrupts. names in these registers. This allows the assembler/ The “return from interrupt” instruction, RETFIE, exits compiler to automatically take care of the placement of the interrupt routine and sets the GIE bit (GIEH or GIEL these bits within the specified register. if priority levels are used), which re-enables interrupts. Each interrupt source has three bits to control its For external interrupt events, such as the INT pins or operation. The functions of these bits are: the PORTB input change interrupt, the interrupt latency • Flag bit to indicate that an interrupt event will be three to four instruction cycles. The exact occurred latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the • Enable bit that allows program execution to status of their corresponding enable bit or the GIE bit. branch to the interrupt vector address when the flag bit is set Note: Do not use the MOVFF instruction to modify • Priority bit to select high priority or low priority any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON register). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts. Setting the GIEL bit (INTCON register) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vec- tor immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. DS41159D-page 77
- 80. PIC18FXX8 FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE Wake-up if in Sleep mode RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF Interrupt to CPU INT2IE Vector to Location Peripheral Interrupt Flag bit INT2IP 0008h Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIE/GIEH TMR1IF TMR1IE TMR1IP IPEN XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF Interrupt to CPU TMR0IE Vector to Location TMR1IF TMR0IP 0018h TMR1IE RBIF TMR1IP RBIE XXXXIF RBIP PEIE/GIEL XXXXIE INT0IF XXXXIP GIE/GIEH INT0IE INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS41159D-page 78 2004 Microchip Technology Inc.
- 81. PIC18FXX8 8.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt The INTCON registers are readable and writable regis- condition occurs regardless of the state of ters which contain various enable, priority and flag bits. its corresponding enable bit or the global Because of the number of interrupts to be controlled, interrupt enable bit. User software should PIC18FXX8 devices have three INTCON registers. ensure the appropriate interrupt flag bits They are detailed in Register 8-1 through Register 8-3. are clear prior to enabling an interrupt. This feature allows software polling. REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON<7>) = 1: 1 = Enables all high priority interrupts 0 = Disables all priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 79
- 82. PIC18FXX8 REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 — — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4-3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. DS41159D-page 80 2004 Microchip Technology Inc.
- 83. PIC18FXX8 REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2004 Microchip Technology Inc. DS41159D-page 81
- 84. PIC18FXX8 8.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt The Peripheral Interrupt Request (PIR) registers condition occurs regardless of the state of contain the individual flag bits for the peripheral its corresponding enable bit or the Global interrupts (Register 8-4 through Register 8-6). Due to Interrupt Enable bit, GIE (INTCON the number of peripheral interrupt sources, there are register). three Peripheral Interrupt Request (Flag) registers 2: User software should ensure the appropri- (PIR1, PIR2, PIR3). ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 82 2004 Microchip Technology Inc.
- 85. PIC18FXX8 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF(1) — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit(1) 1 = Comparator input has changed 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = Write operation is complete (must be cleared in software) 0 = Write operation is not complete bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 ECCP1IF: ECCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 (TMR3) register capture occurred (must be cleared in software) 0 = No TMR1 (TMR3) register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 83
- 86. PIC18FXX8 REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF bit 7 bit 0 bit 7 IRXIF: Invalid Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = An invalid message has not occurred on the CAN bus bit 6 WAKIF: Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = Activity on the CAN bus has not occurred bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = An error has not occurred in the CAN module bit 4 TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message bit 3 TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 RXB1IF: Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message bit 0 RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 84 2004 Microchip Technology Inc.
- 87. PIC18FXX8 8.3 PIE Registers The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts (Register 8-7 through Register 8-9). Due to the number of peripheral interrupt sources, there are three Periph- eral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN is clear, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 8-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 85
- 88. PIC18FXX8 REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE(1) — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: EEPROM Write Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 ECCP1IE: ECCP1 Interrupt Enable bit(1) 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 86 2004 Microchip Technology Inc.
- 89. PIC18FXX8 REGISTER 8-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 bit 7 IRXIE: Invalid CAN Message Received Interrupt Enable bit 1 = Enables the invalid CAN message received interrupt 0 = Disables the invalid CAN message received interrupt bit 6 WAKIE: Bus Activity Wake-up Interrupt Enable bit 1 = Enables the bus activity wake-up interrupt 0 = Disables the bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enables the CAN bus error interrupt 0 = Disables the CAN bus error interrupt bit 4 TXB2IE: Transmit Buffer 2 Interrupt Enable bit 1 = Enables the Transmit Buffer 2 interrupt 0 = Disables the Transmit Buffer 2 interrupt bit 3 TXB1IE: Transmit Buffer 1 Interrupt Enable bit 1 = Enables the Transmit Buffer 1 interrupt 0 = Disables the Transmit Buffer 1 interrupt bit 2 TXB0IE: Transmit Buffer 0 Interrupt Enable bit 1 = Enables the Transmit Buffer 0 interrupt 0 = Disables the Transmit Buffer 0 interrupt bit 1 RXB1IE: Receive Buffer 1 Interrupt Enable bit 1 = Enables the Receive Buffer 1 interrupt 0 = Disables the Receive Buffer 1 interrupt bit 0 RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 interrupt 0 = Disables the Receive Buffer 0 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 87
- 90. PIC18FXX8 8.4 IPR Registers The Interrupt Priority (IPR) registers contain the individ- ual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set. REGISTER 8-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 88 2004 Microchip Technology Inc.
- 91. PIC18FXX8 REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP(1) — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: EEPROM Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ECCP1IP: ECCP1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit is unimplemented and reads as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 89
- 92. PIC18FXX8 REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: Invalid Message Received Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 RXB1IP: Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 90 2004 Microchip Technology Inc.
- 93. PIC18FXX8 8.5 RCON Register The Reset Control (RCON) register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”. REGISTER 8-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 4-3. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-3. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-3. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-3. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-3. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 91
- 94. PIC18FXX8 8.6 INT Interrupts 8.8 PORTB Interrupt-on-Change External interrupts on the RB0/INT0, RB1/INT1 and An input change on PORTB<7:4> sets flag bit RBIF RB2/CANTX/INT2 pins are edge triggered: either rising (INTCON register). The interrupt can be enabled/ if the corresponding INTEDGx bit is set in the disabled by setting/clearing enable bit RBIE (INTCON INTCON2 register, or falling if the INTEDGx bit is clear. register). Interrupt priority for PORTB interrupt-on- When a valid edge appears on the RBx/INTx pin, the change is determined by the value contained in the corresponding flag bit INTxIF is set. This interrupt can interrupt priority bit RBIP (INTCON2 register). be disabled by clearing the corresponding enable bit INTxIE. Flag bit INTxIF must be cleared in software in 8.9 Context Saving During Interrupts the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) During an interrupt, the return PC value is saved on the can wake-up the processor from Sleep if bit INTxIE was stack. Additionally, the WREG, Status and BSR set prior to going into Sleep. If the Global Interrupt registers are saved on the fast return stack. If a fast Enable bit, GIE, is set, the processor will branch to the return from interrupt is not used (see Section 4.3 “Fast interrupt vector following wake-up. Register Stack”), the user may need to save the WREG, Status and BSR registers in software. Depend- Interrupt priority for INT1 and INT2 is determined by the ing on the user’s application, other registers may also value contained in the interrupt priority bits INT1IP need to be saved. Example 8-1 saves and restores the (INTCON3<6>) and INT2IP (INTCON3<7>). There is WREG, Status and BSR registers during an Interrupt no priority bit associated with INT0; it is always a high Service Routine. priority interrupt source. 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh → 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h) in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON register). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register). See Section 11.0 “Timer0 Module” for further details. EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in Low Access bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS41159D-page 92 2004 Microchip Technology Inc.
- 95. PIC18FXX8 9.0 I/O PORTS Read-modify-write operations on the LATA register read and write the latched output value for PORTA. Depending on the device selected, there are up to five The RA4 pin is multiplexed with the Timer0 module general purpose I/O ports available on PIC18FXX8 clock input to become the RA4/T0CKI pin. The RA4/ devices. Some pins of the I/O ports are multiplexed T0CKI pin is a Schmitt Trigger input and an open-drain with an alternate function from the peripheral features output. All other RA port pins have TTL input levels and on the device. In general, when a peripheral is enabled, full CMOS output drivers. that pin may not be used as a general purpose I/O pin. The other PORTA pins are multiplexed with analog Each port has three registers for its operation: inputs and the analog VREF+ and VREF- inputs. The • TRIS register (Data Direction register) operation of each pin is selected by clearing/setting the • PORT register (reads the levels on the pins of the control bits in the ADCON1 register (A/D Control device) Register 1). On a Power-on Reset, these pins are • LAT register (output latch) configured as analog inputs and read as ‘0’. The data latch (LAT register) is useful for read-modify- Note: On a Power-on Reset, RA5 and RA3:RA0 write operations on the value that the I/O pins are are configured as analog inputs and read driving. as ‘0’. RA6 and RA4 are configured as digital inputs. 9.1 PORTA, TRISA and LATA The TRISA register controls the direction of the RA Registers pins, even when they are being used as analog inputs. PORTA is a 7-bit wide, bidirectional port. The corre- The user must ensure the bits in the TRISA register are sponding Data Direction register is TRISA. Setting a maintained set, when using them as analog inputs. TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a EXAMPLE 9-1: INITIALIZING PORTA high-impedance mode). Clearing a TRISA bit (= 0) will CLRF PORTA ; Initialize PORTA by make the corresponding PORTA pin an output (i.e., put ; clearing output data latches the contents of the output latch on the selected pin). On CLRF LATA ; Alternate method to clear a Power-on Reset, these pins are configured as inputs ; output data latches MOVLW 07h ; Configure A/D and read as ‘0’. MOVWF ADCON1 ; for digital inputs Reading the PORTA register reads the status of the MOVLW 0CFh ; Value used to initialize pins, whereas writing to it will write to the port latch. ; data direction MOVWF TRISA ; Set RA3:RA0 as inputs, ; RA5:RA4 as outputs 2004 Microchip Technology Inc. DS41159D-page 93
- 96. PIC18FXX8 FIGURE 9-1: RA3:RA0 AND RA5 PINS FIGURE 9-2: RA4/T0CKI PIN BLOCK BLOCK DIAGRAM DIAGRAM RD LATA RD LATA Data Bus Q D Data Bus D Q WR LATA or VDD WR PORTA WR LATA or CK Q P WR PORTA CK Q Data Latch N I/O pin(1) Data Latch D Q N I/O pin(1) D Q VSS Schmitt WR TRISA CK Trigger Q VSS WR TRISA CK Q Input Analog Input Mode TRIS Latch Buffer TRIS Latch TTL Input Buffer RD TRISA RD TRISA TTL Input Buffer Q D Q D EN EN RD PORTA RD PORTA TMR0 Clock Input SS Input (RA5 only) To A/D Converter and LVD Modules Note 1: I/O pin has diode protection to VSS only. Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 9-3: OSC2/CLKO/RA6 PIN BLOCK DIAGRAM (FOSC = 101, 111) From OSC1 Oscillator CLKO (FOSC/4) 1 Circuit Data Latch Data Bus Q 0 D VDD WR PORTA CK Q OSC2/CLKO P RA6 pin(2) TRIS Latch D Q N WR TRISA CK Q (FOSC = 100, 101, 110, 111) VSS RD TRISA Schmitt Trigger Input Buffer Q D Data Latch EN RD PORTA (FOSC = 110, 100) Note 1: CLKO is 1/4 of FOSC. 2: I/O pin has diode protection to VDD and VSS. DS41159D-page 94 2004 Microchip Technology Inc.
- 97. PIC18FXX8 TABLE 9-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0/CVREF bit 0 TTL Input/output, analog input or analog comparator voltage reference output. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output, analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output, analog input or VREF+. RA4/T0CKI bit 4 ST/OD Input/output, external clock input for Timer0, output is open-drain type. RA5/AN4/SS/LVDIN bit 5 TTL Input/output, analog input, slave select input for synchronous serial port or Low-Voltage Detect input. OSC2/CLKO/RA6 bit 6 TTL Oscillator clock output or input/output. Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open-Drain TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -00x 0000 -uuu uuuu LATA — Latch A Data Output Register -xxx xxxx -uuu uuuu TRISA — PORTA Data Direction Register -111 1111 -111 1111 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 uu-- uuuu Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2004 Microchip Technology Inc. DS41159D-page 95
- 98. PIC18FXX8 9.2 PORTB, TRISB and LATB This interrupt can wake the device from Sleep. The Registers user, in the Interrupt Service Routine, can clear the interrupt in the following manner: PORTB is an 8-bit wide, bidirectional port. The corre- a) Any read or write of PORTB (except with the sponding Data Direction register is TRISB. Setting a MOVFF instruction). This will end the mismatch TRISB bit (= 1) will make the corresponding PORTB condition. pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) b) Clear flag bit RBIF. will make the corresponding PORTB pin an output (i.e., A mismatch condition will continue to set flag bit RBIF. put the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and Read-modify-write operations on the LATB register, allow flag bit RBIF to be cleared. read and write the latched output value for PORTB. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations EXAMPLE 9-2: INITIALIZING PORTB where PORTB is only used for the interrupt-on-change CLRF PORTB ; Initialize PORTB by feature. Polling of PORTB is not recommended while ; clearing output using the interrupt-on-change feature. ; data latches CLRF LATB ; Alternate method Note 1: While in Low-Voltage ICSP mode, the ; to clear output RB5 pin can no longer be used as a ; data latches general purpose I/O pin and should not MOVLW 0CFh ; Value used to be held low during normal operation to ; initialize data protect against inadvertent ICSP mode ; direction entry. MOVWF TRISB ; Set RB3:RB0 as inputs ; RB5:RB4 as outputs 2: When using Low-Voltage ICSP Program- ; RB7:RB6 as inputs ming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, Each of the PORTB pins has a weak internal pull-up. A thereby setting RB5 as an output, LATB single control bit can turn on all the pull-ups. This is bit 5 must also be cleared for proper performed by clearing bit RBPU (INTCON2 register). operation. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of the PORTB pins (RB7:RB4) have an interrupt- on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt- on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit RBIF (INTCON register). DS41159D-page 96 2004 Microchip Technology Inc.
- 99. PIC18FXX8 FIGURE 9-4: RB7:RB4 PINS BLOCK FIGURE 9-5: RB1:RB0 PINS BLOCK DIAGRAM DIAGRAM VDD VDD RBPU(2) RBPU(2) Weak Weak P Pull-up P Pull-up Data Latch Data Latch Data Bus Data Bus D Q D Q I/O pin(1) I/O pin(1) WR LATB WR Port CK CK or WR PORTB TRIS Latch D Q TRIS Latch D Q TTL WR TRISB TTL Input CK Input Buffer Buffer WR TRIS ST CK Buffer RD TRISB RD LATB RD TRIS Latch Q D Q D RD PORTB EN Q1 EN Set RBIF RD Port Q D From other RBx/INTx RB7:RB4 pins Q3 EN Schmitt Trigger Buffer RBx/INTx Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). bit(s) and clear the RBPU bit (INTCON2 register). 2004 Microchip Technology Inc. DS41159D-page 97
- 100. PIC18FXX8 FIGURE 9-6: RB2/CANTX/INT2 PIN BLOCK DIAGRAM OPMODE2:OPMODE0 = 000 ENDRHI CANTX 0 RD LATB VDD Data Latch 1 Data Bus D Q P WR PORTB or WR LATB CK Q TRIS Latch RB2/CANTX/ D Q INT2 pin(1) N WR TRISB CK Q VSS Schmitt RD TRISB Trigger Q D EN RD PORTB Note 1: I/O pin has diode protection to VDD and VSS. FIGURE 9-7: RB3/CANRX PIN BLOCK DIAGRAM CANCON<7:5> VDD RBPU(2) P Weak Pull-up Data Latch Data Bus D Q I/O pin(1) WR LATB or PORTB CK TRIS Latch D Q WR TRISB CK TTL RD TRISB Input Buffer RD LATB Q D EN RD PORTB RB3 or CANRX Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). . DS41159D-page 98 2004 Microchip Technology Inc.
- 101. PIC18FXX8 TABLE 9-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. RB2/CANTX/ bit 2 TTL/ST(1) Input/output pin, CAN bus transmit pin or external interrupt 2 input. INT2 Internal software programmable weak pull-up. RB3/CANRX bit 3 TTL Input/output pin or CAN bus receive pin. Internal software programmable weak pull-up. RB4 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/PGM bit 5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage serial programming enable. RB6/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON2 RBPU INTEDG0 INTEDG1 — — TMR0IP — RBIP 111- -1-1 111- -1-1 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 11-1 0-00 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. 2004 Microchip Technology Inc. DS41159D-page 99
- 102. PIC18FXX8 9.3 PORTC, TRISC and LATC while other peripherals override the TRIS bit to make a Registers pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. PORTC is an 8-bit wide, bidirectional port. The corre- The pin override value is not loaded into the TRIS sponding Data Direction register is TRISC. Setting a register. This allows read-modify-write of the TRIS TRISC bit (= 1) will make the corresponding PORTC register, without concern due to peripheral overrides. pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., EXAMPLE 9-3: INITIALIZING PORTC put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by ; clearing output Read-modify-write operations on the LATC register, ; data latches read and write the latched output value for PORTC. CLRF LATC ; Alternate method ; to clear output PORTC is multiplexed with several peripheral functions ; data latches (Table 9-5). PORTC pins have Schmitt Trigger input MOVLW 0CFh ; Value used to buffers. ; initialize data When enabling peripheral functions, care should be ; direction taken in defining TRIS bits for each PORTC pin. Some MOVWF TRISC ; Set RC3:RC0 as inputs peripherals override the TRIS bit to make a pin an output, ; RC5:RC4 as outputs ; RC7:RC6 as inputs FIGURE 9-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Peripheral Out Select Peripheral Data Out 0 VDD P RD LATC 1 Data Bus D Q WR LATC or CK Q I/O pin(1) WR PORTC Data Latch TRIS OVERRIDE N D Q Pin Override Peripheral VSS WR TRISC TRIS RC0 Yes Timer1 Oscillator CK Q Override for Timer1/Timer3 TRIS Latch RC1 Yes Timer1 Oscillator for Timer1/Timer3 RD TRISC Schmitt RC2 No — Peripheral Enable Trigger RC3 Yes SPI™/I2C™ Q D Master Clock RC4 Yes I2C Data Out EN RC5 Yes SPI Data Out RD PORTC RC6 Yes USART Async Peripheral Data In Xmit, Sync Clock RC7 Yes USART Sync Data Out Note 1: I/O pins have diode protection to VDD and VSS. DS41159D-page 100 2004 Microchip Technology Inc.
- 103. PIC18FXX8 TABLE 9-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI bit 1 ST Input/output port pin or Timer1 oscillator input. RC2/CCP1 bit 2 ST Input/output port pin or Capture 1 input/Compare 1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST Input/output port pin or synchronous serial clock for SPI™/I2C™. RC4/SDI/SDA bit 4 ST Input/output port pin or SPI data in (SPI mode) or data I/O (I2C mode). RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output. RC6/TX/CK bit 6 ST Input/output port pin, addressable USART asynchronous transmit or addressable USART synchronous clock. RC7/RX/DT bit 7 ST Input/output port pin, addressable USART asynchronous receive or addressable USART synchronous data. Legend: ST = Schmitt Trigger input TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged 2004 Microchip Technology Inc. DS41159D-page 101
- 104. PIC18FXX8 9.4 PORTD, TRISD and LATD PORTD can be configured as an 8-bit wide, micro- Registers processor port (Parallel Slave Port or PSP) by setting the control bit PSPMODE (TRISE<4>). In this mode, Note: This port is only available on the the input buffers are TTL. See Section 10.0 “Parallel PIC18F448 and PIC18F458. Slave Port” for additional information. PORTD is an 8-bit wide, bidirectional port. The corre- PORTD is also multiplexed with the analog comparator sponding Data Direction register for the port is TRISD. module and the ECCP module. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output EXAMPLE 9-4: INITIALIZING PORTD driver in a high-impedance mode). Clearing a TRISD CLRF PORTD ; Initialize PORTD by bit (= 0) will make the corresponding PORTD pin an ; clearing output output (i.e., put the contents of the output latch on the ; data latches selected pin). CLRF LATD ; Alternate method ; to clear output Read-modify-write operations on the LATD register ; data latches read and write the latched output value for PORTD. MOVLW 07h ; comparator off MOVWF CMCON PORTD uses Schmitt Trigger input buffers. Each pin is MOVLW 0CFh ; Value used to individually configurable as an input or output. ; initialize data ; direction MOVWF TRISD ; Set RD3:RD0 as inputs ; RD5:RD4 as outputs ; RD7:RD6 as inputs FIGURE 9-9: PORTD BLOCK DIAGRAM IN I/O PORT MODE PORT/PSP Select PSP Data Out VDD P RD LATD Data Bus D Q WR LATD RD0/PSP0/ or CK Q N C1IN+ pin(1) PORTD Data Latch D Q Vss WR TRISD CK Q TRIS Latch RD TRISD Schmitt PSP Read Trigger Q D EN RD PORTD PSP Write C1IN+ Note 1: I/O pins have diode protection to VDD and VSS. DS41159D-page 102 2004 Microchip Technology Inc.
- 105. PIC18FXX8 TABLE 9-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0/C1IN+ bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or C1IN+ comparator input. RD1/PSP1/C1IN- bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or C1IN- comparator input. RD2/PSP2/C2IN+ bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or C2IN+ comparator input. RD3/PSP3/C2IN- bit 3 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 3 or C2IN- comparator input. RD4/PSP4/ECCP1/P1A bit 4 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 4 or ECCP1/P1A pin. RD5/PSP5/P1B bit 5 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 5 or P1B pin. RD6/PSP6/P1C bit 6 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 6 or P1C pin. RD7/PSP7/P1D bit 7 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 7 or P1D pin. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. 2004 Microchip Technology Inc. DS41159D-page 103
- 106. PIC18FXX8 9.5 PORTE, TRISE and LATE When the Parallel Slave Port is active, the PORTE pins Registers function as its control inputs. For additional details, refer to Section 10.0 “Parallel Slave Port”. Note: This port is only available on the PORTE pins are also multiplexed with inputs for the A/D PIC18F448 and PIC18F458. converter and outputs for the analog comparators. When PORTE is a 3-bit wide, bidirectional port. PORTE has selected as an analog input, these pins will read as ‘0’s. three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and Direction bits TRISE<2:0> control the direction of the RE RE2/AN7/CS/C2OUT) which are individually config- pins, even when they are being used as analog inputs. urable as inputs or outputs. These pins have Schmitt The user must make sure to keep the pins configured as Trigger input buffers. inputs when using them as analog inputs. Read-modify-write operations on the LATE register, EXAMPLE 9-5: INITIALIZING PORTE read and write the latched output value for PORTE. CLRF PORTE ; Initialize PORTE by The corresponding Data Direction register for the port ; clearing output is TRISE. Setting a TRISE bit (= 1) will make the ; data latches corresponding PORTE pin an input (i.e., put the corre- CLRF LATE ; Alternate method sponding output driver in a high-impedance mode). ; to clear output Clearing a TRISE bit (= 0) will make the corresponding ; data latches PORTE pin an output (i.e., put the contents of the MOVLW 03h ; Value used to ; initialize data output latch on the selected pin). ; direction The TRISE register also controls the operation of the MOVWF TRISE ; Set RE1:RE0 as inputs Parallel Slave Port through the control bits in the upper ; RE2 as an output half of the register. These are shown in Register 9-1. ; (RE4=0 - PSPMODE Off) FIGURE 9-10: PORTE BLOCK DIAGRAM Peripheral Out Select Peripheral Data Out 0 VDD P RD LATE 1 Data Bus D Q WR LATE I/O pin(1) CK Q or WR PORTE Data Latch N D Q VSS WR TRISE CK Q TRIS Override TRIS Latch RD TRISE Schmitt TRIS OVERRIDE Peripheral Enable Trigger Q D Pin Override Peripheral RE0 Yes PSP EN RD PORTE RE1 Yes PSP Peripheral Data In RE2 Yes PSP Note 1: I/O pins have diode protection to VDD and VSS. DS41159D-page 104 2004 Microchip Technology Inc.
- 107. PIC18FXX8 REGISTER 9-1: TRISE REGISTER R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 105
- 108. PIC18FXX8 TABLE 9-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/AN5/RD bit 0 ST/TTL(1) Input/output port pin, analog input or read control input in Parallel Slave Port mode. RE1/AN6/WR/C1OUT bit 1 ST/TTL(1) Input/output port pin, analog input, write control input in Parallel Slave Port mode or Comparator 1 output. RE2/AN7/CS/C2OUT bit 2 ST/TTL(1) Input/output port pin, analog input, chip select control input in Parallel Slave Port mode or Comparator 2 output. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111 PORTE — — — — — Read PORTE pin/ ---- -xxx ---- -uuu Write PORTE Data Latch LATE — — — — — Read PORTE Data Latch/ ---- -xxx ---- -uuu Write PORTE Data Latch ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. DS41159D-page 106 2004 Microchip Technology Inc.
- 109. PIC18FXX8 10.0 PARALLEL SLAVE PORT FIGURE 10-1: PORTD AND PORTE BLOCK DIAGRAM Note: The Parallel Slave Port is only available on (PARALLEL SLAVE PORT) PIC18F4X8 devices. One bit of PORTD In addition to its function as a general I/O port, PORTD Data Bus can also operate as an 8-bit wide Parallel Slave Port D Q (PSP) or microprocessor port. PSP operation is RDx pin controlled by the 4 upper bits of the TRISE register WR LATD CK or (Register 9-1). Setting control bit PSPMODE WR PORTD Data Latch TTL (TRISE<4>) enables PSP operation. In Slave mode, the port is asynchronously readable and writable by the Q D external world. The PSP can directly interface to an 8-bit micro- RD PORTD EN EN processor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting the control bit PSPMODE enables the PORTE I/O pins to become control inputs for the microprocessor port. RD LATD When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (chip select) input. For this Set Interrupt Flag functionality, the corresponding data direction bits of PSPIF (PIR1<7>) the TRISE register (TRISE<2:0>) must be configured as inputs (set). PORTE pins A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs Read RD TTL when both the CS and RD lines are first detected low. The timing for the control signals in Write and Read Chip Select TTL CS modes is shown in Figure 10-2 and Figure 10-3, respectively. Write TTL WR Note: I/O pins have diode protection to VDD and VSS. FIGURE 10-2: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF 2004 Microchip Technology Inc. DS41159D-page 107
- 110. PIC18FXX8 FIGURE 10-3: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF TABLE 10-1: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -000 LATE LATE Data Output bits ---- -xxx ---- -uuu TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS41159D-page 108 2004 Microchip Technology Inc.
- 111. PIC18FXX8 11.0 TIMER0 MODULE Register 11-1 shows the Timer0 Control register (T0CON). The Timer0 module has the following features: Figure 11-1 shows a simplified block diagram of the • Software selectable as an 8-bit or Timer0 module in 8-bit mode and Figure 11-2 shows a 16-bit timer/counter simplified block diagram of the Timer0 module in 16-bit • Readable and writable mode. • Dedicated 8-bit software programmable prescaler The T0CON register is a readable and writable register • Clock source selectable to be external or internal that controls all the aspects of Timer0, including the • Interrupt-on-overflow from FFh to 00h in 8-bit prescale selection. mode and FFFFh to 0000h in 16-bit mode Note: Timer0 is enabled on POR. • Edge select for external clock REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 109
- 112. PIC18FXX8 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus 1 8 RA4/T0CKI 1 pin(2) T0SE Sync with FOSC/4 0 Internal TMR0L Clocks Programmable 0 Prescaler (2 TCY Delay) 3 PSA Set Interrupt T0PS2, T0PS1, T0PS0 Flag bit TMR0IF (1) T0CS on Overflow Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE T0CKI pin(2) 1 1 Sync with T0SE Set Interrupt 0 Internal TMR0 FOSC/4 TMR0L High Byte Flag bit TMR0IF Clocks on Overflow Programmable 0 Prescaler 8 (2 TCY Delay) 3 Read TMR0L T0PS2, T0PS1, T0PS0 Write TMR0L T0CS(1) PSA 8 8 TMR0H 8 Data Bus<7:0> Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. DS41159D-page 110 2004 Microchip Technology Inc.
- 113. PIC18FXX8 11.1 Timer0 Operation 11.2.1 SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software Timer mode is selected by clearing the T0CS bit. In control (i.e., it can be changed “on-the-fly” during Timer mode, the Timer0 module will increment every program execution). instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work 11.3 Timer0 Interrupt around this by writing an adjusted value to the TMR0L The TMR0 interrupt is generated when the TMR0 register. register overflows from FFh to 00h in 8-bit mode or Counter mode is selected by setting the T0CS bit. In FFFFh to 0000h in 16-bit mode. This overflow sets the Counter mode, Timer0 will increment either on every TMR0IF bit. The interrupt can be masked by clearing rising or falling edge of pin RA4/T0CKI. The increment- the TMR0IE bit. The TMR0IF bit must be cleared in ing edge is determined by the Timer0 Source Edge software by the Timer0 module Interrupt Service Select bit (T0SE). Clearing the T0SE bit selects the Routine before re-enabling this interrupt. The TMR0 rising edge. Restrictions on the external clock input are interrupt cannot awaken the processor from Sleep discussed below. since the timer is shut-off during Sleep. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure 11.4 16-Bit Mode Timer Reads the external clock can be synchronized with the internal and Writes phase clock (TOSC). Also, there is a delay in the actual Timer0 can be set in 16-bit mode by clearing the incrementing of Timer0 after synchronization. T08BIT in T0CON. Registers TMR0H and TMR0L are used to access the 16-bit timer value. 11.2 Prescaler TMR0H is not the high byte of the timer/counter in An 8-bit counter is available as a prescaler for the 16-bit mode, but is actually a buffered version of the Timer0 module. The prescaler is not readable or high byte of Timer0 (refer to Figure 11-1). The high byte writable. of the Timer0 timer/counter is not directly readable nor The PSA and T0PS2:T0PS0 bits determine the writable. TMR0H is updated with the contents of the prescaler assignment and prescale ratio. high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without Clearing bit PSA will assign the prescaler to the Timer0 having to verify that the read of the high and low byte module. When the prescaler is assigned to the Timer0 were valid, due to a rollover between successive reads module, prescale values of 1:2, 1:4, ..., 1:256 are of the high and low byte. selectable. A write to the high byte of Timer0 must also take place When assigned to the Timer0 module, all instructions through the TMR0H Buffer register. Timer0 high byte is writing to the TMR0 register (e.g., CLRF TMR0, MOVWF updated with the contents of the buffered value of TMR0, BSF TMR0, x.... etc.) will clear the prescaler TMR0H when a write occurs to TMR0L. This allows all count. 16 bits of Timer0 to be updated at once. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA — PORTA Data Direction Register(1) -111 1111 -111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: Bit 6 of PORTA, LATA and TRISA is enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, it is disabled and reads as ‘0’. 2004 Microchip Technology Inc. DS41159D-page 111
- 114. PIC18FXX8 NOTES: DS41159D-page 112 2004 Microchip Technology Inc.
- 115. PIC18FXX8 12.0 TIMER1 MODULE Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 The Timer1 module timer/counter has the following module, as well as contains the Timer1 Oscillator features: Enable bit (T1OSCEN). Timer1 can be enabled/ • 16-bit timer/counter disabled by setting/clearing control bit, TMR1ON (two 8-bit registers: TMR1H and TMR1L) (T1CON register). • Readable and writable (both registers) Figure 12-1 is a simplified block diagram of the Timer1 • Internal or external clock select module. • Interrupt-on-overflow from FFFFh to 0000h Note: Timer1 is disabled on POR. • Reset from CCP module special event trigger REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 113
- 116. PIC18FXX8 12.1 Timer1 Operation When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 Timer1 can operate in one of these modes: increments on every rising edge of the external clock • As a timer input or the Timer1 oscillator, if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is • As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored. bit, TMR1CS (T1CON register). Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section 15.1 “CCP1 Module”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF CCP Special Event Trigger Overflow Synchronized Interrupt TMR1 0 Flag bit CLR Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T1CKI/T1OSO 1 T1OSCEN Synchronize Prescaler T1OSI Enable 1, 2, 4, 8 det FOSC/4 Oscillator(1) Internal 0 Clock 2 Sleep Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L Read TMR1L Special Event Trigger Synchronized TMR1IF 8 TMR1 0 Overflow Clock Input Interrupt Timer 1 TMR1L High Byte Flag bit 1 TMR1ON On/Off T1SYNC T1OSC T1CKI/T1OSO 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR1CS Sleep Input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. DS41159D-page 114 2004 Microchip Technology Inc.
- 117. PIC18FXX8 12.2 Timer1 Oscillator 12.4 Resetting Timer1 Using a CCP A crystal oscillator circuit is built in between pins T1OSI Trigger Output (input) and T1OSO (amplifier output). It is enabled by If the CCP module is configured in Compare mode setting control bit T1OSCEN (T1CON register). The to generate a “special event trigger” oscillator is a low-power oscillator rated up to 50 kHz. It (CCP1M3:CCP1M0 = 1011), this signal will reset will continue to run during Sleep. It is primarily intended Timer1 and start an A/D conversion (if the A/D module for a 32 kHz crystal. Table 12-1 shows the capacitor is enabled). selection for the Timer1 oscillator. Note: The special event triggers from the CCP1 The user must provide a software time delay to ensure module will not set interrupt flag bit, proper start-up of the Timer1 oscillator. TMR1IF (PIR registers). TABLE 12-1: CAPACITOR SELECTION FOR Timer1 must be configured for either Timer or Synchro- THE ALTERNATE nized Counter mode to take advantage of this feature. OSCILLATOR If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. Osc Type Freq C1 C2 In the event that a write to Timer1 coincides with a special LP 32 kHz TBD(1) TBD(1) event trigger from CCP1, the write will take precedence. Crystal to be Tested: In this mode of operation, the CCPR1H:CCPR1L register 32.768 kHz Epson C-001R32.768K-A ±20 PPM pair effectively becomes the period register for Timer1. Note 1: Microchip suggests 33 pF as a starting 12.5 Timer1 16-Bit Read/Write Mode point in validating the oscillator circuit. Timer1 can be configured for 16-bit reads and writes 2: Higher capacitance increases the stability (see Figure 12-2). When the RD16 control bit (T1CON of the oscillator, but also increases the register) is set, the address for TMR1H is mapped to a start-up time. buffer register for the high byte of Timer1. A read from 3: Since each resonator/crystal has its own TMR1L will load the contents of the high byte of Timer1 characteristics, the user should consult into the Timer1 High Byte Buffer register. This provides the resonator/crystal manufacturer for the user with the ability to accurately read all 16 bits of appropriate values of external components. Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid 4: Capacitor values are for design guidance due to a rollover between reads. only. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is 12.3 Timer1 Interrupt updated with the contents of TMR1H when a write The TMR1 register pair (TMR1H:TMR1L) increments occurs to TMR1L. This allows a user to write all 16 bits from 0000h to FFFFh and rolls over to 0000h. The TMR1 to both the high and low bytes of Timer1 at once. Interrupt, if enabled, is generated on overflow which is The high byte of Timer1 is not directly readable or latched in interrupt flag bit, TMR1IF (PIR registers). This writable in this mode. All reads and writes must take interrupt can be enabled/disabled by setting/clearing place through the Timer1 High Byte Buffer register. TMR1 Interrupt Enable bit, TMR1IE (PIE registers). Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 2004 Microchip Technology Inc. DS41159D-page 115
- 118. PIC18FXX8 TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. DS41159D-page 116 2004 Microchip Technology Inc.
- 119. PIC18FXX8 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is • 8-bit timer (TMR2 register) readable and writable and is cleared on any device • 8-bit period register (PR2) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits • Software programmable prescaler (1:1, 1:4, 1:16) T2CKPS1:T2CKPS0 (T2CON register). The match • Software programmable postscaler (1:1 to 1:16) output of TMR2 goes through a 4-bit postscaler (which • Interrupt on TMR2 match of PR2 gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, PIR • SSP module optional use of TMR2 output to registers). generate clock shift The prescaler and postscaler counters are cleared Register 13-1 shows the Timer2 Control register. when any of the following occurs: Timer2 can be shut-off by clearing control bit TMR2ON (T2CON register) to minimize power consumption. • A write to the TMR2 register Figure 13-1 is a simplified block diagram of the Timer2 • A write to the T2CON register module. The prescaler and postscaler selection of • Any device Reset (Power-on Reset, MCLR Reset, Timer2 are controlled by this register. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. Note: Timer2 is disabled on POR. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 117
- 120. PIC18FXX8 13.2 Timer2 Interrupt 13.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. The output of TMR2 (before the postscaler) is a clock Timer2 increments from 00h until it matches PR2 and input to the Synchronous Serial Port module which then resets to 00h on the next increment cycle. PR2 is optionally uses it to generate the shift clock. a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output(1) Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Postscaler Comparator EQ 1:1 to 1:16 T2CKPS1:T2CKPS0 PR2 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. DS41159D-page 118 2004 Microchip Technology Inc.
- 121. PIC18FXX8 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following Register 14-1 shows the Timer3 Control register. This features: register controls the operating mode of the Timer3 • 16-bit timer/counter module and sets the CCP1 and ECCP1 clock source. (two 8-bit registers: TMR3H and TMR3L) Register 12-1 shows the Timer1 Control register. This • Readable and writable (both registers) register controls the operating mode of the Timer1 • Internal or external clock select module, as well as contains the Timer1 Oscillator • Interrupt-on-overflow from FFFFh to 0000h Enable bit (T1OSCEN) which can be a clock source for • Reset from CCP1/ECCP1 module trigger Timer3. Note: Timer3 is disabled on POR. REGISTER 14-1: T3CON:TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits 1x = Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules 01 = Timer3 is the clock source for compare/capture of ECCP1, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 119
- 122. PIC18FXX8 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or • As a timer the Timer1 oscillator, if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), • As an asynchronous counter the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. The operating mode is determined by the clock select bit, TMR3CS (T3CON register). Timer3 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section 15.1 “CCP1 Module”). FIGURE 14-1: TIMER3 BLOCK DIAGRAM CCP Special Trigger TMR3IF Overflow T3CCPx Synchronized Interrupt 0 Clock Input Flag bit CLR TMR3H TMR3L 1 TMR3ON On/Off T3SYNC T1OSC T1OSO/ 1 T1CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR3CS Sleep Input T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L CCP Special Trigger 8 T3CCPx Synchronized TMR3IF Overflow TMR3 0 Interrupt Flag CLR Clock Input bit TMR3H TMR3L 1 To Timer1 Clock Input TMR3ON On/Off T3SYNC T1OSC T1OSO/ T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 Sleep Input T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS41159D-page 120 2004 Microchip Technology Inc.
- 123. PIC18FXX8 14.2 Timer1 Oscillator 14.4 Resetting Timer3 Using a CCP The Timer1 oscillator may be used as the clock source Trigger Output for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in Compare mode the T1OSCEN bit (T1CON register). The oscillator is a to generate a “special event trigger” low-power oscillator rated up to 50 kHz. Refer to (CCP1M3:CCP1M0 = 1011), this signal will reset Section 12.0 “Timer1 Module” for Timer1 oscillator Timer3. details. Note: The special event triggers from the CCP module will not set interrupt flag bit 14.3 Timer3 Interrupt TMR3IF (PIR registers). The TMR3 register pair (TMR3H:TMR3L) increments Timer3 must be configured for either Timer or Synchro- from 0000h to 0FFFFh and rolls over to 0000h. The nized Counter mode to take advantage of this feature. If TMR3 interrupt, if enabled, is generated on overflow Timer3 is running in Asynchronous Counter mode, this which is latched in interrupt flag bit TMR3IF (PIR regis- Reset operation may not work. In the event that a write ters). This interrupt can be enabled/disabled by setting/ to Timer3 coincides with a special event trigger from clearing TMR3 Interrupt Enable bit, TMR3IE (PIE CCP1, the write will take precedence. In this mode of registers). operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer3. Refer to Section 15.0 “Capture/Compare/PWM (CCP) Modules” for CCP details. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. DS41159D-page 121
- 124. PIC18FXX8 NOTES: DS41159D-page 122 2004 Microchip Technology Inc.
- 125. PIC18FXX8 15.0 CAPTURE/COMPARE/PWM module has a Capture special event trigger that can be used as a message received time-stamp for the CAN (CCP) MODULES module (refer to Section 19.0 “CAN Module” for CAN The CCP (Capture/Compare/PWM) module contains a operation) which the ECCP module does not. The 16-bit register that can operate as a 16-bit Capture ECCP module, on the other hand, has Enhanced PWM register, as a 16-bit Compare register or as a PWM functionality and auto-shutdown capability. Aside from Duty Cycle register. these, the operation of the module described in this section is the same as the ECCP. The operation of the CCP module is identical to that of the ECCP module (discussed in detail in The control register for the CCP module is shown in Section 16.0 “Enhanced Capture/Compare/PWM Register 15-1. Table 15-2 (following page) details the (ECCP) Module”) with two exceptions. The CCP interactions of the CCP and ECCP modules. REGISTER 15-1: CCP1CON: CCP1 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Capture mode, CAN message received (CCP1 only) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high (CCPIF bit is set) 1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low (CCPIF bit is set) 1010 = Compare mode, CCP pin is unaffected (CCPIF bit is set) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP resets TMR1 or TMR3 and starts an A/D conversion if the A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 123
- 126. PIC18FXX8 15.1 CCP1 Module An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the Capture/Compare/PWM Register1 (CCPR1) is com- interrupt request flag bit, CCP1IF (PIR registers), is set. prised of two 8-bit registers: CCPR1L (low byte) and It must be cleared in software. If another capture CCPR1H (high byte). The CCP1CON register controls occurs before the value in register CCPR1 is read, the the operation of CCP1. All are readable and writable. old captured value will be lost. Table 15-1 shows the timer resources of the CCP module modes. 15.2.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be TABLE 15-1: CCP1 MODE – TIMER configured as an input by setting the TRISC<2> bit. RESOURCE Note: If the RC2/CCP1 is configured as an out- CCP1 Mode Timer Resource put, a write to the port can cause a capture condition. Capture Timer1 or Timer3 Compare Timer1 or Timer3 15.2.2 TIMER1/TIMER3 MODE SELECTION PWM Timer2 The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- 15.2 Capture Mode chronized Counter mode. In Asynchronous Counter In Capture mode, CCPR1H:CCPR1L captures the 16- mode, the capture operation may not work. The timer bit value of the TMR1 or TMR3 register when an event used with each CCP module is selected in the T3CON occurs on pin RC2/CCP1. An event is defined as: register. • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge TABLE 15-2: INTERACTION OF CCP1 AND ECCP1 MODULES CCP1 ECCP1 Interaction Mode Mode Capture Capture TMR1 or TMR3 time base. Time base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger which clears either TMR1 or TMR3, depending upon which time base is used. Compare Compare The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3, depending upon which time base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None. DS41159D-page 124 2004 Microchip Technology Inc.
- 127. PIC18FXX8 15.2.3 SOFTWARE INTERRUPT 15.2.5 CAN MESSAGE TIME-STAMP When the Capture mode is changed, a false capture The CAN capture event occurs when a message is interrupt may be generated. The user should keep bit received in either of the receive buffers. The CAN CCP1IE (PIE registers) clear to avoid false interrupts module provides a rising edge to the CCP1 module to and should clear the flag bit CCP1IF, following any cause a capture event. This feature is provided to such change in operating mode. time-stamp the received CAN messages. This feature is enabled by setting the CANCAP bit of 15.2.4 CCP1 PRESCALER the CAN I/O control register (CIOCON<4>). The There are four prescaler settings specified by bits message receive signal from the CAN module then CCP1M3:CCP1M0. Whenever the CCP1 module is takes the place of the events on RC2/CCP1. turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared. This means that any EXAMPLE 15-1: CHANGING BETWEEN Reset will clear the prescaler counter. CAPTURE PRESCALERS Switching from one capture prescaler to another may CLRF CCP1CON, F ; Turn CCP module off generate an interrupt. Also, the prescaler counter will MOVLW NEW_CAPT_PS ; Load WREG with the not be cleared; therefore, the first capture may be from ; new prescaler mode a non-zero prescaler. Example 15-1 shows the recom- ; value and CCP ON mended method for switching between capture MOVWF CCP1CON ; Load CCP1CON with prescalers. This example also clears the prescaler ; this value counter and will not generate the “false” interrupt. FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1<2>) T3CCP1 TMR3H TMR3L T3ECCP1 TMR3 Prescaler Enable ÷ 1, 4, 16 CCP1 pin CCPR1H CCPR1L and TMR1 Enable Edge Detect T3ECCP1 T3CCP1 TMR1H TMR1L CCP1CON<3:0> Qs Note: I/O pins have diode protection to VDD and VSS. 2004 Microchip Technology Inc. DS41159D-page 125
- 128. PIC18FXX8 15.3 Compare Mode 15.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 and ECCPR1 Timer1 and/or Timer3 must be running in Timer mode, register value is constantly compared against either the or Synchronized Counter mode, if the CCP module is TMR1 register pair value or the TMR3 register pair using the compare feature. In Asynchronous Counter value. When a match occurs, the CCP1 pin can have mode, the compare operation may not work. one of the following actions: 15.3.3 SOFTWARE INTERRUPT MODE • Driven high When generate software interrupt is chosen, the CCP1 • Driven low pin is not affected. Only a CCP interrupt is generated (if • Toggle output (high-to-low or low-to-high) enabled). • Remains unchanged The action on the pin is based on the value of control 15.3.4 SPECIAL EVENT TRIGGER bits CCP1M3:CCP1M0. At the same time, interrupt flag In this mode, an internal hardware trigger is generated, bit CCP1IF is set. which may be used to initiate an action. The special event trigger output of CCP1 resets either 15.3.1 CCP1 PIN CONFIGURATION the TMR1 or TMR3 register pair. Additionally, the The user must configure the CCP1 pin as an output by ECCP1 special event trigger will start an A/D clearing the appropriate TRISC bit. conversion if the A/D module is enabled. Note: Clearing the CCP1CON register will force Note: The special event trigger from the ECCP1 the CCP1 compare output latch to the module will not set the Timer1 or Timer3 default low level. This is not the data latch. interrupt flag bits. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit) Set bit GO/DONE which starts an A/D conversion (ECCP1 only) TMR1H TMR1L TMR3H TMR3L Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) T3CCP1 T3ECCP1 0 1 Q S Output Comparator CCP1 Logic Match R CCPR1H CCPR1L Output Enable CCP1CON<3:0> Mode Select Note 1: I/O pins have diode protection to VDD and VSS. DS41159D-page 126 2004 Microchip Technology Inc.
- 129. PIC18FXX8 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISD PORTD Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 127
- 130. PIC18FXX8 15.4 PWM Mode 15.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTC data latch, following formula. the TRISC<2> bit must be cleared to make the CCP1 pin an output. EQUATION 15-1: Note: Clearing the CCP1CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the CCP1 PWM output latch to the default (TMR2 Prescale Value) low level. This is not the PORTC I/O data latch. PWM frequency is defined as 1/[PWM period]. Figure 15-3 shows a simplified block diagram of the When TMR2 is equal to PR2, the following three events CCP module in PWM mode. occur on the next increment cycle: For a step-by-step procedure on how to set up the CCP • TMR2 is cleared module for PWM operation, see Section 15.4.3 • The CCP1 pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into FIGURE 15-3: SIMPLIFIED PWM BLOCK CCPR1H DIAGRAM Note: The Timer2 postscaler (see Section 13.0 Duty Cycle Registers CCP1CON<5:4> “Timer2 Module”) is not used in the determination of the PWM frequency. The CCPR1L (Master) postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCPR1H (Slave) 15.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the Comparator R Q CCPR1L register and to the CCP1CON<5:4> bits. Up RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains TMR2 (Note 1) the eight MSbs and the CCP1CON<5:4> contains the S two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is Comparator TRISC<2> used to calculate the PWM duty cycle in time. Clear Timer, set CCP1 pin and latch D.C. PR2 EQUATION 15-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, TOSC • (TMR2 Prescale Value) or 2 bits of the prescaler, to create 10-bit time base. A PWM output (Figure 15-4) has a time base (period) CCPR1L and CCP1CON<5:4> can be written to at any and a time that the output stays high (duty cycle). The time, but the duty cycle value is not latched into frequency of the PWM is the inverse of the period CCPR1H until after a match between PR2 and TMR2 (1/period). occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. FIGURE 15-4: PWM OUTPUT The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This Period double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of Duty Cycle the TMR2 prescaler, the CCP1 pin is cleared. TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS41159D-page 128 2004 Microchip Technology Inc.
- 131. PIC18FXX8 The maximum PWM resolution (bits) for a given PWM 15.4.3 SETUP FOR PWM OPERATION frequency is given by the following equation. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 15-3: 1. Set the PWM period by writing to the PR2 log --------------- F OSC register. F PWM PWM Resolution (max) = -----------------------------bits 2. Set the PWM duty cycle by writing to the log ( 2 ) CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. Note: If the PWM duty cycle value is longer than 4. Set the TMR2 prescale value and enable Timer2 the PWM period, the CCP1 pin will not be by writing to T2CON. cleared. 5. Configure the CCP1 module for PWM operation. TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0FFh 0FFh 0FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISD PORTD Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 129
- 132. PIC18FXX8 NOTES: DS41159D-page 130 2004 Microchip Technology Inc.
- 133. PIC18FXX8 16.0 ENHANCED CAPTURE/ The operation of the ECCP module differs from the CCP (discussed in detail in Section 15.0 “Capture/ COMPARE/PWM (ECCP) Compare/PWM (CCP) Modules”) with the addition of MODULE an Enhanced PWM module which allows for up to 4 output channels and user selectable polarity. These Note: The ECCP (Enhanced Capture/Compare/ features are discussed in detail in Section 16.5 PWM) module is only available on “Enhanced PWM Mode”. The module can also be PIC18F448 and PIC18F458 devices. programmed for automatic shutdown in response to This module contains a 16-bit register which can oper- various analog or digital events. ate as a 16-bit Capture register, a 16-bit Compare The control register for ECCP1 is shown in register or a PWM Master/Slave Duty Cycle register. Register 16-1. REGISTER 16-1: ECCP1CON: ECCP1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 bit 7 bit 0 bit 7-6 EPWM1M<1:0>: PWM Output Configuration bits If ECCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If ECCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 EDC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in ECCPR1L. bit 3-0 ECCP1M<3:0>: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, ECCP1 pin is unaffected (ECCP1IF bit is set) 1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1or TMR3 and starts an A/D conversion if the A/D module is enabled) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 131
- 134. PIC18FXX8 16.1 ECCP1 Module In PWM mode, the ECCP module can have up to four available outputs, depending on which operating mode Enhanced Capture/Compare/PWM Register 1 (ECCPR1) is selected. These outputs are multiplexed with PORTD is comprised of two 8-bit registers: ECCPR1L (low and the Parallel Slave Port. Both the operating mode byte) and ECCPR1H (high byte). The ECCP1CON and the output pin assignments are configured by setting register controls the operation of ECCP1; the additional PWM output configuration bits, EPWM1M1:EPWM1M0 registers, ECCPAS and ECCP1DEL, control Enhanced (ECCP1CON<7:6>). The specific pin assignments for PWM specific features. All registers are readable and the various output modes are shown in Table 16-3. writable. Table 16-1 shows the timer resources for the ECCP TABLE 16-1: ECCP1 MODE – TIMER module modes. Table 16-2 describes the interactions RESOURCE of the ECCP module with the standard CCP module. ECCP1 Mode Timer Resource Capture Timer1 or Timer3 Compare Timer1 or Timer3 PWM Timer2 TABLE 16-2: INTERACTION OF CCP1 AND ECCP1 MODULES ECCP1 Mode CCP1 Mode Interaction Capture Capture TMR1 or TMR3 time base. Time base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger which clears either TMR1 or TMR3 depending upon which time base is used. Compare Compare The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3 depending upon which time base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None PWM Compare None TABLE 16-3: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES ECCP1CON ECCP Mode(1) RD4 RD5 RD6 RD7 Configuration Conventional CCP Compatible 00xx11xx ECCP1 RD<5>, RD<6>, RD<7>, PSP<5> PSP<6> PSP<7> Dual Output PWM(2) 10xx11xx P1A P1B RD<6>, RD<7>, PSP<6> PSP<7> Quad Output PWM(2) x1xx11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output. 2: In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D. DS41159D-page 132 2004 Microchip Technology Inc.
- 135. PIC18FXX8 16.2 Capture Mode 16.3 Compare Mode The Capture mode of the ECCP module is virtually The Compare mode of the ECCP module is virtually identical in operation to that of the standard CCP mod- identical in operation to that of the standard CCP ule as discussed in Section 15.1 “CCP1 Module”. module as discussed in Section 15.2 “Capture The differences are in the registers and port pins Mode”. The differences are in the registers and port involved: pins as described in Section 16.2 “Capture Mode”. • The 16-bit Capture register is ECCPR1 All other details are exactly the same. (ECCPR1H and ECCPR1L); 16.3.1 SPECIAL EVENT TRIGGER • The capture event is selected by control bits ECCP1M3:ECCP1M0 (ECCP1CON<3:0>); Except as noted below, the special event trigger output of ECCP1 functions identically to that of the standard • The interrupt bits are ECCP1IE (PIE2<0>) and CCP module. It may be used to start an A/D conversion ECCP1IF (PIR2<0>); and if the A/D module is enabled. • The capture input pin is RD4 and its corresponding direction control bit is TRISD<4>. Note: The special event trigger from the ECCP1 module will not set the Timer1 or Timer3 Other operational details, including timer selection, interrupt flag bits. output pin configuration and software interrupts, are exactly the same as the standard CCP module. 16.2.1 CAN MESSAGE TIME-STAMP The special capture event for the reception of CAN mes- sages (Section 15.2.5 “CAN Message Time-Stamp”) is not available with the ECCP module. TABLE 16-4: REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 ECCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu ECCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module and Timer1. 2004 Microchip Technology Inc. DS41159D-page 133
- 136. PIC18FXX8 16.4 Standard PWM Mode Figure 16-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and When configured in Single Output mode, the ECCP are loaded at the beginning of a new PWM cycle (the module functions identically to the standard CCP period boundary when the assigned timer resets) in module in PWM mode as described in Section 15.4 order to prevent glitches on any of the outputs. The “PWM Mode”. The differences in registers and ports exception is the PWM Delay register, ECCP1DEL, are as described in Section 16.2 “Capture Mode”. In which is loaded at either the duty cycle boundary or the addition, the two Least Significant bits of the 10-bit boundary period (whichever comes first). Because of PWM duty cycle value are represented by the buffering, the module waits until the assigned timer ECCP1CON<5:4>. resets instead of starting immediately. This means that Note: When setting up single output PWM Enhanced PWM waveforms do not exactly match the operations, users are free to use either of standard PWM waveforms, but are instead offset by the processes described in Section 15.4.3 one full instruction cycle (4 TOSC). “Setup for PWM Operation” or As before, the user must manually configure the Section 16.5.8 “Setup for PWM Opera- appropriate TRISD bits for output. tion”. The latter is more generic, but will work for either single or multi-output PWM. 16.5.1 PWM OUTPUT CONFIGURATIONS The EPWM1M<1:0> bits in the ECCP1CON register 16.5 Enhanced PWM Mode allow one of four configurations: The Enhanced PWM mode provides additional PWM • Single Output output options for a broader range of control applica- • Half-Bridge Output tions. The module is an upwardly compatible version of • Full-Bridge Output, Forward mode the standard CCP module and is modified to provide up • Full-Bridge Output, Reverse mode to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either The Single Output mode is the standard PWM mode active-high or active-low). The module’s output mode discussed in Section 15.4 “PWM Mode”. The Half- and polarity are configured by setting the Bridge and Full-Bridge Output modes are covered in EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits detail in the sections that follow. of the ECCP1CON register (ECCP1CON<7:6> and The general relationship of the outputs in all ECCP1CON<3:0>, respectively). configurations is summarized in Figure 16-2. FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE ECCP1CON<5:4> EPWM1M1<1:0> ECCP1M<3:0> Duty Cycle Registers 2 4 ECCPR1L ECCP1/P1A RD4/PSP4/ECCP1/P1A TRISD<4> ECCPR1H (Slave) P1B RD5/PSP5/P1B Output TRISD<5> Comparator R Q Controller RD6/PSP6/P1C P1C TMR2 (Note 1) S TRISD<6> P1D RD7/PSP7/P1D Comparator Clear Timer, TRISD<7> set ECCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. DS41159D-page 134 2004 Microchip Technology Inc.
- 137. PIC18FXX8 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS 0 PR2 + 1 Duty ECCP1CON SIGNAL Cycle <7:6> Period P1A Modulated, Active-High 00 P1A Modulated, Active-Low P1A Modulated, Active-High P1A Modulated, Active-Low 10 Delay Delay P1B Modulated, Active-High P1B Modulated, Active-Low P1A Active, Active-High P1A Active, Active-Low P1B Inactive, Active-High P1B Inactive, Active-Low 01 P1C Inactive, Active-High P1C Inactive, Active-Low P1D Modulated, Active-High P1D Modulated, Active-Low P1A Inactive, Active-High P1A Inactive, Active-Low P1B Modulated, Active-High P1B Modulated, Active-Low 11 P1C Active, Active-High P1C Active, Active-Low P1D Inactive, Active-High P1D Inactive, Active-Low Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * ECCP1DEL 2004 Microchip Technology Inc. DS41159D-page 135
- 138. PIC18FXX8 16.5.2 HALF-BRIDGE MODE FIGURE 16-3: HALF-BRIDGE PWM In the Half-Bridge Output mode, two pins are used as OUTPUT outputs to drive push-pull loads. The RD4/PSP4/ Period Period ECCP1/P1A pin has the PWM output signal, while the RD5/PSP5/P1B pin has the complementary PWM Duty Cycle output signal (Figure 16-3). This mode can be used for P1A(2) half-bridge applications, as shown in Figure 16-4, or for td full-bridge applications where four power switches are td being modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead- band delay can be used to prevent shoot-through (1) (1) (1) current in bridge power devices. The value of register ECCP1DEL dictates the number of clock cycles before td = Dead-Band Delay the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section 16.5.4 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as asserted high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTD<4> and PORTD<5> data latches, the TRISD<4> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-4: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) V+ PIC18F448/458 FET Driver + P1A V - + - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F448/458 FET FET Driver Driver P1A + - Load FET FET Driver Driver P1B V- DS41159D-page 136 2004 Microchip Technology Inc.
- 139. PIC18FXX8 16.5.3 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4:7> data latches. The TRISD<4:7> bits In Full-Bridge Output mode, four pins are used as out- must be cleared to make the P1A, P1B, P1C and P1D puts; however, only two outputs are active at a time. In pins output. the Forward mode, pin RD4/PSP4/ECCP1/P1A is con- tinuously active and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continu- ously active and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-5. FIGURE 16-5: FULL-BRIDGE PWM OUTPUT FORWARD MODE Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) REVERSE MODE Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as asserted high. 2004 Microchip Technology Inc. DS41159D-page 137
- 140. PIC18FXX8 FIGURE 16-6: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F448/458 FET QD QB FET Driver Driver P1D + - Load P1C FET FET Driver Driver P1B QC QA V- P1A 16.5.3.1 Direction Change in Full-Bridge Figure 16-8 shows an example where the PWM Mode direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D In the Full-Bridge Output mode, the EPWM1M1 bit in become inactive, while output P1C becomes active. In the ECCP1CON register allows the user to control the this example, since the turn-off time of the power forward/reverse direction. When the application firm- devices is longer than the turn-on time, a shoot-through ware changes this direction control bit, the ECCP1 current flows through power devices QB and QD (see module will assume the new direction on the next PWM Figure 16-6) for the duration of ‘t’. The same phenom- cycle. The current PWM cycle still continues, however, enon will occur to power devices QA and QC for PWM the non-modulated outputs, P1A and P1C signals, will direction change from reverse to forward. transition to the new direction TOSC, 4 TOSC or 16 TOSC earlier (for T2CKRS<1:0> = 00, 01 or 1x, respectively) If changing PWM direction at high duty cycle is required before the end of the period. During this transition for an application, one of the following requirements cycle, the modulated outputs, P1B and P1D, will go to must be met: the inactive state (Figure 16-7). 1. Avoid changing PWM output direction at or near Note that in the Full-Bridge Output mode, the ECCP 100% duty cycle. module does not provide any dead-band delay. In 2. Use switch drivers that compensate the slow general, since only one output is modulated at all times, turn off of the power devices. The total turn-off dead-band delay is not required. However, there is a time (toff) of the power device and the driver situation where a dead-band delay might be required. must be less than the turn-on time (ton). This situation occurs when all of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than turn-on time. DS41159D-page 138 2004 Microchip Technology Inc.
- 141. PIC18FXX8 FIGURE 16-7: PWM DIRECTION CHANGE Period(1) Period SIGNAL DC P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) (2) Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM cycle. 2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler value earlier when changing direction. The modulated P1B and P1D signals are inactive at this time. FIGURE 16-8: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period Reverse Period P1A(1) P1B(1) (PWM) P1C(1) P1D(1) (PWM) ton(2) External Switch C(1) toff(3) External Switch D(1) Potential t = toff – ton(2,3) Shoot-Through Current(1) t1 Note 1: All signals are shown as active-high. 2: ton is the turn-on delay of power switch and driver. 3: toff is the turn-off delay of power switch and driver. 2004 Microchip Technology Inc. DS41159D-page 139
- 142. PIC18FXX8 16.5.4 PROGRAMMABLE DEAD-BAND devices in the off state until the microcontroller drives DELAY the I/O pins with the proper signal levels, or activates the PWM output(s). In half-bridge or full-bridge applications, where all power switches are modulated at the PWM frequency 16.5.6 START-UP CONSIDERATIONS at all times, the power switches normally require longer time to turn off than to turn on. If both the upper and Prior to enabling the PWM outputs, the P1A, P1B, P1C lower power switches are switched at the same time and P1D latches may not be in the proper states. (one turned on and the other turned off), both switches Enabling the TRISD bits for output at the same time will be on for a short period of time until one switch with the ECCP1 module may cause damage to the completely turns off. During this time, a very high power switch devices. The ECCP1 module must be current (shoot-through current) flows through both enabled in the proper output mode with the TRISD bits power switches, shorting the bridge supply. To avoid enabled as inputs. Once the ECCP1 completes a full this potentially destructive shoot-through current from PWM cycle, the P1A, P1B, P1C and P1D output flowing during switching, turning on the power switch is latches are properly initialized. At this time, the TRISD normally delayed to allow the other switch to bits can be enabled for outputs to start driving the completely turn off. power switch devices. The completion of a full PWM cycle is indicated by the TMR2IF bit going from a ‘0’ to In the Half-Bridge Output mode, a digitally programmable a ‘1’. dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The 16.5.7 OUTPUT POLARITY delay occurs at the signal transition from the non-active CONFIGURATION state to the active state. See Figure 16-3 for illustration. The ECCP1DEL register (Register 16-2) sets the amount The ECCP1M<1:0> bits in the ECCP1CON register of delay. allow user to choose the logic conventions (asserted high/low) for each of the outputs. 16.5.5 SYSTEM IMPLEMENTATION The PWM output polarities must be selected before the When the ECCP module is used in the PWM mode, the PWM outputs are enabled. Charging the polarity application hardware must use the proper external pull- configuration while the PWM outputs are active is not up and/or pull-down resistors on the PWM output pins. recommended since it may result in unpredictable When the microcontroller powers up, all of the I/O pins operation. are in the high-impedance state. The external pull-up and pull-down resistors must keep the power switch REGISTER 16-2: ECCP1DEL: PWM DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 bit 7 bit 0 bit 7-0 EPDC<7:0>: PWM Delay Count for Half-Bridge Output Mode bits Number of FOSC/4 (TOSC * 4) cycles between the P1A transition and the P1B transition. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 140 2004 Microchip Technology Inc.
- 143. PIC18FXX8 16.5.8 SETUP FOR PWM OPERATION 2. Configure and start TMR2: The following steps should be taken when configuring a) Clear the TMR2 interrupt flag bit by clearing the ECCP1 module for PWM operation: the TMR2IF bit in the PIR1 register. b) Set the TMR2 prescale value by loading the 1. Configure the PWM module: T2CKPS bits (T2CON<1:0>). a) Disable the ECCP1/P1A, P1B, P1C and/or c) Enable Timer2 by setting the TMR2ON bit P1D outputs by setting the respective TRISD (T2CON<2>) register. bits. 3. Enable PWM outputs after a new cycle has b) Set the PWM period by loading the PR2 started: register. a) Wait until TMR2 overflows (TMR2IF bit c) Set the PWM duty cycle by loading the becomes a ‘1’). The new PWM cycle begins ECCPR1L register and ECCP1CON<5:4> here. bits. b) Enable the ECCP1/P1A, P1B, P1C and/or d) Configure the ECCP1 module for the P1D pin outputs by clearing the respective desired PWM operation by loading the TRISD bits. ECCP1CON register with the appropriate value. With the ECCP1M<3:0> bits, select the active-high/low levels for each PWM output. With the EPWM1M<1:0> bits, select one of the available output modes. e) For Half-Bridge Output mode, set the dead- band delay by loading the ECCP1DEL register with the appropriate value. TABLE 16-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u RCON IPEN — — RI TO PD POR BOR 0--1 110q 0--0 011q IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP -1-1 1111 -1-1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF ECCP1IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE ECCP1IE -0-0 0000 -0-0 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TRISD PORTD Data Direction Register 1111 1111 1111 1111 ECCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu ECCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000 ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 ECCP1DEL EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module. 2004 Microchip Technology Inc. DS41159D-page 141
- 144. PIC18FXX8 16.6 Enhanced CCP Auto-Shutdown The internal shutdown signal is gated with the outputs and will immediately and asynchronously disable the When the ECCP is programmed for any of the PWM outputs. If the internal shutdown is still in effect at the modes, the output pins associated with its function may time a new cycle begins, that entire cycle is be configured for auto-shutdown. suppressed, thus eliminating narrow, glitchy pulses. Auto-shutdown allows the internal output of either of The ECCPASE bit is set by hardware upon a compara- the two comparator modules, or the external tor event and can only be cleared in software. The interrupt 0, to asynchronously disable the ECCP output ECCP outputs can be re-enabled only by clearing the pins. Thus, an external analog or digital event can ECCPASE bit. discontinue an ECCP sequence. The comparator out- put(s) to be used is selected by setting the proper mode The Auto-Shutdown mode can be manually entered by bits in the ECCPAS register. To use external interrupt writing a ‘1’ to the ECCPASE bit. INT0 as a shutdown event, INT0IE must be set. To use either of the comparator module outputs as a shutdown event, corresponding comparators must be enabled. When a shutdown occurs, the selected output values (PSSACn, PSSBDn) are written to the ECCP port pins. REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs enabled, no shutdown event 1 = A shutdown event has occurred, must be reset in software to re-enable ECCP bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown bits 000 = No auto-shutdown enabled, comparators have no effect on ECCP 001 = Comparator 1 output will cause shutdown 010 = Comparator 2 output will cause shutdown 011 = Either Comparator 1 or 2 can cause shutdown 100 = INT0 101 = INT0 or Comparator 1 output 110 = INT0 or Comparator 2 output 111 = INT0 or Comparator 1 or Comparator 2 output bit 3-2 PSSACn: Pins A and C Shutdown State Control bits 00 = Drive Pins A and C to ‘0’ 01 = Drive Pins A and C to ‘1’ 1x = Pins A and C tri-state bit 1-0 PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ 01 = Drive Pins B and D to ‘1’ 1x = Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 142 2004 Microchip Technology Inc.
- 145. PIC18FXX8 17.0 MASTER SYNCHRONOUS 17.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, 17.1 Master SSP (MSSP) Module typically three pins are used: Overview • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other • Serial Clock (SCK) – RC3/SCK/SCL peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, mode of operation: display drivers, A/D converters, etc. The MSSP module • Slave Select (SS) – RA5/AN4/SS/LVDIN can operate in one of two modes: Figure 17-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 17-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPI™ MODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode SSPBUF reg • Slave mode 17.2 Control Registers RC4/SDI/SDA The MSSP module has three associated registers. SSPSR reg These include a status register (SSPSTAT) and two RC5/SDO bit0 Shift Clock control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. RA5/AN4/ Additional details are provided under the individual SS/LVDIN SS Control sections. Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 RC3/SCK/ SCL 2 ( TMR2 Output 2 ) Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit 2004 Microchip Technology Inc. DS41159D-page 143
- 146. PIC18FXX8 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer (SSPBUF) and the SSPIF interrupt is set. • MSSP Shift Register (SSPSR) – Not directly During transmission, the SSPBUF is not double- accessible buffered. A write to SSPBUF will write to both SSPBUF SSPCON1 and SSPSTAT are the control and status and SSPSR. registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Edge Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 144 2004 Microchip Technology Inc.
- 147. PIC18FXX8 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF even if only transmitting data to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 145
- 148. PIC18FXX8 17.3.2 OPERATION SSPBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL When initializing the SPI, several options need to be (SSPCON1<7>), will be set. User software must clear specified. This is done by programming the appropriate the WCOL bit so that it can be determined if the follow- control bits (SSPCON1<5:0> and SSPSTAT<7:6>). ing write(s) to the SSPBUF register completed These control bits allow the following to be specified: successfully. • Master mode (SCK is the clock output) When the application software is expecting to receive • Slave mode (SCK is the clock input) valid data, the SSPBUF should be read before the next • Clock Polarity (Idle state of SCK) byte of data to transfer is written to the SSPBUF. Buffer • Data Input Sample Phase (middle or end of data Full bit, BF (SSPSTAT<0>), indicates when SSPBUF output time) has been loaded with the received data (transmission • Clock Edge (output data on rising/falling edge of is complete). When the SSPBUF is read, the BF bit is SCK) cleared. This data may be irrelevant if the SPI is only a • Clock Rate (Master mode only) transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has com- • Slave Select mode (Slave mode only) pleted. The SSPBUF must be read and/or written. If the The MSSP consists of a transmit/receive shift register interrupt method is not going to be used, then software (SSPSR) and a buffer register (SSPBUF). The SSPSR polling can be done to ensure that a write collision does shifts the data in and out of the device, MSb first. The not occur. Example 17-1 shows the loading of the SSPBUF holds the data that was written to the SSPSR SSPBUF (SSPSR) for data transmission. until the received data is ready. Once the 8 bits of data The SSPSR is not directly readable or writable and can have been received, that byte is moved to the SSPBUF only be accessed by addressing the SSPBUF register. register. Then, the Buffer Full detect bit BF Additionally, the MSSP Status register (SSPSTAT) (SSPSTAT<0>) and the interrupt flag bit SSPIF are set. indicates the various status conditions. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS41159D-page 146 2004 Microchip Technology Inc.
- 149. PIC18FXX8 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure 17-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the SSPCON initiates the data transfer by sending the SCK signal. registers and then, set the SSPEN bit. This configures Data is shifted out of both shift registers on their the SDI, SDO, SCK and SS pins as serial port pins. For programmed clock edge and latched on the opposite the pins to behave as the serial port function, some must edge of the clock. Both processors should be have their data direction bits (in the TRIS register) programmed to the same Clock Polarity (CKP), then appropriately programmed as follows: both controllers would send and receive data at the • SDI is automatically controlled by the SPI module same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads • SDO must have TRISC<5> bit cleared to three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit cleared • Master sends data – Slave sends dummy data • SCK (Slave mode) must have TRISC<3> bit set • Master sends data – Slave sends data • SS must have TRISA<5> bit set • Master sends dummy data – Slave sends data Any serial port function that is not desired may be over- ridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 17-2: SPI™ MASTER/SLAVE CONNECTION SPI™ Master SSPM3:SSPM0 = 00xxb SPI™ Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) Shift Register SDI SDO Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 2004 Microchip Technology Inc. DS41159D-page 147
- 150. PIC18FXX8 17.3.5 MASTER MODE The clock polarity is selected by appropriately program- ming the CKP bit (SSPCON1<4>). This then, would The master can initiate the data transfer at any time give waveforms for SPI communication as shown in because it controls the SCK. The master determines Figure 17-3, Figure 17-5 and Figure 17-6, where the when the slave (Processor 2, Figure 17-2) is to MSB is transmitted first. In Master mode, the SPI clock broadcast data by the software protocol. rate (bit rate) is user programmable to be one of the In Master mode, the data is transmitted/received as following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be dis- abled (programmed as an input). The SSPSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY) at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of if a normal received byte (interrupts and status bits 10.00 Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure 17-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 17-3: SPI™ MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock SCK Modes (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit7 Input Sample (SMP = 1) SSPIF Next Q4 cycle SSPSR to after Q2↓ SSPBUF DS41159D-page 148 2004 Microchip Technology Inc.
- 151. PIC18FXX8 17.3.6 SLAVE MODE must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When In Slave mode, the data is transmitted and received as the SS pin goes high, the SDO pin is no longer driven, the external clock pulses appear on SCK. When the even if in the middle of a transmitted byte and becomes last bit is latched, the SSPIF interrupt flag bit is set. a floating output. External pull-up/pull-down resistors While in Slave mode, the external clock is supplied by may be desirable depending on the application. the external clock source on the SCK pin. This external clock must meet the minimum high and low times as Note 1: When the SPI is in Slave mode with SS pin specified in the electrical specifications. control enabled (SSPCON1<3:0> = 0100), the SPI module will reset if the SS pin is set While in Sleep mode, the slave can transmit/receive to VDD. data. When a byte is received, the device will wake-up from Sleep. Before enabling the module in SPI Slave 2: If the SPI is used in Slave mode with CKE mode, the clock line must match the proper Idle state. set, then the SS pin control must be The clock line can be observed by reading the SCK pin. enabled. The Idle state is determined by the CKP bit When the SPI module resets, the bit counter is forced (SSPCON1<4>). to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. 17.3.7 SLAVE SELECT To emulate two-wire communication, the SDO pin can SYNCHRONIZATION be connected to the SDI pin. When the SPI needs to The SS pin allows a Synchronous Slave mode. The operate as a receiver, the SDO pin can be configured SPI must be in Slave mode with SS pin control enabled as an input. This disables transmissions from the SDO. (SSPCON1<3:0> = 04h). The pin must not be driven The SDI can always be left as an input (SDI function) low for the SS pin to function as an input. The data latch since it cannot create a bus conflict. FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2↓ SSPBUF 2004 Microchip Technology Inc. DS41159D-page 149
- 152. PIC18FXX8 FIGURE 17-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2↓ SSPBUF FIGURE 17-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2↓ SSPSR to SSPBUF DS41159D-page 150 2004 Microchip Technology Inc.
- 153. PIC18FXX8 17.3.8 SLEEP OPERATION 17.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the Table 17-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to transmit/ receive data. TABLE 17-1: SPI™ BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Control Bits State Standard SPI Mode operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be Terminology CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device 0, 1 0 0 from Sleep. 1, 0 1 1 1, 1 1 0 17.3.9 EFFECTS OF A RESET There is also an SMP bit which controls when the data A Reset disables the MSSP module and terminates the is sampled. current transfer. TABLE 17-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 (1) IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISA — TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 151
- 154. PIC18FXX8 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I 2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit addressing. • Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly Two pins are used for data transfer: accessible • Serial clock (SCL) – RC3/SCK/SCL • MSSP Address Register (SSPADD) • Serial data (SDA) – RC4/SDI/SDA SSPCON1, SSPCON2 and SSPSTAT are the control The user must configure these pins as inputs or outputs and status registers in I2C mode operation. The through the TRISC<4:3> bits. SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read-only. FIGURE 17-7: MSSP BLOCK DIAGRAM The upper two bits of the SSPSTAT are read/write. (I2C™ MODE) SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes Internal are written to or read from. Data Bus SSPADD register holds the slave device address Read Write when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower RC3/SCK/ SSPBUF reg SCL seven bits of SSPADD act as the Baud Rate Generator reload value. Shift Clock In receive operations, SSPSR and SSPBUF together SSPSR reg create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF RC4/ MSb LSb SDI/ and the SSPIF interrupt is set. SDA During transmission, the SSPBUF is not double- Match Detect Addr Match buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS41159D-page 152 2004 Microchip Technology Inc.
- 155. PIC18FXX8 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write Information bit (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 153
- 156. PIC18FXX8 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 154 2004 Microchip Technology Inc.
- 157. PIC18FXX8 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is enabled for slave transmit only (Legacy mode) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2004 Microchip Technology Inc. DS41159D-page 155
- 158. PIC18FXX8 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON1<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I 2C the 8 bits are shifted into the SSPSR register. All incom- operation. Four mode selection bits (SSPCON1<3:0>) ing bits are sampled with the rising edge of the clock allow one of the following I 2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode, clock = OSC/4 (SSPADD +1) address is compared on the falling edge of the eighth • I 2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I 2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I 2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I 2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit BF is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I 2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated if enabled) on the Selection of any I 2C mode with the SSPEN bit set falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, pro- In 10-bit Address mode, two address bytes need to be vided these pins are programmed to inputs by setting received by the slave. The five Most Significant bits the appropriate TRISC bits. To ensure proper operation (MSbs) of the first address byte specify if this is a 10-bit of the module, pull-up resistors must be provided address. Bit R/W (SSPSTAT<2>) must specify a write so externally to the SCL and SDA pins. the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 17.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs In Slave mode, the SCL and SDA pins must be config- of the address. The sequence of events for 10-bit ured as inputs (TRISC<4:3> set). The MSSP module address is as follows, with steps 7 through 9 for the will override the input state with the output data when slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I 2C Slave mode hardware will always generate an BF and bit UA (SSPSTAT<1>) are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the Start and Stop bits. SCL line). When an address is matched, or the data transfer after 3. Read the SSPBUF register (clears bit BF) and an address match is received, the hardware automati- clear flag bit SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (bits load the SSPBUF register with the received value SSPIF, BF and UA are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit UA. • The Buffer Full bit, BF (SSPSTAT<0>), was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. • The overflow bit, SSPOV (SSPCON1<6>), was 7. Receive Repeated Start condition. set before the transfer was received. 8. Receive first (high) byte of address (bits SSPIF In this case, the SSPSR register value is not loaded and BF are set). into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The 9. Read the SSPBUF register (clears bit BF) and BF bit is cleared by reading the SSPBUF register, while clear flag bit SSPIF. bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101. DS41159D-page 156 2004 Microchip Technology Inc.
- 159. PIC18FXX8 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held When the address byte overflow condition exists, then low regardless of SEN (see Section 17.4.4 “Clock the no Acknowledge (ACK) pulse is given. An overflow Stretching” for more detail). By stretching the clock, condition is defined as either bit BF (SSPSTAT<0>) is the master will be unable to assert another clock pulse set or bit SSPOV (SSPCON1<6>) is set. until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register, An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then, pin RC3/ byte. Flag bit SSPIF (PIR1<3>) must be cleared in SCK/SCL should be enabled by setting bit CKP software. The SSPSTAT register is used to determine (SSPCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure 17-9). transfer. The clock must be released by setting bit The ACK pulse from the master-receiver is latched on CKP (SSPCON1<4>). See Section 17.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA Stretching” for more detail. line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 2004 Microchip Technology Inc. DS41159D-page 157
- 160. FIGURE 17-8: DS41159D-page 158 PIC18FXX8 Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P SSPIF Bus master (PIR1<3>) terminates transfer BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) SSPOV is set because SSPBUF is still full. ACK is not sent. CKP (CKP does not reset to ‘0’ when SEN = 0) I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc.
- 161. FIGURE 17-9: Receiving Address R/W = 1 Transmitting Data Transmitting Data ACK ACK 2004 Microchip Technology Inc. SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S Data in SCL held low P sampled while CPU responds to SSPIF SSPIF (PIR1<3>) BF (SSPSTAT<0>) Cleared in software Cleared in software From SSPIF ISR From SSPIF ISR SSPBUF is written in software SSPBUF is written in software CKP CKP is set in software CKP is set in software I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) PIC18FXX8 DS41159D-page 159
- 162. FIGURE 17-10: DS41159D-page 160 Clock is held low until Clock is held low until update of SSPADD has update of SSPADD has taken place taken place Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte R/W = 0 ACK ACK PIC18FXX8 SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Bus master terminates SSPIF transfer (PIR1<3>) Cleared in software Cleared in software Cleared in software Cleared in software BF (SSPSTAT<0>) SSPBUF is written with Dummy read of SSPBUF contents of SSPSR to clear BF flag SSPOV (SSPCON1<6>) SSPOV is set because SSPBUF is still full. ACK is not sent. UA (SSPSTAT<1>) UA is set indicating that Cleared by hardware Cleared by hardware when the SSPADD needs to be when SSPADD is updated SSPADD is updated with high updated with low byte of address byte of address UA is set indicating that SSPADD needs to be updated CKP (CKP does not reset to ‘0’ when SEN = 0) I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc.
- 163. FIGURE 17-11: Bus master terminates Clock is held low until Clock is held low until transfer update of SSPADD has update of SSPADD has Clock is held low until 2004 Microchip Technology Inc. taken place taken place CKP is set to ‘1’ R/W = 0 Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W = 1 Transmitting Data Byte ACK SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S Sr P SSPIF (PIR1<3>) Cleared in software Cleared in software Cleared in software BF (SSPSTAT<0>) SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF contents of SSPSR to clear BF flag BF flag is clear Write of SSPBUF Completion of to clear BF flag initiates transmit data transmission at the end of the UA (SSPSTAT<1>) third address sequence clears BF flag UA is set indicating that Cleared by hardware when Cleared by hardware when the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high updated byte of address byte of address UA is set indicating that SSPADD needs to be updated CKP (SSPCON1<4>) CKP is set in software CKP is automatically cleared in hardware holding SCL low I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) PIC18FXX8 DS41159D-page 161
- 164. PIC18FXX8 17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-bit Slave Both 7 and 10-bit Slave modes implement automatic Transmit Mode clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the be enabled during receives. Setting SEN will cause ninth clock if the BF bit is clear. This occurs regardless the SCL pin to be held low at the end of each data of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 17.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 17-9). ninth clock at the end of the ACK sequence, if the BF Note 1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is auto- setting the BF bit before the falling edge of matically cleared, forcing the SCL output to be held the ninth clock, the CKP bit will not be low. The CKP being cleared to ‘0’ will assert the SCL cleared and clock stretching will not occur. line low. The CKP bit must be set in the user’s ISR before reception is allowed to continue. By holding the 2: The CKP bit can be set in software SCL line low, the user has time to service the ISR and regardless of the state of the BF bit. read the contents of the SSPBUF before the master 17.4.4.4 Clock Stretching for 10-bit Slave device can initiate another receive sequence. This will prevent buffer overruns from occurring. Transmit Mode In 10-bit Slave Transmit mode, clock stretching is Note 1: If the user reads the contents of the controlled during the first two address sequences by SSPBUF before the falling edge of the the state of the UA bit, just as it is in 10-bit Slave ninth clock, thus clearing the BF bit, the Receive mode. The first two addresses are followed CKP bit will not be cleared and clock by a third address sequence which contains the high- stretching will not occur. order bits of the 10-bit address and the R/W bit set to 2: The CKP bit can be set in software ‘1’. After the third address sequence is performed, the regardless of the state of the BF bit. The UA bit is not set, the module is now configured in user should be careful to clear the BF bit Transmit mode and clock stretching is controlled by in the ISR before the next receive the BF flag as in 7-bit Slave Transmit mode (see sequence in order to prevent an overflow Figure 17-11). condition. 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS41159D-page 162 2004 Microchip Technology Inc.
- 165. PIC18FXX8 17.4.4.5 Clock Synchronization and assert the SCL line until an external I2C master device the CKP bit has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices If a user clears the CKP bit, the SCL output is forced to on the I2C bus have deasserted SCL. This ensures that ‘0’. Setting the CKP bit will not assert the SCL output a write to the CKP bit will not violate the minimum high low until the SCL output is already sampled low. If the time requirement for SCL (see Figure 17-12). user attempts to drive SCL low, the CKP bit will not FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON1 2004 Microchip Technology Inc. DS41159D-page 163
- 166. FIGURE 17-13: DS41159D-page 164 Clock is not held low PIC18FXX8 because buffer full bit is clear prior to falling edge Clock is held low until Clock is not held low of 9th clock CKP is set to ‘1’ because ACK = 1 Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P SSPIF Bus master (PIR1<3>) terminates transfer BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) SSPOV is set because SSPBUF is still full. ACK is not sent. CKP CKP If BF is cleared written prior to the falling to ‘1’ in edge of the 9th clock, software CKP will not be reset BF is set after falling to ‘0’ and no clock edge of the 9th clock, stretching will occur CKP is reset to ‘0’ and clock stretching occurs I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc.
- 167. FIGURE 17-14: Clock is held low until Clock is held low until update of SSPADD has update of SSPADD has Clock is not held low Clock is held low until taken place taken place because ACK = 1 CKP is set to ‘1’ Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte R/W = 0 ACK ACK ACK SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 2004 Microchip Technology Inc. SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P SSPIF Bus master (PIR1<3>) terminates Cleared in software Cleared in software Cleared in software transfer Cleared in software BF (SSPSTAT<0>) SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF contents of SSPSR to clear BF flag to clear BF flag SSPOV (SSPCON1<6>) SSPOV is set because SSPBUF is still full. ACK is not sent. UA (SSPSTAT<1>) UA is set indicating that Cleared by hardware when Cleared by hardware when the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high updated byte of address after falling edge byte of address after falling edge of ninth clock of ninth clock UA is set indicating that SSPADD needs to be updated CKP Note: An update of the SSPADD register before the falling edge of the ninth clock will CKP written to ‘1’ have no effect on UA and in software UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) UA will remain set. PIC18FXX8 DS41159D-page 165
- 168. PIC18FXX8 17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the inter- the master. The exception is the general call address rupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set and the slave will begin receiving data after the set). Following a Start bit detect, 8 bits are shifted into Acknowledge (Figure 17-15). the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt Receiving data ACK R/W = 0 General Call Address ACK D7 SDA D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS41159D-page 166 2004 Microchip Technology Inc.
- 169. PIC18FXX8 17.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop SSPBUF will not be written to and the conditions. The Stop (P) and Start (S) bits are cleared WCOL bit will be set, indicating that a write from a Reset or when the MSSP module is disabled. to the SSPBUF did not occur. Control of the I 2C bus may be taken when the P bit is set or the bus is Idle, with both the S and P bits clear. The following events will cause SSP Interrupt Flag bit, In Firmware Controlled Master mode, user code SSPIF, to be set (SSP interrupt if enabled): conducts all I 2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift Clock Arbitrate/WCOL Detect SDA in Clock SSPSR (hold off clock source) MSb LSb Receive Enable Start bit, Stop bit, Clock Cntl Acknowledge Generate SCL Start bit Detect Stop bit Detect SCL in Write Collision Detect Set/Reset S, P, WCOL (SSPSTAT); Clock Arbitration set SSPIF, BCLIF; Bus Collision State Counter for reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV 2004 Microchip Technology Inc. DS41159D-page 167
- 170. PIC18FXX8 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition, or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7 bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate receive bit. Serial data is received via SDA while SCL outputs the serial 9. The MSSP module shifts in the ACK bit from the clock. Serial data is received 8 bits at a time. After each slave device and writes its value into the byte is received, an Acknowledge bit is transmitted. SSPCON2 register (SSPCON2<6>). Start and Stop conditions indicate the beginning and 10. The MSSP module generates an interrupt at the end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode operation is used to set the SCL clock frequency for 11. The user generates a Stop condition by setting either 100 kHz, 400 kHz or 1 MHz I2C operation. See the Stop Enable bit PEN (SSPCON2<2>). Section 17.4.7 “Baud Rate Generator” for more 12. Interrupt is generated once the Stop condition is details. complete. DS41159D-page 168 2004 Microchip Technology Inc.
- 171. PIC18FXX8 17.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmis- 2 sion of the last data bit is followed by ACK), the internal In I C Master mode, the Baud Rate Generator (BRG) clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table 17-3 demonstrates clock rates based on begin counting. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 17-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2004 Microchip Technology Inc. DS41159D-page 169
- 172. PIC18FXX8 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure 17-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS41159D-page 170 2004 Microchip Technology Inc.
- 173. PIC18FXX8 17.4.8 I2C MASTER MODE START 17.4.8.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a Start sequence To initiate a Start condition, the user sets the Start is in progress, the WCOL is set and the contents of the condition enable bit, SEN (SSPCON2<0>). If the SDA buffer are unchanged (the write doesn’t occur). and SCL pins are sampled high, the Baud Rate Gener- Note: Because queueing of events is not ator is reloaded with the contents of SSPADD<6:0> allowed, writing to the lower 5 bits of and starts its count. If SCL and SDA are both sampled SSPCON2 is disabled until the Start high when the Baud Rate Generator times out (TBRG), condition is complete. the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If, at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs; the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S 2004 Microchip Technology Inc. DS41159D-page 171
- 174. PIC18FXX8 17.4.9 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the user START CONDITION TIMING may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After A Repeated Start condition occurs when the RSEN bit the first eight bits are transmitted and an ACK is (SSPCON2<1>) is programmed high and the I2C logic received, the user may then transmit an additional eight module is in the Idle state. When the RSEN bit is set, bits of address (10-bit mode) or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is sam- mode). pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The 17.4.9.1 WCOL Status Flag SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Genera- If the user writes the SSPBUF when a Repeated Start tor times out, if SDA is sampled high, the SCL pin will sequence is in progress, the WCOL is set and the be deasserted (brought high). When SCL is sampled contents of the buffer are unchanged (the write doesn’t high, the Baud Rate Generator is reloaded with the occur). contents of SSPADD<6:0> and begins counting. SDA Note: Because queueing of events is not and SCL must be sampled high for one TBRG. This allowed, writing of the lower 5 bits of action is then followed by assertion of the SDA pin SSPCON2 is disabled until the Repeated (SDA = 0) for one TBRG while SCL is high. Following Start condition is complete. this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 17-20: REPEATED START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here. At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG Sr = Repeated Start DS41159D-page 172 2004 Microchip Technology Inc.
- 175. PIC18FXX8 17.4.10 I2C MASTER MODE 17.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK = 0) and is set when the slave does not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when set the Buffer Full flag bit BF and allow the Baud Rate it has recognized its address (including a general call) Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is 17.4.11 I2C MASTER MODE RECEPTION asserted (see data hold time specification parameter Master mode reception is enabled by programming the #106). SCL is held low for one Baud Rate Generator Receive Enable bit, RCEN (SSPCON2<3>). rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification Note: The RCEN bit should be set after the ACK parameter #107). When the SCL pin is released high, it sequence is complete or the RCEN bit will is held that way for TBRG. The data on the SDA pin be disregarded. must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/ bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After the BF flag is cleared and the master releases SDA. the falling edge of the eighth clock, the receive enable This allows the slave device being addressed to flag is automatically cleared, the contents of the respond with an ACK bit during the ninth bit time, if an SSPSR are loaded into the SSPBUF, the BF flag bit is address match occurred, or if data was received prop- set, the SSPIF flag bit is set and the Baud Rate Gener- erly. The status of ACK is written into the ACKDT bit ator is suspended from counting, holding SCL low. The on the falling edge of the ninth clock. If the master MSSP is now in Idle state awaiting the next command. receives an Acknowledge, the Acknowledge Status bit, When the buffer is read by the CPU, the BF flag bit is ACKSTAT, is cleared. If not, the bit is set. After the ninth automatically cleared. The user can then send an clock, the SSPIF bit is set and the master clock (Baud Acknowledge bit at the end of reception by setting the Rate Generator) is suspended until the next data byte Acknowledge Sequence Enable bit, ACKEN is loaded into the SSPBUF, leaving SCL low and SDA (SSPCON2<4>). unchanged (Figure 17-21). After the write to the SSPBUF, each bit of address will 17.4.11.1 BF Status Flag be shifted out on the falling edge of SCL until all seven In receive operation, the BF bit is set when an address address bits and the R/W bit are completed. On the or data byte is loaded into SSPBUF from SSPSR. It is falling edge of the eighth clock, the master will deassert cleared when the SSPBUF register is read. the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the 17.4.11.2 SSPOV Status Flag master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when 8 bits was recognized by a slave. The status of the ACK bit is are received into the SSPSR and the BF flag bit is loaded into the ACKSTAT status bit (SSPCON2<6>). already set from a previous reception. Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF bit is set, the BF flag is 17.4.11.3 WCOL Status Flag cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL If the user writes the SSPBUF when a receive is low and allowing SDA to float. already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer 17.4.10.1 BF Status Flag are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2004 Microchip Technology Inc. DS41159D-page 173
- 176. FIGURE 17-21: DS41159D-page 174 Write SSPCON2<0> SEN = 1 ACKSTAT in Start condition begins SSPCON2 = 1 From slave, clear ACKSTAT bit SSPCON2<6> PIC18FXX8 SEN = 0 Transmitting Data or Second Half Transmit Address to Slave R/W = 0 of 10-bit Address ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0 SSPBUF written with 7-bit address and R/W, start transmit SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P SCL held low while CPU responds to SSPIF SSPIF Cleared in software service routine Cleared in software from SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SSPBUF is written in software SEN After Start condition, SEN cleared by hardware PEN R/W I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 2004 Microchip Technology Inc.
- 177. FIGURE 17-22: Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Write to SSPCON2<0> (SEN = 1), begin Start Condition ACK from master Set ACKEN, start Acknowledge sequence Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1 SEN = 0 by programming SSPCON2<3> (RCEN = 1) 2004 Microchip Technology Inc. PEN bit = 1 Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared ACK from Slave next receive automatically written here start XMIT automatically Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus master ACK is not sent terminates transfer 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL S P Data shifted in on falling edge of CLK Set SSPIF at end of receive Set SSPIF interrupt Set SSPIF interrupt at end of Acknow- Set SSPIF interrupt ledge sequence at end of receive at end of Acknowledge SSPIF sequence Set P bit Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>) SDA = 0, SCL = 1 Cleared in while CPU software and SSPIF responds to SSPIF BF (SSPSTAT<0>) Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV SSPOV is set because SSPBUF is still full ACKEN I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) PIC18FXX8 DS41159D-page 175
- 178. PIC18FXX8 17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is erate an Acknowledge, then the ACKDT bit should be sampled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to 0. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is SCL pin is sampled high (clock arbitration), the Baud sampled high while SCL is high, the P bit Rate Generator counts for TBRG. The SCL pin is then (SSPSTAT<4>) is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure 17-24). cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 17-23). 17.4.13.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence 17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con- If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the con- occur). tents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the end Cleared in software of receive software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG Set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS41159D-page 176 2004 Microchip Technology Inc.
- 179. PIC18FXX8 17.4.14 SLEEP OPERATION 17.4.17 MULTI -MASTER 2 While in Sleep mode, the I C module can receive COMMUNICATION, BUS COLLISION addresses or data and when an address match or AND BUS ARBITRATION complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 17.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 17.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag BCLIF and reset the I2C detection of the Start and Stop conditions allows the port to its Idle state (Figure 17-25). determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be moni- If a Start, Repeated Start, Stop or Acknowledge tored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in The states where arbitration can be lost are: the SSPCON2 register are cleared. When the user ser- vices the bus collision Interrupt Service Routine and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high, Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. SDA released Bus collision has occurred. by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF 2004 Microchip Technology Inc. DS41159D-page 177
- 180. PIC18FXX8 17.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure 17-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure 17-26). counts down to 0 and during this time, if the SCL pins b) SCL is sampled low before SDA is asserted low are sampled as ‘0’, a bus collision does not occur. At (Figure 17-27). the end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus If the SDA pin is already low, or the SCL pin is already masters can assert a Start condition at the low, then all of the following occur: exact same time. Therefore, one master will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus colli- • the BCLIF flag is set and sion because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address (Figure 17-26). following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software. DS41159D-page 178 2004 Microchip Technology Inc.
- 181. PIC18FXX8 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software 2004 Microchip Technology Inc. DS41159D-page 179
- 182. PIC18FXX8 17.4.17.2 Bus Collision During a Repeated counting. If SDA goes from high-to-low before the BRG Start Condition times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision a) A low level is sampled on SDA when SCL goes occurs. In this case, another master is attempting to from low level to high level. transmit a data ‘1’ during the Repeated Start condition b) SCL goes low before SDA is asserted low, (Figure 17-30). indicating that another master is attempting to transmit a data ‘1’. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is When the user deasserts SDA and the pin is allowed to reloaded and begins counting. At the end of the count, float high, the BRG is loaded with SSPADD<6:0> and regardless of the status of the SCL pin, the SCL pin is counts down to 0. The SCL pin is then deasserted and driven low and the Repeated Start condition is when sampled high, the SDA pin is sampled. complete. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 17-30: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS41159D-page 180 2004 Microchip Technology Inc.
- 183. PIC18FXX8 17.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 17-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL goes low before SDA goes high, set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ 2004 Microchip Technology Inc. DS41159D-page 181
- 184. PIC18FXX8 NOTES: DS41159D-page 182 2004 Microchip Technology Inc.
- 185. PIC18FXX8 18.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes: SYNCHRONOUS • Asynchronous (full-duplex) ASYNCHRONOUS RECEIVER • Synchronous – Master (half-duplex) TRANSMITTER (USART) • Synchronous – Slave (half-duplex). The SPEN (RCSTA register) and the TRISC<7> bits The Universal Synchronous Asynchronous Receiver have to be set and the TRISC<6> bit must be cleared Transmitter (USART) module is one of the three serial in order to configure pins RC6/TX/CK and RC7/RX/DT I/O modules incorporated into PIC18FXX8 devices. as the Universal Synchronous Asynchronous Receiver (USART is also known as a Serial Communications Transmitter. Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communi- Register 18-1 shows the Transmit Status and Control cate with peripheral devices, such as CRT terminals register (TXSTA) and Register 18-2 shows the Receive and personal computers, or it can be configured as a Status and Control register (RCSTA). half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 183
- 186. PIC18FXX8 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive (this bit is cleared after reception is complete) Synchronous mode – Slave: Unused in this mode. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 184 2004 Microchip Technology Inc.
- 187. PIC18FXX8 18.1 USART Baud Rate Generator Example 18-1 shows the calculation of the baud rate (BRG) error for the following conditions: FOSC = 16 MHz The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated Desired Baud Rate = 9600 8-bit Baud Rate Generator. The SPBRG register BRGH = 0 controls the period of a free running, 8-bit timer. In SYNC = 0 Asynchronous mode, bit BRGH (TXSTA register) also It may be advantageous to use the high baud rate controls the baud rate. In Synchronous mode, bit (BRGH = 1) even for slower baud clocks. This is BRGH is ignored. Table 18-1 shows the formula for because the FOSC/(16(X + 1)) equation can reduce the computation of the baud rate for different USART baud rate error in some cases. modes which only apply in Master mode (internal clock). Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the Given the desired baud rate and FOSC, the nearest BRG does not wait for a timer overflow before integer value for the SPBRG register can be calculated outputting the new baud rate. using the formula in Table 18-1. From this, the error in baud rate can be determined. 18.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. EXAMPLE 18-1: CALCULATING BAUD RATE ERROR Desired Baud Rate = FOSC/(64 (X + 1)) Solving for X: X = ((FOSC/Desired Baud Rate)/64) – 1 X = ((16000000/9600)/64) – 1 X = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 18-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64 (X + 1)) Baud Rate = FOSC/(16 (X + 1)) 1 (Synchronous) Baud Rate = FOSC/(4 (X + 1)) NA Legend: X = value in SPBRG (0 to 255) TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. 2004 Microchip Technology Inc. DS41159D-page 185
- 188. PIC18FXX8 TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 HIGH 10000 - 0 8250 - 0 6250 - 0 5000 - 0 LOW 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 HIGH 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 LOW 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - 0.30 +1.14 26 1.2 NA - - NA - - 1.20 +0.16 207 1.17 -2.48 6 2.4 NA - - NA - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 NA - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 NA - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 NA - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 NA - - 500 500 0 1 447.44 -10.51 1 NA - - NA - - HIGH 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 LOW 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255 DS41159D-page 186 2004 Microchip Technology Inc.
- 189. PIC18FXX8 TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 NA - - 312.50 +4.17 0 500 625 +25.00 0 NA - - NA - - NA - - HIGH 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 LOW 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 NA - - NA - - 300 250 -16.67 0 156.25 -47.92 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 LOW 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 NA - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 NA - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 NA - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 NA - - 76.8 62.50 -18.62 0 55.93 -27.17 0 NA - - NA - - 96 NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 LOW 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255 2004 Microchip Technology Inc. DS41159D-page 187
- 190. PIC18FXX8 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz 33 MHz 25 MHz 20 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 HIGH 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 LOW 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 FOSC = 16 MHz 10 MHz 7.15909 MHz 5.0688 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 NA - - HIGH 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 LOW 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 FOSC = 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG RATE value value value value % % % % (Kbps) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 NA - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 NA - - 76.8 NA - - 74.57 -2.90 2 62.50 -18.62 0 NA - - 96 NA - - 111.86 +16.52 1 NA - - NA - - 300 NA - - 223.72 -25.43 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 LOW 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255 DS41159D-page 188 2004 Microchip Technology Inc.
- 191. PIC18FXX8 18.2 USART Asynchronous Mode interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1 register). Flag bit TXIF will be set In this mode, the USART uses standard Non-Return- regardless of the state of enable bit TXIE and cannot be to-Zero (NRZ) format (one Start bit, eight or nine data cleared in software. It will reset only when new data is bits and one Stop bit). The most common data format loaded into the TXREG register. While flag bit, TXIF, is 8 bits. An on-chip dedicated 8-bit Baud Rate indicated the status of the TXREG register, another bit, Generator can be used to derive standard baud rate TRMT (TXSTA register), shows the status of the TSR frequencies from the oscillator. The USART transmits register. Status bit TRMT is a read-only bit which is set and receives the LSb first. The USART’s transmitter when the TSR register is empty. No interrupt logic is and receiver are functionally independent but use the tied to this bit, so the user has to poll this bit in order to same data format and baud rate. The Baud Rate determine if the TSR register is empty. Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH bit (TXSTA regis- Note 1: The TSR register is not mapped in data ter). Parity is not supported by the hardware but can be memory, so it is not available to the user. implemented in software (and stored as the ninth data 2: Flag bit TXIF is set when enable bit TXEN bit). Asynchronous mode is stopped during Sleep. is set. Asynchronous mode is selected by clearing the SYNC Steps to follow when setting up an Asynchronous bit (TXSTA register). Transmission: The USART Asynchronous module consists of the 1. Initialize the SPBRG register for the appropriate following important elements: baud rate. If a high-speed baud rate is desired, • Baud Rate Generator set bit BRGH (Section 18.1 “USART Baud • Sampling Circuit Rate Generator (BRG)”). • Asynchronous Transmitter 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • Asynchronous Receiver. 3. If interrupts are desired, set enable bit TXIE. 18.2.1 USART ASYNCHRONOUS 4. If 9-bit transmission is desired, set transmit bit TRANSMITTER TX9. Can be used as address/data bit. The USART transmitter block diagram is shown in 5. Enable the transmission by setting bit TXEN Figure 18-1. The heart of the transmitter is the Transmit which will also set bit TXIF. (Serial) Shift Register (TSR). The TSR register obtains 6. If 9-bit transmission is selected, the ninth bit its data from the Read/Write Transmit Buffer register should be loaded in bit TX9D. (TXREG). The TXREG register is loaded with data in 7. Load data to the TXREG register (starts software. The TSR register is not loaded until the Stop transmission). bit has been transmitted from the previous load. As Note: TXIF is not cleared immediately upon soon as the Stop bit is transmitted, the TSR is loaded loading data into the transmit buffer with new data from the TXREG register (if available). TXREG. The flag bit becomes valid in the Once the TXREG register transfers the data to the TSR second instruction cycle following the load register (occurs in one TCY), the TXREG register is instruction. empty and flag bit TXIF (PIR1 register) is set. This FIGURE 18-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D 2004 Microchip Technology Inc. DS41159D-page 189
- 192. PIC18FXX8 FIGURE 18-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 18-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit (Interrupt Reg. Flag) Word 1 Word 2 TRMT bit Word 1 (Transmit Shift Word 2 Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. DS41159D-page 190 2004 Microchip Technology Inc.
- 193. PIC18FXX8 18.2.2 USART ASYNCHRONOUS 18.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure 18-4. This mode would typically be used in RS-485 systems. The data is received on the RC7/RX/DT pin and drives Steps to follow when setting up an Asynchronous the data recovery block. The data recovery block is Reception with Address Detect Enable: actually a high-speed shifter, operating at x16 times the 1. Initialize the SPBRG register for the appropriate baud rate, whereas the main receive serial shifter oper- baud rate. If a high-speed baud rate is required, ates at the bit rate or at FOSC. This mode would set the BRGH bit. typically be used in RS-232 systems. 2. Enable the asynchronous serial port by clearing Steps to follow when setting up an Asynchronous the SYNC bit and setting the SPEN bit. Reception: 3. If interrupts are required, set the RCEN bit and 1. Initialize the SPBRG register for the appropriate select the desired priority level with the RCIP bit. baud rate. If a high-speed baud rate is desired, 4. Set the RX9 bit to enable 9-bit reception. set bit BRGH (Section 18.1 “USART Baud 5. Set the ADDEN bit to enable address detect. Rate Generator (BRG)”). 6. Enable reception by setting the CREN bit. 2. Enable the asynchronous serial port by clearing 7. The RCIF bit will be set when reception is bit SYNC and setting bit SPEN. complete. The interrupt will be Acknowledged if 3. If interrupts are desired, set enable bit RCIE. the RCIE and GIE bits are set. 4. If 9-bit reception is desired, set bit RX9. 8. Read the RCSTA register to determine if any 5. Enable the reception by setting bit CREN. error occurred during reception, as well as read 6. Flag bit RCIF will be set when reception is bit 9 of data (if applicable). complete and an interrupt will be generated if 9. Read RCREG to determine if the device is being enable bit RCIE was set. addressed. 7. Read the RCSTA register to get the ninth bit (if 10. If any error occurred, clear the CREN bit. enabled) and determine if any error occurred 11. If the device has been addressed, clear the during reception. ADDEN bit to allow all received data into the 8. Read the 8-bit received data by reading the receive buffer and interrupt the CPU. RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. FIGURE 18-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN SPBRG ÷ 64 MSb RSR Register LSb or ÷ 16 Baud Rate Generator Stop (8) 7 • • • 1 0 Start RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE Note: I/O pins have diode protection to VDD and VSS. 2004 Microchip Technology Inc. DS41159D-page 191
- 194. PIC18FXX8 FIGURE 18-5: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG RCREG Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 (1) IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. DS41159D-page 192 2004 Microchip Technology Inc.
- 195. PIC18FXX8 18.3 USART Synchronous software. It will reset only when new data is loaded into Master Mode the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT In Synchronous Master mode, the data is transmitted in (TXSTA register), shows the status of the TSR register. a half-duplex manner (i.e., transmission and reception TRMT is a read-only bit which is set when the TSR is do not occur at the same time). When transmitting data, empty. No interrupt logic is tied to this bit, so the user the reception is inhibited and vice versa. Synchronous has to poll this bit in order to determine if the TSR mode is entered by setting bit SYNC (TXSTA register). register is empty. The TSR is not mapped in data In addition, enable bit SPEN (RCSTA register) is set in memory, so it is not available to the user. order to configure the RC6/TX/CK and RC7/RX/DT I/O Steps to follow when setting up a Synchronous Master pins to CK (clock) and DT (data) lines, respectively. The Transmission: Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is 1. Initialize the SPBRG register for the appropriate entered by setting bit CSRC (TXSTA register). baud rate (Section 18.1 “USART Baud Rate Generator (BRG)”). 18.3.1 USART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits SYNC, SPEN and CSRC. The USART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit TXIE. Figure 18-1. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit TX9. (Serial) Shift Register (TSR). The shift register obtains 5. Enable the transmission by setting bit TXEN. its data from the Read/Write Transmit Buffer register 6. If 9-bit transmission is selected, the ninth bit (TXREG). The TXREG register is loaded with data in should be loaded in bit TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the TXREG bit has been transmitted from the previous load. As register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the Note: TXIF is not cleared immediately upon TXREG register transfers the data to the TSR register loading data into the transmit buffer (occurs in one TCY), the TXREG is empty and interrupt TXREG. The flag bit becomes valid in the bit TXIF (PIR1 register) is set. The interrupt can be second instruction cycle following the load enabled/disabled by setting/clearing enable bit TXIE instruction. (PIE1 register). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u (1) PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 193
- 196. PIC18FXX8 FIGURE 18-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 pin Word 1 Word 2 RC6/TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TRMT ‘1’ ‘1’ TXEN bit Note: Sync Master mode; SPBRG = 0; continuous transmission of two 8-bit words. FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit DS41159D-page 194 2004 Microchip Technology Inc.
- 197. PIC18FXX8 18.3.2 USART SYNCHRONOUS MASTER Steps to follow when setting up a Synchronous Master RECEPTION Reception: Once Synchronous Master mode is selected, reception 1. Initialize the SPBRG register for the appropriate is enabled by setting either enable bit SREN (RCSTA baud rate (Section 18.1 “USART Baud Rate register) or enable bit CREN (RCSTA register). Data is Generator (BRG)”). sampled on the RC7/RX/DT pin on the falling edge of 2. Enable the synchronous master serial port by the clock. If enable bit SREN is set, only a single word setting bits SYNC, SPEN and CSRC. is received. If enable bit CREN is set, the reception is 3. Ensure bits CREN and SREN are clear. continuous until CREN is cleared. If both bits are set, 4. If interrupts are desired, set enable bit RCIE. then CREN takes precedence. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. FIGURE 18-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. 2004 Microchip Technology Inc. DS41159D-page 195
- 198. PIC18FXX8 18.4 USART Synchronous Slave Mode 18.4.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous Slave mode differs from the Master mode in that the shift clock is supplied externally at the RC6/ The operation of the Synchronous Master and Slave TX/CK pin (instead of being supplied internally in modes is identical, except in the case of the Sleep Master mode). This allows the device to transfer or mode and bit SREN, which is a “don’t care” in Slave receive data while in Sleep mode. Slave mode is mode. entered by clearing bit CSRC (TXSTA register). If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during 18.4.1 USART SYNCHRONOUS SLAVE Sleep. On completely receiving the word, the RSR TRANSMIT register will transfer the data to the RCREG register The operation of the Synchronous Master and Slave and if enable bit RCIE bit is set, the interrupt generated modes are identical, except in the case of the Sleep will wake the chip from Sleep. If the global interrupt is mode. enabled, the program will branch to the interrupt vector. If two words are written to the TXREG and then the Steps to follow when setting up a Synchronous Slave SLEEP instruction is executed, the following will occur: Reception: a) The first word will immediately transfer to the 1. Enable the synchronous master serial port by TSR register and transmit. setting bits SYNC and SPEN and clearing bit b) The second word will remain in TXREG register. CSRC. c) Flag bit TXIF will not be set. 2. If interrupts are desired, set enable bit RCIE. d) When the first word has been shifted out of TSR, 3. If 9-bit reception is desired, set bit RX9. the TXREG register will transfer the second 4. To enable reception, set enable bit CREN. word to the TSR and flag bit TXIF will be set. 5. Flag bit RCIF will be set when reception is e) If enable bit TXIE is set, the interrupt will wake complete. An interrupt will be generated if the chip from Sleep. If the global interrupt is enable bit RCIE was set. enabled, the program will branch to the interrupt 6. Read the RCSTA register to get the ninth bit (if vector. enabled) and determine if any error occurred Steps to follow when setting up a Synchronous Slave during reception. Transmission: 7. Read the 8-bit received data by reading the RCREG register. 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit 8. If any error occurred, clear the error by clearing CSRC. bit CREN. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. DS41159D-page 196 2004 Microchip Technology Inc.
- 199. PIC18FXX8 TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s. 2004 Microchip Technology Inc. DS41159D-page 197
- 200. PIC18FXX8 NOTES: DS41159D-page 198 2004 Microchip Technology Inc.
- 201. PIC18FXX8 19.0 CAN MODULE 19.1.1 OVERVIEW OF THE MODULE The CAN bus module consists of a protocol engine and 19.1 Overview message buffering and control. The CAN protocol engine handles all functions for receiving and transmit- The Controller Area Network (CAN) module is a serial ting messages on the CAN bus. Messages are interface, useful for communicating with other peripher- transmitted by first loading the appropriate data als or microcontroller devices. This interface/protocol registers. Status and errors can be checked by reading was designed to allow communications within noisy the appropriate registers. Any message detected on environments. the CAN bus is checked for errors and then matched The CAN module is a communication controller, against filters to see if it should be received and stored implementing the CAN 2.0 A/B protocol as defined in in one of the 2 receive registers. the BOSCH specification. The module will support The CAN module supports the following frame types: CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implemen- • Standard Data Frame tation is a full CAN system. The CAN specification is • Extended Data Frame not covered within this data sheet. The reader may • Remote Frame refer to the BOSCH CAN specification for further • Error Frame details. • Overload Frame Reception The module features are as follows: • Interframe Space • Complies with ISO CAN Conformance Test CAN module uses RB3/CANRX and RB2/CANTX/INT2 • Implementation of the CAN protocol CAN 1.2, pins to interface with CAN bus. In order to configure CAN 2.0A and CAN 2.0B CANRX and CANTX as CAN interface: • Standard and extended data frames • bit TRISB<3> must be set; • 0-8 bytes data length • bit TRISB<2> must be cleared. • Programmable bit rate up to 1 Mbit/sec • Support for remote frames 19.1.2 TRANSMIT/RECEIVE BUFFERS • Double-buffered receiver with two prioritized The PIC18FXX8 has three transmit and two receive received message storage buffers buffers, two acceptance masks (one for each receive • 6 full (standard/extended identifier) acceptance buffer) and a total of six acceptance filters. Figure 19-1 filters, 2 associated with the high priority receive is a block diagram of these buffers and their connection buffer and 4 associated with the low priority to the protocol engine. receive buffer • 2 full acceptance filter masks, one each associated with the high and low priority receive buffers • Three transmit buffers with application specified prioritization and abort capability • Programmable wake-up functionality with integrated low-pass filter • Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-power Sleep mode 2004 Microchip Technology Inc. DS41159D-page 199
- 202. PIC18FXX8 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS Accept Acceptance Mask RXM1 TXREQ TXB0 Acceptance Filter TXABT RXM2 TXLARB MESSAGE Accept TXERR Acceptance Mask Acceptance Filter TXBUFF RXM0 RXF3 TXREQ TXB1 Acceptance Filter Acceptance Filter TXABT MESSAGE RXF0 RXF4 TXLARB TXERR TXBUFF Acceptance Filter Acceptance Filter RXF1 RXF5 TXREQ TXB2 Message TXABT TXLARB MESSAGE Request TXERR RXB0 RXB1 TXBUFF Message Data and Data and Identifier Identifier Identifier Identifier Queue Control Transmit Byte Sequencer Message Assembly Buffer PROTOCOL ENGINE Transmit Shift Receive Shift RXERRCNT Comparator CRC Register Bus-Off Bit Timing Generator Transmit Protocol Err-Pas Logic FSM Bit Timing Logic Transmit Receive TXERRCNT Error Error Counter Counter TX RX DS41159D-page 200 2004 Microchip Technology Inc.
- 203. PIC18FXX8 19.2 CAN Module Registers 19.2.1 CAN CONTROL AND STATUS REGISTERS Note: Not all CAN registers are available in the Access Bank. The registers described in this section control the overall operation of the CAN module and show its There are many control and data registers associated operational status. with the CAN module. For convenience, their descriptions have been grouped into the following sections: • Control and Status Registers • Transmit Buffer Registers (Data and Control) • Receive Buffer Registers (Data and Control) • Baud Rate Control Registers • I/O Control Register • Interrupt Status and Control Registers REGISTER 19-1: CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — bit 7 bit 0 bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal bit 3-1 WIN2:WIN0: Window Address bits This selects which of the CAN buffers to switch into the Access Bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See Example 19-1 for code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 201
- 204. PIC18FXX8 REGISTER 19-2: CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0 OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — bit 7 bit 0 bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable mode 000 = Normal mode Note: Before the device goes into Sleep mode, select Disable mode. bit 4 Unimplemented: Read as ‘0’ bit 3-1 ICODE2:ICODE0: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in the ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access Bank area. See Example 19-1 for code example. 111 = Wake-up on interrupt 110 = RXB0 interrupt 101 = RXB1 interrupt 100 = TXB0 interrupt 011 = TXB1 interrupt 010 = TXB2 interrupt 001 = Error interrupt 000 = No interrupt bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 202 2004 Microchip Technology Inc.
- 205. PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW b’00001110’ ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here … NoInterrupt … ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer 2004 Microchip Technology Inc. DS41159D-page 203
- 206. PIC18FXX8 EXAMPLE 19-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANCON.ICODE bits to CANSTAT.WIN bits MOVF CANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW b’11110001’ ; Use previously saved CANCON value to ; make sure same value. MOVWF CANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW b’00001110’ ; Use previously saved CANSTAT value ; to make sure same value. IORWF CANCON ; Copy ICODE bits to WIN bits. ; Copy the result to actual CANCON ; Access current buffer… ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW b’11110001’ IORWF TempCANCON, W ; Restore original WIN bits MOVWF CANCON ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS41159D-page 204 2004 Microchip Technology Inc.
- 207. PIC18FXX8 REGISTER 19-3: COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 bit 7 RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed bit 6 RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit Error Counter > 255 0 = Transmit Error Counter ≤ 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmission Error Counter > 127 0 = Transmission Error Counter ≤ 127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive Error Counter > 127 0 = Receive Error Counter ≤ 127 bit 2 TXWARN: Transmitter Warning bit 1 = 127 ≥ Transmit Error Counter > 95 0 = Transmit Error Counter ≤ 95 bit 1 RXWARN: Receiver Warning bit 1 = 127 ≥ Receive Error Counter > 95 0 = Receive Error Counter ≤ 95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 205
- 208. PIC18FXX8 19.2.2 CAN TRANSMIT BUFFER REGISTERS This section describes the CAN Transmit Buffer registers and their associated control registers. REGISTER 19-4: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TXABT: Transmission Aborted Status bit 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit 1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits. 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software while the bit is set will request a message abort. bit 2 Unimplemented: Read as ‘0’ bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note: These bits set the order in which the Transmit Buffer will be transferred. They do not alter the CAN message identifier. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 206 2004 Microchip Technology Inc.
- 209. PIC18FXX8 REGISTER 19-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits if EXIDE = 0 (TXBnSID Register) or Extended Identifier bits EID28:EID21 if EXIDE = 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-6: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits if EXIDE = 0 or Extended Identifier bits EID20:EID18 if EXIDE = 1 bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier enable bit 1 = Message will transmit extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit standard ID, EID17:EID0 are ignored bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-7: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 207
- 210. PIC18FXX8 REGISTER 19-8: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-9: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 bit 7-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8) Each Transmit Buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 208 2004 Microchip Technology Inc.
- 211. PIC18FXX8 REGISTER 19-10: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmission Frame Remote Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-11: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 bit 7-0 TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 209
- 212. PIC18FXX8 19.2.3 CAN RECEIVE BUFFER REGISTERS This section shows the Receive Buffer registers with their associated control registers. REGISTER 19-12: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 (1) (1) (1) RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and must be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits(1) 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages bit 4 Unimplemented: Read as ‘0’ bit 3 RXRTRRO: Receive Remote Transfer Request Read-Only bit 1 = Remote transfer request 0 = No remote transfer request bit 2 RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 bit 1 JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Note: This bit allows same filter jump table for both RXB0CON and RXB1CON. bit 0 FILHIT0: Filter Hit bit This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Note 1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON. Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 210 2004 Microchip Technology Inc.
- 213. PIC18FXX8 REGISTER 19-13: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0 RXFUL(1) RXM1(1) RXM0(1) — RXRTRRO FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. bit 6-5 RXM1:RXM0: Receive Buffer Mode bits(1) 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages bit 4 Unimplemented: Read as ‘0’ bit 3 RXRTRRO: Receive Remote Transfer Request bit (read-only) 1 = Remote transfer request 0 = No remote transfer request bit 2-0 FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Note 1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON. Legend: R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 211
- 214. PIC18FXX8 REGISTER 19-14: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits if EXID = 0 (RXBnSIDL Register) or Extended Identifier bits EID28:EID21 if EXID = 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-15: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits if EXID = 0 or Extended Identifier bits EID20:EID18 if EXID = 1 bit 4 SRR: Substitute Remote Request bit This bit is always ‘0’ when EXID = 1 or equal to the value of RXRTRRO (RXnBCON<3>) when EXID = 0. bit 3 EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard data frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-16: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 212 2004 Microchip Technology Inc.
- 215. PIC18FXX8 REGISTER 19-17: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-18: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN spec and read as ‘0’. bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 213
- 216. PIC18FXX8 REGISTER 19-19: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 bit 7-0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-20: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 bit 7-0 REC7:REC0: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not have the ability to put the module in “Bus-Off” state. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 214 2004 Microchip Technology Inc.
- 217. PIC18FXX8 19.2.3.1 Message Acceptance Filters and Masks This subsection describes the message acceptance filters and masks for the CAN receive buffers. REGISTER 19-21: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Filter bits if EXIDEN = 0 or Extended Identifier Filter bits EID28:EID21 if EXIDEN = 1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-22: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Filter bits if EXIDEN = 0 or Extended Identifier Filter bits EID20:EID18 if EXIDEN = 1 bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDEN: Extended Identifier Filter Enable bit 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 215
- 218. PIC18FXX8 REGISTER 19-23: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-24: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Filter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-25: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Mask bits or Extended Identifier Mask bits EID28:EID21 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 216 2004 Microchip Technology Inc.
- 219. PIC18FXX8 REGISTER 19-26: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK, LOW BYTE REGISTERS R/W-x R/W-x R/W-x U-0 U-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — — — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18 bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-27: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK, HIGH BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 19-28: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK, LOW BYTE REGISTERS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 217
- 220. PIC18FXX8 19.2.4 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. REGISTER 19-29: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization Jump Width Time = 4 x TQ 10 = Synchronization Jump Width Time = 3 x TQ 01 = Synchronization Jump Width Time = 2 x TQ 00 = Synchronization Jump Width Time = 1 x TQ bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: This register is accessible in Configuration mode only. DS41159D-page 218 2004 Microchip Technology Inc.
- 221. PIC18FXX8 REGISTER 19-30: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 Time = 8 x TQ 110 = Phase Segment 1 Time = 7 x TQ 101 = Phase Segment 1 Time = 6 x TQ 100 = Phase Segment 1 Time = 5 x TQ 011 = Phase Segment 1 Time = 4 x TQ 010 = Phase Segment 1 Time = 3 x TQ 001 = Phase Segment 1 Time = 2 x TQ 000 = Phase Segment 1 Time = 1 x TQ bit 2-0 PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation Time = 8 x TQ 110 = Propagation Time = 7 x TQ 101 = Propagation Time = 6 x TQ 100 = Propagation Time = 5 x TQ 011 = Propagation Time = 4 x TQ 010 = Propagation Time = 3 x TQ 001 = Propagation Time = 2 x TQ 000 = Propagation Time = 1 x TQ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: This register is accessible in Configuration mode only. 2004 Microchip Technology Inc. DS41159D-page 219
- 222. PIC18FXX8 REGISTER 19-31: BRGCON3: BAUD RATE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 Time = 8 x TQ 110 = Phase Segment 2 Time = 7 x TQ 101 = Phase Segment 2 Time = 6 x TQ 100 = Phase Segment 2 Time = 5 x TQ 011 = Phase Segment 2 Time = 4 x TQ 010 = Phase Segment 2 Time = 3 x TQ 001 = Phase Segment 2 Time = 2 x TQ 000 = Phase Segment 2 Time = 1 x TQ Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 220 2004 Microchip Technology Inc.
- 223. PIC18FXX8 19.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller. REGISTER 19-32: CIOCON: CAN I/O CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — ENDRHI CANCAP — — — — bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 ENDRHI: Enable Drive High bit 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 221
- 224. PIC18FXX8 19.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 8.0 “Interrupts”. They are duplicated here for convenience. REGISTER 19-33: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF bit 7 bit 0 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message bit 0 RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 222 2004 Microchip Technology Inc.
- 225. PIC18FXX8 REGISTER 19-34: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE bit 7 bit 0 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt bit 0 RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 223
- 226. PIC18FXX8 REGISTER 19-35: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS41159D-page 224 2004 Microchip Technology Inc.
- 227. PIC18FXX8 TABLE 19-1: CAN CONTROLLER REGISTER MAP Address Name Address Name Address Name Address Name F7Fh — F5Fh — F3Fh — F1Fh RXM1EIDL (2) (2) F7Eh — F5Eh CANSTATRO1 F3Eh CANSTATRO3 F1Eh RXM1EIDH F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h — F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h — F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh — F2Fh — F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTATRO2(2) F2Eh CANSTATRO4(2) F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 2004 Microchip Technology Inc. DS41159D-page 225
- 228. PIC18FXX8 19.3 CAN Modes of Operation 19.3.2 DISABLE MODE The PIC18FXX8 has six main modes of operation: In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit • Configuration mode due to bus activity, however, any pending interrupts will • Disable mode remain and the error counters will retain their value. • Normal Operation mode If REQOP<2:0> is set to ‘001’, the module will enter the • Listen Only mode Module Disable mode. This mode is similar to disabling • Loopback mode other peripheral modules by turning off the module • Error Recognition mode enables. This causes the module internal clock to stop unless the module is active (i.e., receiving or transmit- All modes, except Error Recognition, are requested by ting a message). If the module is active, the module will setting the REQOP bits (CANCON<7:5>); Error Recog- wait for 11 recessive bits on the CAN bus, detect that nition is requested through the RXM bits of the Receive condition as an IDLE bus, then accept the module Buffer register(s). Entry into a mode is Acknowledged disable command. OPMODE<2:0> = 001 indicates by monitoring the OPMODE bits. whether the module successfully went into Module When changing modes, the mode will not actually Disable mode. change until all pending message transmissions are The WAKIF interrupt is the only module interrupt that is complete. Because of this, the user must verify that the still active in the Module Disable mode. If the WAKIE is device has actually changed into the requested mode set, the processor will receive an interrupt whenever before fUrther Operations Are Executed. the CAN bus detects a dominant state, as occurs with a SOF. If the processor receives an interrupt while it is 19.3.1 CONFIGURATION MODE sleeping, more than one message may get lost. User The CAN module has to be initialized before the firmware must anticipate this condition and request activation. This is only possible if the module is in the retransmission. If the processor is running while it Configuration mode. The Configuration mode is receives an interrupt, only the first message may get requested by setting the REQOP2 bit. Only when the lost. OPMODE2 status bit has a high level can the initializa- The I/O pins will revert to normal I/O function when the tion be performed. Afterwards, the Configuration module is in the Module Disable mode. registers, the Acceptance Mask registers and the Acceptance Filter registers can be written. The module 19.3.3 NORMAL MODE is activated by setting the REQOP control bits to zero. This is the standard operating mode of the PIC18FXX8. The module will protect the user from accidentally In this mode, the device actively monitors all bus violating the CAN protocol through programming messages and generates Acknowledge bits, error errors. All registers which control the configuration of frames, etc. This is also the only mode in which the the module can not be modified while the module is on- PIC18FXX8 will transmit messages over the CAN bus. line. The CAN module will not be allowed to enter the Configuration mode while a transmission is taking 19.3.4 LISTEN ONLY MODE place. The CONFIG bit serves as a lock to protect the following registers. Listen Only mode provides a means for the PIC18FXX8 to receive all messages, including • Configuration registers messages with errors. This mode can be used for bus • Bus Timing registers monitor applications or for detecting the baud rate in • Identifier Acceptance Filter registers ‘hot plugging’ situations. For auto-baud detection, it is • Identifier Acceptance Mask registers necessary that there are at least two other nodes which are communicating with each other. The baud rate can In the Configuration mode, the module will not transmit be detected empirically by testing different values until or receive. The error counters are cleared and the valid messages are received. The Listen Only mode is interrupt flags remain unchanged. The programmer will a silent mode, meaning no messages will be trans- have access to Configuration registers that are access mitted while in this state, including error flags or restricted in other modes. Acknowledge signals. The filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. DS41159D-page 226 2004 Microchip Technology Inc.
- 229. PIC18FXX8 19.3.5 LOOPBACK MODE 19.4.2 TRANSMIT PRIORITY This mode will allow internal transmission of messages Transmit priority is a prioritization within the from the transmit buffers to the receive buffers without PIC18FXX8 of the pending transmittable messages. actually transmitting messages on the CAN bus. This This is independent from and not related to any prioriti- mode can be used in system development and testing. zation implicit in the message arbitration scheme built In this mode, the ACK bit is ignored and the device will into the CAN protocol. Prior to sending the SOF, the allow incoming messages from itself, just as if they priority of all buffers that are queued for transmission is were coming from another node. The Loopback mode compared. The transmit buffer with the highest priority is a silent mode, meaning no messages will be trans- will be sent first. If two buffers have the same priority mitted while in this state, including error flags or setting, the buffer with the highest buffer number will be Acknowledge signals. The TXCAN pin will revert to port sent first. There are four levels of transmit priority. If I/O while the device is in this mode. The filters and TXP bits for a particular message buffer are set to ‘11’, masks can be used to allow only particular messages that buffer has the highest possible priority. If TXP bits to be loaded into the receive registers. The masks can for a particular message buffer are ‘00’, that buffer has be set to all zeros to provide a mode that accepts all the lowest possible priority. messages. The Loopback mode is activated by setting the mode request bits in the CANCON register. FIGURE 19-2: TRANSMIT BUFFER BLOCK DIAGRAM 19.3.6 ERROR RECOGNITION MODE The module can be set to ignore all errors and receive TXREQ TXB0 all message. The Error Recognition mode is activated TXABT by setting the RXM<1:0> bits in the RXBnCON TXLARB MESSAGE registers to ‘11’. In this mode, all messages, valid or TXERR TXBUFF invalid, are received and copied to the receive buffer. TXREQ TXB1 19.4 CAN Message Transmission TXABT TXLARB MESSAGE TXERR 19.4.1 TRANSMIT BUFFERS TXBUFF The PIC18FXX8 implements three transmit buffers TXREQ TXB2 (Figure 19-2). Each of these buffers occupies 14 bytes Message TXABT of SRAM and are mapped into the device memory Request MESSAGE TXLARB map. TXERR TXBUFF For the MCU to have write access to the message Message buffer, the TXREQ bit must be clear, indicating that the Queue Control message buffer is clear of any pending message to be transmitted. At a minimum, the TXBnSIDH, TXBnSIDL Transmit Byte Sequencer and TXBnDLC registers must be loaded. If data bytes are present in the message, the TXBnDm registers must also be loaded. If the message is to use extended identifiers, the TXBnEIDm registers must also be loaded and the EXIDE bit set. Prior to sending the message, the MCU must initialize the TXInE bit to enable or disable the generation of an interrupt when the message is sent. The MCU must also initialize the TXP priority bits (see Section 19.4.2 “Transmit Priority”). 2004 Microchip Technology Inc. DS41159D-page 227
- 230. PIC18FXX8 19.4.3 INITIATING TRANSMISSION 19.4.4 ABORTING TRANSMISSION To initiate message transmission, the TXREQ bit must The MCU can request to abort a message by clearing be set for each buffer to be transmitted. When TXREQ the TXREQ bit associated with the corresponding is set, the TXABT, TXLARB and TXERR bits will be message buffer (TXBnCON<3>). Setting the ABAT bit cleared. (CANCON<4>) will request an abort of all pending Setting the TXREQ bit does not initiate a message messages. If the message has not yet started transmis- transmission; it merely flags a message buffer as ready sion, or if the message started but is interrupted by loss for transmission. Transmission will start when the of arbitration or an error, the abort will be processed. device detects that the bus is available. The device will The abort is indicated when the module sets the ABT then begin transmission of the highest priority message bits for the corresponding buffer (TXBnCON<6>). If the that is ready. message has started to transmit, it will attempt to transmit the current message fully. If the current When the transmission has completed successfully, message is transmitted fully and is not lost to arbitration the TXREQ bit will be cleared, the TXBnIF bit will be set or an error, the ABT bit will not be set because the and an interrupt will be generated if the TXBnIE bit is message was transmitted successfully. Likewise, if a set. message is being transmitted during an abort request If the message transmission fails, the TXREQ will and the message is lost to arbitration or an error, the remain set, indicating that the message is still pending message will not be retransmitted and the ABT bit will for transmission and one of the following condition flags be set, indicating that the message was successfully will be set. If the message started to transmit but aborted. encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set. DS41159D-page 228 2004 Microchip Technology Inc.
- 231. PIC18FXX8 FIGURE 19-3: INTERNAL TRANSMIT MESSAGE FLOWCHART Start The message transmission sequence begins when the device determines that the TXREQ for any of the transmit registers has been set. No Are any TXREQ bits = 1? Clearing the TXREQ bit while it is set, or setting Yes the ABAT bit before the message has started transmission, will abort the message. Clear: TXABT, TXLARB and TXERR No Is CAN bus No Is Yes Available to Start TXREQ = 0 Transmission? ABAT = 1? Yes Examine TXPRI <1:0> to Determine Highest Priority Message Begin Transmission (SOF) Was No Message Transmitted Set Successfully? TXERR = 1 Yes Set TXREQ = 0 Is Yes Arbitration Lost During TXLARB = 1? Transmission Yes Generate Is Interrupt TXIE = 1? A message can also be No aborted if a message error or lost arbitration No condition occurred during transmission. Is TXREQ = 0 Yes or TXABT = 1? Set TXBUFE = 1 The TXIE bit determines if an inter- No rupt should be generated when a Abort Transmission: message is successfully transmitted. Set TXABT = 1 END 2004 Microchip Technology Inc. DS41159D-page 229
- 232. PIC18FXX8 19.5 Message Reception The RXM bits set special Receive modes. Normally, these bits are set to ‘00’ to enable reception of all valid 19.5.1 RECEIVE MESSAGE BUFFERING messages as determined by the appropriate accep- The PIC18FXX8 includes two full receive buffers with tance filters. In this case, the determination of whether multiple acceptance filters for each. There is also a or not to receive standard or extended messages is separate Message Assembly Buffer (MAB) which acts determined by the EXIDE bit in the Acceptance Filter as a third receive buffer (see Figure 19-4). register. If the RXM bits are set to ‘01’ or ‘10’, the receiver will accept only messages with standard or 19.5.2 RECEIVE BUFFERS extended identifiers, respectively. If an acceptance filter has the EXIDE bit set, such that it does not corre- Of the three receive buffers, the MAB is always commit- spond with the RXM mode, that acceptance filter is ted to receiving the next message from the bus. The rendered useless. These two modes of RXM bits can remaining two receive buffers are called RXB0 and be used in systems where it is known that only standard RXB1 and can receive a complete message from the or extended messages will be on the bus. If the RXM protocol engine. The MCU can access one buffer while bits are set to ‘11’, the buffer will receive all messages the other buffer is available for message reception or regardless of the values of the acceptance filters. Also, holding a previously received message. if a message has an error before the end of frame, that The MAB assembles all messages received. These portion of the message assembled in the MAB before messages will be transferred to the RXBn buffers only the error frame will be loaded into the buffer. This mode if the acceptance filter criteria are met. has some value in debugging a CAN system and would not be used in an actual system environment. Note: The entire contents of the MAB are moved into the receive buffer once a message is 19.5.4 TIME-STAMPING accepted. This means that regardless of the type of identifier (standard or The CAN module can be programmed to generate a extended) and the number of data bytes time-stamp for every message that is received. When received, the entire receive buffer is over- enabled, the module generates a capture signal for written with the MAB contents. Therefore, CCP1 which in turns captures the value of either Timer1 or Timer3. This value can be used as the the contents of all registers in the buffer message time-stamp. must be assumed to have been modified when any message is received. To use the time-stamp capability, the CANCAP bit (CIOCAN<4>) must be set. This replaces the capture When a message is moved into either of the receive input for CCP1 with the signal generated from the CAN buffers, the appropriate RXBnIF bit is set. This bit must module. In addition, CCP1CON<3:0> must be set to be cleared by the MCU when it has completed process- ‘0011’ to enable the CCP special event trigger for CAN ing the message in the buffer in order to allow a new events. message to be received into the buffer. This bit provides a positive lockout to ensure that the MCU has finished with the message before the PIC18FXX8 FIGURE 19-4: RECEIVE BUFFER BLOCK attempts to load a new message into the receive buffer. DIAGRAM If the RXBnIE bit is set, an interrupt will be generated to Accept Acceptance Mask indicate that a valid message has been received. RXM1 19.5.3 RECEIVE PRIORITY Acceptance Filter RXB0 is the higher priority buffer and has two message RXM2 Accept acceptance filters associated with it. RXB1 is the lower Acceptance Mask Acceptance Filter priority buffer and has four acceptance filters associ- RXM0 RXF3 ated with it. The lower number of acceptance filters makes the match on RXB0 more restrictive and implies Acceptance Filter Acceptance Filter a higher priority for that buffer. Additionally, the RXF0 RXF4 RXB0CON register can be configured such if RXB0 contains a valid message and another valid message is Acceptance Filter Acceptance Filter RXF1 RXF5 received, an overflow error will not occur and the new message will be moved into RXB1 regardless of the acceptance criteria of RXB1. There are also two RXB0 RXB1 programmable acceptance filter masks available, one for each receive buffer (see Section 19.6 “Message Data and Data and Identifier Identifier Identifier Identifier Acceptance Filters and Masks”). When a message is received, bits <3:0> of the Message Assembly Buffer RXBnCON register will indicate the acceptance filter number that enabled reception and whether the received message is a remote transfer request. DS41159D-page 230 2004 Microchip Technology Inc.
- 233. PIC18FXX8 FIGURE 19-5: INTERNAL MESSAGE RECEPTION FLOWCHART Start Detect No Start of Message? Yes Begin Loading Message into Message Assembly Buffer (MAB) Generate No Valid Error Message Frame Received? Yes Yes, meets criteria Yes, meets criteria for RXBO Message for RXB1 Identifier meets a Filter Criteria? No Go to Start The RXFUL bit determines if the receive register is empty and able to accept a new message. The RXB0DBEN bit determines if RXB0 can rollover into RXB1 if it is full. Is No Is Yes RXFUL = 0? RX0DBEN = 1? Yes No No Is Move Message into RXB0 Generate Overrun Error: Generate Overrun Error: RXFUL = 0? Set RXB0OVFL Set RXB1OVFL Set RXRDY = 1 Yes Move Message into RXB1 Set FILHIT <0> Is No according to which Filter ERRIE = 1? Criteria was met Set RXRDY = 1 Yes Go to Start Set FILHIT <2:0> according to which Filter Criteria was met Is Yes Yes Is Generate RXIE = 1? Interrupt RXIE = 1? No No Set CANSTAT <3:0> according to which Receive Buffer the Message was loaded into 2004 Microchip Technology Inc. DS41159D-page 231
- 234. PIC18FXX8 19.6 Message Acceptance Filters For RXB1, the RXB1CON register contains the and Masks FILHIT<2:0> bits. They are coded as follows: • 101 = Acceptance Filter 5 (RXF5) The message acceptance filters and masks are used to determine if a message in the message assembly • 100 = Acceptance Filter 4 (RXF4) buffer should be loaded into either of the receive buff- • 011 = Acceptance Filter 3 (RXF3) ers. Once a valid message has been received into the • 010 = Acceptance Filter 2 (RXF2) MAB, the identifier fields of the message are compared • 001 = Acceptance Filter 1 (RXF1) to the filter values. If there is a match, that message will • 000 = Acceptance Filter 0 (RXF0) be loaded into the appropriate receive buffer. The filter masks are used to determine which bits in the identifier Note: ‘000’ and ‘001’ can only occur if the are examined with the filters. A truth table is shown RXB0DBEN bit is set in the RXB0CON below in Table 19-2 that indicates how each bit in the register allowing RXB0 messages to identifier is compared to the masks and filters to deter- rollover into RXB1. mine if a message should be loaded into a receive buffer. The mask essentially determines which bits to The coding of the RXB0DBEN bit enables these three apply the acceptance filters to. If any mask bit is set to bits to be used similarly to the FILHIT bits and to a zero, then that bit will automatically be accepted distinguish a hit on filter RXF0 and RXF1, in either regardless of the filter bit. RXB0, or after a rollover into RXB1. • 111 = Acceptance Filter 1 (RXF1) TABLE 19-2: FILTER/MASK TRUTH TABLE • 110 = Acceptance Filter 0 (RXF0) Message Accept or • 001 = Acceptance Filter 1 (RXF1) Mask Filter bit n Identifier Reject • 000 = Acceptance Filter 0 bit n bit n001 bit n If the RXB0DBEN bit is clear, there are six codes 0 x x Accept corresponding to the six filters. If the RXB0DBEN bit is 1 0 0 Accept set, there are six codes corresponding to the six filters plus two additional codes corresponding to RXF0 and 1 0 1 Reject RXF1 filters that rollover into RXB1. 1 1 0 Reject If more than one acceptance filter matches, the FILHIT 1 1 1 Accept bits will encode the binary value of the lowest Legend: x = don’t care numbered filter that matched. In other words, if filter RXF2 and filter RXF4 match, FILHIT will be loaded with As shown in the receive buffer block diagram the value for RXF2. This essentially prioritizes the (Figure 19-4), acceptance filters RXF0 and RXF1 and acceptance filters with a lower number filter having filter mask RXM0 are associated with RXB0. Filters higher priority. Messages are compared to filters in RXF2, RXF3, RXF4 and RXF5 and mask RXM1 are ascending order of filter number. associated with RXB1. When a filter matches and a message is loaded into the receive buffer, the filter The mask and filter registers can only be modified number that enabled the message reception is loaded when the PIC18FXX8 is in Configuration mode. The into the FILHIT bit(s). mask and filter registers cannot be read outside of Configuration mode. When outside of Configuration mode, all mask and filter registers will be read as ‘0’. FIGURE 19-6: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFn0 RXMn0 RXFn1 RXMn1 RxRqst RXFnn RXMnn Message Assembly Buffer Identifier DS41159D-page 232 2004 Microchip Technology Inc.
- 235. PIC18FXX8 19.7 Baud Rate Setting The Nominal Bit Time is defined as: All nodes on a given CAN bus must have the same TBIT = 1/Nominal Bit Rate nominal bit rate. The CAN protocol uses Non-Return- The nominal bit time can be thought of as being divided to-Zero (NRZ) coding which does not encode a clock into separate, non-overlapping time segments. These within the data stream. Therefore, the receive clock segments (Figure 19-7) include: must be recovered by the receiving nodes and • Synchronization Segment (Sync_Seg) synchronized to the transmitters clock. • Propagation Time Segment (Prop_Seg) As oscillators and transmission time may vary from • Phase Buffer Segment 1 (Phase_Seg1) node to node, the receiver must have some type of • Phase Buffer Segment 2 (Phase_Seg2) Phase Lock Loop (PLL) synchronized to data transmis- sion edges to synchronize and maintain the receiver The time segments (and thus, the nominal bit time) are, clock. Since the data is NRZ coded, it is necessary to in turn, made up of integer units of time called time include bit stuffing to ensure that an edge occurs at quanta or TQ (see Figure 19-7). By definition, the least every six bit times to maintain the Digital Phase nominal bit time is programmable from a minimum of Lock Loop (DPLL) synchronization. 8 TQ to a maximum of 25 TQ. Also, by definition, the minimum nominal bit time is 1 µs corresponding to a The bit timing of the PIC18FXX8 is implemented using maximum 1 Mb/s rate. The actual duration is given by a DPLL that is configured to synchronize to the the relationship: incoming data and provides the nominal timing for the transmitted data. The DPLL breaks each bit time into Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + multiple segments made up of minimal periods of time Phase_Seg1 + Phase_Seg2) called the Time Quanta (TQ). The time quantum is a fixed unit derived from the Bus timing functions executed within the bit time frame, oscillator period. It is also defined by the programmable such as synchronization to the local oscillator, network baud rate prescaler, with integer values from 1 to 64, in transmission delay compensation and sample point addition to a fixed divide-by-two for clock generation. positioning, are defined by the programmable bit timing Mathematically, this is logic of the DPLL. TQ (µs) = (2 * (BRP + 1))/FOSC (MHz) All devices on the CAN bus must use the same bit rate. or However, all devices are not required to have the same master oscillator clock frequency. For the different clock TQ (µs) = (2 * (BRP + 1)) * TOSC (µs) frequencies of the individual devices, the bit rate has to where FOSC is the clock frequency, TOSC is the be adjusted by appropriately setting the baud rate corresponding oscillator period and BRP is an integer prescaler and number of time quanta in each segment. (0 through 63) represented by the binary values of The Nominal Bit Rate is the number of bits transmitted BRGCON1<5:0>. per second, assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. The nominal bit rate is defined to be a maximum of 1 Mb/s. FIGURE 19-7: BIT TIME PARTITIONING Input Signal Sync Propagation Phase Phase Bit Segment Segment Segment 1 Segment 2 Time Intervals TQ Sample Point Nominal Bit Time 2004 Microchip Technology Inc. DS41159D-page 233
- 236. PIC18FXX8 19.7.1 TIME QUANTA 19.7.2 SYNCHRONIZATION SEGMENT As already mentioned, the time quanta is a fixed unit This part of the bit time is used to synchronize the derived from the oscillator period and baud rate various CAN nodes on the bus. The edge of the input prescaler. Its relationship to TBIT and the nominal bit signal is expected to occur during the sync segment. rate is shown in Example 19-2. The duration is 1 TQ. EXAMPLE 19-2: CALCULATING TQ, 19.7.3 PROPAGATION SEGMENT NOMINAL BIT RATE AND This part of the bit time is used to compensate for NOMINAL BIT TIME physical delay times within the network. These delay TQ (µs) = (2 * (BRP + 1))/FOSC (MHz) times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length TBIT (µs) = TQ (µs) * number of TQ per bit interval of the Propagation Segment can be programmed from Nominal Bit Rate (bits/s) = 1/TBIT 1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits. 19.7.4 PHASE BUFFER SEGMENTS CASE 1: The phase buffer segments are used to optimally For FOSC = 16 MHz, BRP<5:0> = 00h and locate the sampling point of the received bit within the Nominal Bit Time = 8 TQ: nominal bit time. The sampling point occurs between TQ = (2 * 1)/16 = 0.125 µs (125 ns) Phase Segment 1 and Phase Segment 2. These segments can be lengthened or shortened by the TBIT = 8 * 0.125 = 1 µs (10-6s) resynchronization process. The end of Phase Segment Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) 1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase Segment 2 provides delay before CASE 2: the next transmitted data transition and is also For FOSC = 20 MHz, BRP<5:0> = 01h and programmable from 1 TQ to 8 TQ in duration. However, Nominal Bit Time = 8 TQ: due to IPT requirements, the actual minimum length of Phase Segment 2 is 2 TQ or it may be defined to be TQ = (2 * 2)/20 = 0.2 µs (200 ns) equal to the greater of Phase Segment 1 or the TBIT = 8 * 0.2 = 1.6 µs (1.6 * 10-6s) Information Processing Time (IPT). Nominal Bit Rate = 1/1.6 * 10-6s = 625,000 bits/s (625 Kb/s) 19.7.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and the value of the received bit is deter- CASE 3: mined. The sampling point occurs at the end of Phase For FOSC = 25 MHz, BRP<5:0> = 3Fh and Segment 1. If the bit timing is slow and contains many Nominal Bit Time = 25 TQ: TQ, it is possible to specify multiple sampling of the bus TQ = (2 * 64)/25 = 5.12 µs line at the sample point. The value of the received bit is determined to be the value of the majority decision of TBIT = 25 * 5.12 = 128 µs (1.28 * 10-4s) three values. The three samples are taken at the sam- Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s ple point and twice before, with a time of TQ/2 between (7.8 Kb/s) each sample. The frequencies of the oscillators in the different nodes 19.7.6 INFORMATION PROCESSING TIME must be coordinated in order to provide a system wide The Information Processing Time (IPT) is the time specified nominal bit time. This means that all oscilla- segment, starting at the sample point, that is reserved tors must have a TOSC that is an integral divisor of TQ. for calculation of the subsequent bit level. The CAN It should also be noted that although the number of TQ specification defines this time to be less than or equal is programmable from 4 to 25, the usable minimum is to 2 TQ. The PIC18FXX8 defines this time to be 2 TQ. 8 TQ. A bit time of less than 8 TQ in length is not Thus, Phase Segment 2 must be at least 2 TQ long. ensured to operate correctly. DS41159D-page 234 2004 Microchip Technology Inc.
- 237. PIC18FXX8 19.8 Synchronization The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The To compensate for phase shifts between the oscillator phase error is defined in magnitude of TQ as follows: frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant • e = 0 if the edge lies within Sync_Seg. signal edge of the incoming signal. When an edge in • e > 0 if the edge lies before the sample point. the transmitted data is detected, the logic will compare • e < 0 if the edge lies after the sample point of the the location of the edge to the expected time previous bit. (Sync_Seg). The circuit will then adjust the values of If the magnitude of the phase error is less than or equal Phase Segment 1 and Phase Segment 2, as to the programmed value of the synchronization jump necessary. There are two mechanisms used for width, the effect of a resynchronization is the same as synchronization. that of a hard synchronization. 19.8.1 HARD SYNCHRONIZATION If the magnitude of the phase error is larger than the synchronization jump width and if the phase error is Hard synchronization is only done when there is a reces- positive, then Phase Segment 1 is lengthened by an sive to dominant edge during a bus Idle condition, indi- amount equal to the synchronization jump width. cating the start of a message. After hard synchronization, the bit time counters are restarted with If the magnitude of the phase error is larger than the Sync_Seg. Hard synchronization forces the edge which resynchronization jump width and if the phase error is has occurred to lie within the synchronization segment of negative, then Phase Segment 2 is shortened by an the restarted bit time. Due to the rules of synchroniza- amount equal to the synchronization jump width. tion, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 19.8.3 SYNCHRONIZATION RULES • Only one synchronization within one bit time is 19.8.2 RESYNCHRONIZATION allowed. As a result of resynchronization, Phase Segment 1 • An edge will be used for synchronization only if may be lengthened or Phase Segment 2 may be short- the value detected at the previous sample point ened. The amount of lengthening or shortening of the (previously read bus value) differs from the bus phase buffer segments has an upper bound given by value immediately after the edge. the Synchronization Jump Width (SJW). The value of • All other recessive to dominant edges, fulfilling the SJW will be added to Phase Segment 1 (see rules 1 and 2, will be used for resynchronization Figure 19-8) or subtracted from Phase Segment 2 (see with the exception that a node transmitting a Figure 19-9). The SJW is programmable between 1 TQ dominant bit will not perform a resynchronization and 4 TQ. as a result of a recessive to dominant edge with a Clocking information will only be derived from reces- positive phase error. sive to dominant transitions. The property, that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. FIGURE 19-8: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Prop Phase Phase Time Sync Segment Segment 1 ≤ SJW Segment 2 Segments TQ Sample Point Nominal Bit Length Actual Bit Length 2004 Microchip Technology Inc. DS41159D-page 235
- 238. PIC18FXX8 FIGURE 19-9: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Phase Phase Sync Segment Segment 1 Segment 2 ≤ SJW TQ Sample Point Actual Bit Length Nominal Bit Length 19.9 Programming Time Segments 19.11.1 BRGCON1 Some requirements for programming of the time The BRP bits control the baud rate prescaler. The segments: SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. • Prop Seg + Phase Seg 1 ≥ Phase Seg 2 • Phase Seg 2 ≥ Sync Jump Width 19.11.2 BRGCON2 For example, assume that a 125 kHz CAN baud rate is The PRSEG bits set the length of the Propagation Seg- desired using 20 MHz for FOSC. With a TOSC of 50 ns, ment in terms of TQ. The SEG1PH bits set the length of a baud rate prescaler value of 04h gives a TQ of 500 ns. Phase Segment 1 in TQ. The SAM bit controls how To obtain a nominal bit rate of 125 kHz, the nominal bit many times the RXCAN pin is sampled. Setting this bit time must be 8 µs or 16 TQ. to a ‘1’ causes the bus to be sampled three times; twice Using 1 TQ for the Sync Segment, 2 TQ for the Propa- at TQ/2 before the sample point and once at the normal gation Segment and 7 TQ for Phase Segment 1 would sample point (which is at the end of Phase Segment 1). place the sample point at 10 TQ after the transition. The value of the bus is determined to be the value read This leaves 6 TQ for Phase Segment 2. during at least two of the samples. If the SAM bit is set to a ‘0’, then the RXCAN pin is sampled only once at By the rules above, the Sync Jump Width could be the the sample point. The SEG2PHTS bit controls how the maximum of 4 TQ. However, normally a large SJW is length of Phase Segment 2 is determined. If this bit is only necessary when the clock generation of the differ- set to a ‘1’, then the length of Phase Segment 2 is ent nodes is inaccurate or unstable, such as using determined by the SEG2PH bits of BRGCON3. If the ceramic resonators. Typically, an SJW of 1 is enough. SEG2PHTS bit is set to a ‘0’, then the length of Phase Segment 2 is the greater of Phase Segment 1 and the 19.10 Oscillator Tolerance information processing time (which is fixed at 2 TQ for the PIC18FXX8). As a rule of thumb, the bit timing requirements allow ceramic resonators to be used in applications with 19.11.3 BRGCON3 transmission rates of up to 125 Kbit/sec. For the full bus speed range of the CAN protocol, a quartz oscillator is The PHSEG2<2:0> bits set the length (in TQ) of Phase required. A maximum node-to-node oscillator variation Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the of 1.7% is allowed. SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0> bits have no effect. 19.11 Bit Timing Configuration Registers The Configuration registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18FXX8 is in Configuration mode. DS41159D-page 236 2004 Microchip Technology Inc.
- 239. PIC18FXX8 19.12 Error Detection 19.12.6 ERROR STATES The CAN protocol provides sophisticated error detection Detected errors are made public to all other nodes via mechanisms. The following errors can be detected. error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon 19.12.1 CRC ERROR as possible. Furthermore, each CAN node is in one of the three error states “error-active”, “error-passive” or With the Cyclic Redundancy Check (CRC), the “bus-off” according to the value of the internal error transmitter calculates special check bits for the bit counters. The error-active state is the usual state, sequence, from the start of a frame until the end of the where the bus node can transmit messages and data field. This CRC sequence is transmitted in the activate error frames (made of dominant bits) without CRC field. The receiving node also calculates the CRC any restrictions. In the error-passive state, messages sequence using the same formula and performs a and passive error frames (made of recessive bits) may comparison to the received sequence. If a mismatch is be transmitted. The bus-off state makes it temporarily detected, a CRC error has occurred and an error frame impossible for the station to participate in the bus is generated. The message is repeated. communication. During this state, messages can neither be received nor transmitted. 19.12.2 ACKNOWLEDGE ERROR In the Acknowledge field of a message, the transmitter 19.12.7 ERROR MODES AND ERROR checks if the Acknowledge slot (which was sent out as COUNTERS a recessive bit) contains a dominant bit. If not, no other The PIC18FXX8 contains two error counters: the node has received the frame correctly. An Acknowl- Receive Error Counter (RXERRCNT) and the Transmit edge Error has occurred; an error frame is generated Error Counter (TXERRCNT). The values of both and the message will have to be repeated. counters can be read by the MCU. These counters are 19.12.3 FORM ERROR incremented or decremented in accordance with the CAN bus specification. If a node detects a dominant bit in one of the four segments, including end of frame, interframe space, The PIC18FXX8 is error-active if both error counters Acknowledge delimiter or CRC delimiter, then a Form are below the error-passive limit of 128. It is error- Error has occurred and an error frame is generated. passive if at least one of the error counters equals or The message is repeated. exceeds 128. It goes to bus-off if the transmit error counter equals or exceeds the bus-off limit of 256. The 19.12.4 BIT ERROR device remains in this state until the bus-off recovery sequence is received. The bus-off recovery sequence A Bit Error occurs if a transmitter sends a dominant bit consists of 128 occurrences of 11 consecutive and detects a recessive bit, or if it sends a recessive bit recessive bits (see Figure 19-10). Note that the CAN and detects a dominant bit, when monitoring the actual module, after going bus-off, will recover back to error- bus level and comparing it to the just transmitted bit. In active without any intervention by the MCU if the bus the case where the transmitter sends a recessive bit remains Idle for 128 x 11 bit times. If this is not desired, and a dominant bit is detected during the arbitration the error Interrupt Service Routine should address this. field and the Acknowledge slot, no Bit Error is The current error mode of the CAN module can be read generated because normal arbitration is occurring. by the MCU via the COMSTAT register. 19.12.5 STUFF BIT ERROR Additionally, there is an Error State Warning flag bit, EWARN, which is set if at least one of the error If, between the start of frame and the CRC delimiter, six counters equals or exceeds the error warning limit of consecutive bits with the same polarity are detected, 96. EWARN is reset if both error counters are less than the bit stuffing rule has been violated. A Stuff Bit Error the error warning limit. occurs and an error frame is generated. The message is repeated. 2004 Microchip Technology Inc. DS41159D-page 237
- 240. PIC18FXX8 FIGURE 19-10: ERROR MODES STATE DIAGRAM Reset Error- RXERRCNT < 127 or TXERRCNT < 127 Active 128 occurrences of 11 consecutive “recessive” bits RXERRCNT > 127 or TXERRCNT > 127 Error- Passive TXERRCNT > 255 Bus- Off 19.13 CAN Interrupts 19.13.1 INTERRUPT CODE BITS The module has several sources of interrupts. Each of The source of a pending interrupt is indicated in the these interrupts can be individually enabled or ICODE (Interrupt Code) bits of the CANSTAT register disabled. The CANINTF register contains interrupt (ICODE<2:0>). Interrupts are internally prioritized such flags. The CANINTE register contains the enables for that the higher priority interrupts are assigned lower the 8 main interrupts. A special set of read-only bits in ICODE values. Once the highest priority interrupt con- the CANSTAT register, the ICODE bits, can be used in dition has been cleared, the code for the next highest combination with a jump table for efficient handling of priority interrupt that is pending (if any) will be reflected interrupts. by the ICODE bits (see Table 19-3, following page). Note that only those interrupt sources that have their All interrupts have one source, with the exception of the associated CANINTE enable bit set will be reflected in error interrupt. Any of the error interrupt sources can set the ICODE bits. the error interrupt flag. The source of the error interrupt can be determined by reading the Communication 19.13.2 TRANSMIT INTERRUPT Status register, COMSTAT. When the transmit interrupt is enabled, an interrupt will The interrupts can be broken up into two categories: be generated when the associated transmit buffer receive and transmit interrupts. becomes empty and is ready to be loaded with a new The receive related interrupts are: message. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the • Receive Interrupts MCU resetting the TXBnIF bit to a ‘0’. • Wake-up Interrupt • Receiver Overrun Interrupt 19.13.3 RECEIVE INTERRUPT • Receiver Warning Interrupt When the receive interrupt is enabled, an interrupt will • Receiver Error-Passive Interrupt be generated when a message has been successfully The transmit related interrupts are: received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving • Transmit Interrupts the EOF field. The RXBnIF bit will be set to indicate the • Transmitter Warning Interrupt source of the interrupt. The interrupt is cleared by the • Transmitter Error-Passive Interrupt MCU resetting the RXBnIF bit to a ‘0’. • Bus-Off Interrupt DS41159D-page 238 2004 Microchip Technology Inc.
- 241. PIC18FXX8 TABLE 19-3: VALUES FOR ICODE<2:0> 19.13.6 ERROR INTERRUPT ICOD When the error interrupt is enabled, an interrupt is Interrupt Boolean Expression <2:0> generated if an overflow condition occurs or if the error state of transmitter or receiver has changed. The error ERR•WAK•TX0•TX1•TX2•RX0• flags in COMSTAT will indicate one of the following 000 None RX1 conditions. 001 Error ERR 19.13.6.1 Receiver Overflow 010 TXB2 ERR•TX0•TX1•TX2 An overflow condition occurs when the MAB has assembled a valid received message (the message 011 TXB1 ERR•TX0•TX1 meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available 100 TXB0 ERR•TX0 for loading of a new message. The associated COMSTAT.RXnOVFL bit will be set to indicate the 101 RXB1 ERR•TX0•TX1•TX2•RX0•RX1 overflow condition. This bit must be cleared by the MCU. 110 RXB0 ERR•TX0•TX1•TX2•RX0 19.13.6.2 Receiver Warning Wake on ERR•TX0•TX1•TX2•RX0•RX1• 111 The receive error counter has reached the MCU Interrupt WAK warning limit of 96. Key: ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE 19.13.6.3 Transmitter Warning TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE The transmit error counter has reached the MCU TX2 = TXB2IF * TXB2IE warning limit of 96. 19.13.6.4 Receiver Bus Passive 19.13.4 MESSAGE ERROR INTERRUPT The receive error counter has exceeded the error- passive limit of 127 and the device has gone to When an error occurs during transmission or reception error-passive state. of a message, the message error flag IRXIF will be set and if the IRXIE bit is set, an interrupt will be generated. 19.13.6.5 Transmitter Bus Passive This is intended to be used to facilitate baud rate determination when used in conjunction with Listen The transmit error counter has exceeded the error- Only mode. passive limit of 127 and the device has gone to error-passive state. 19.13.5 BUS ACTIVITY WAKE-UP INTERRUPT 19.13.6.6 Bus-Off When the PIC18FXX8 is in Sleep mode and the bus The transmit error counter has exceeded 255 and the activity wake-up interrupt is enabled, an interrupt will be device has gone to bus-off state. generated and the WAKIF bit will be set when activity is detected on the CAN bus. This interrupt causes the 19.13.7 INTERRUPT ACKNOWLEDGE PIC18FXX8 to exit Sleep mode. The interrupt is reset Interrupts are directly associated with one or more by the MCU, clearing the WAKIF bit. status flags in the PIR register. Interrupts are pending as long as one of the flags is set. Once an interrupt flag is set by the device, the flag cannot be reset by the microcontroller until the interrupt condition is removed. 2004 Microchip Technology Inc. DS41159D-page 239
- 242. PIC18FXX8 NOTES: DS41159D-page 240 2004 Microchip Technology Inc.
- 243. PIC18FXX8 20.0 COMPATIBLE 10-BIT ANALOG- The A/D module has four registers. These registers are: TO-DIGITAL CONVERTER (A/D) • A/D Result High Register (ADRESH) MODULE • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) The Analog-to-Digital (A/D) Converter module has five • A/D Control Register 1 (ADCON1) inputs for the PIC18F2X8 devices and eight for the PIC18F4X8 devices. This module has the ADCON0 The ADCON0 register, shown in Register 20-1, and ADCON1 register definitions that are compatible controls the operation of the A/D module. The with the PICmicro® mid-range A/D module. ADCON1 register, shown in Register 20-2, configures the functions of the port pins. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5)(1) 110 = Channel 6 (AN6)(1) 111 = Channel 7 (AN7)(1) Note 1: These channels are unimplemented on PIC18F2X8 (28-pin) devices. Do not select any unimplemented channel. bit 2 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress bit 1 Unimplemented: Read as ‘0’ bit 0 ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 241
- 244. PIC18FXX8 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’. bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R 0000 A A A A A A A A VDD VSS 8/0 0001 A A A A VREF+ A A A AN3 VSS 7/1 0010 D D D A A A A A VDD VSS 5/0 0011 D D D A VREF+ A A A AN3 VSS 4/1 0100 D D D D A D A A VDD VSS 3/0 0101 D D D D VREF+ D A A AN3 VSS 2/1 011x D D D D D D D D — — 0/0 1000 A A A A VREF+ VREF- A A AN3 AN2 6/2 1001 D D A A A A A A VDD VSS 6/0 1010 D D A A VREF+ A A A AN3 VSS 5/1 1011 D D A A VREF+ VREF- A A AN3 AN2 4/2 1100 D D D A VREF+ VREF- A A AN3 AN2 3/2 1101 D D D D VREF+ VREF- A A AN3 AN2 2/2 1110 D D D D D D D A VDD VSS 1/0 1111 D D D D VREF+ VREF- D A AN3 AN2 1/2 A = Analog input D = Digital I/O C/R = # of analog input channels/# of A/D voltage references Note: Shaded cells indicate channels available only on PIC18F4X8 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx) are forced to be analog inputs. DS41159D-page 242 2004 Microchip Technology Inc.
- 245. PIC18FXX8 The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS) or the voltage level on the RA3/AN3/ conversion is aborted. VREF+ pin and RA2/AN2/VREF- pin. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input (RA3 can also be a to operate while the device is in Sleep mode. To oper- voltage reference) or as a digital I/O. ate in Sleep, the A/D conversion clock must be derived The ADRESH and ADRESL registers contain the result from the A/D’s internal RC oscillator. of the A/D conversion. When the A/D conversion is com- The output of the sample and hold is the input into the plete, the result is loaded into the ADRESH/ADRESL converter which generates the result via successive registers, the GO/DONE bit (ADCON0<2>) is cleared approximation. and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 20-1. FIGURE 20-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 AN7(1) 110 AN6(1) 101 AN5(1) 100 AN4 VAIN (Input Voltage) 011 AN3 010 10-bit AN2 Converter A/D 001 AN1 PCFG0 000 VDD AN0 VREF+ Reference voltage VREF- VSS Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices. 2: All I/O pins have diode protection to VDD and VSS. 2004 Microchip Technology Inc. DS41159D-page 243
- 246. PIC18FXX8 The value that is in the ADRESH/ADRESL registers is 6. Read A/D Result registers (ADRESH/ADRESL); not modified for a Power-on Reset. The ADRESH/ clear bit ADIF if required. ADRESL registers will contain unknown data after a 7. For next conversion, go to step 1 or step 2 as Power-on Reset. required. The A/D conversion time per bit is After the A/D module has been configured as desired, defined as TAD. A minimum wait of 2 TAD is the selected channel must be acquired before the required before next acquisition starts. conversion is started. The analog input channels must have their corresponding TRIS bits selected as an 20.1 A/D Acquisition Requirements input. To determine acquisition time, see Section 20.1 “A/D Acquisition Requirements”. After this acquisi- For the A/D converter to meet its specified accuracy, tion time has elapsed, the A/D conversion can be the charge holding capacitor (CHOLD) must be allowed started. The following steps should be followed for to fully charge to the input channel voltage level. The doing an A/D conversion: analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling 1. Configure the A/D module: switch (RSS) impedance directly affect the time • Configure analog pins, voltage reference and required to charge the capacitor CHOLD. The sampling digital I/O (ADCON1) switch (RSS) impedance varies over the device voltage • Select A/D input channel (ADCON0) (VDD). The source impedance affects the offset voltage • Select A/D conversion clock (ADCON0) at the analog input (due to pin leakage current). The maximum recommended impedance for analog • Turn on A/D module (ADCON0) sources is 2.5 kΩ. After the analog input channel is 2. Configure A/D interrupt (if desired): selected (changed), this acquisition must be done • Clear ADIF bit before the conversion can be started. • Set ADIE bit Note: When the conversion is started, the • Set GIE bit holding capacitor is disconnected from the 3. Wait the required acquisition time. input pin. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt FIGURE 20-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V ANx RIC ≤ 1k SS RSS Rs CPIN I LEAKAGE VAIN CHOLD = 120 pF 5 pF VT = 0.6V ± 500 nA VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 8 9 10 11 Sampling Switch (kΩ) DS41159D-page 244 2004 Microchip Technology Inc.
- 247. PIC18FXX8 To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 20-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: • CHOLD = 120 pF • Rs = 2.5 kΩ • Conversion Error ≤ 1/2 LSb • VDD = 5V → Rss = 7 kΩ • Temperature = 50°C (system max.) • VHOLD = 0V @ time = 0 EQUATION 20-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 20-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))) or Tc = -(120 pF)(1 kΩ + RSS + RS) ln(1/2047) EXAMPLE 20-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25°C. TACQ = 2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885) -120 pF (10.5 kΩ) ln(0.0004885) -1.26 µs (-7.6241) 9.61 µs TACQ = 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)] 11.61 µs + 1.25 µs 12.86 µs Note: When using external voltage references with the A/D converter, the source impedance of the external voltage references must be less than 20Ω to obtain the specified A/D resolution. Higher reference source impedances will increase both offset and gain errors. Resistive voltage dividers will not provide a sufficiently low source impedance. To maintain the best possible performance in A/D conversions, external VREF inputs should be buffered with an operational amplifier or other low output impedance circuit. 2004 Microchip Technology Inc. DS41159D-page 245
- 248. PIC18FXX8 20.2 Selecting the A/D Conversion 20.3 Configuring Analog Port Pins Clock The ADCON1, TRISA and TRISE registers control the The A/D conversion time per bit is defined as TAD. The operation of the A/D port pins. The port pins that are A/D conversion requires 12 TAD per 10-bit conversion. desired as analog inputs must have their corresponding The source of the A/D conversion clock is software TRIS bits set (input). If the TRIS bit is cleared (output), selectable. The seven possible options for TAD are: the digital output level (VOH or VOL) will be converted. • 2 TOSC The A/D operation is independent of the state of the • 4 TOSC CHS2:CHS0 bits and the TRIS bits. • 8 TOSC Note 1: When reading the port register, all pins • 16 TOSC configured as analog input channels will • 32 TOSC read as cleared (a low level). Pins config- ured as digital inputs will convert an • 64 TOSC analog input. Analog levels on a digitally • Internal RC oscillator. configured input will not affect the For correct A/D conversions, the A/D conversion clock conversion accuracy. (TAD) must be selected to ensure a minimum TAD time 2: Analog levels on any pin that is defined as of 1.6 µs. a digital input (including the AN4:AN0 Table 20-1 shows the resultant TAD times derived from pins) may cause the input buffer to the device operating frequencies and the A/D clock consume current that is out of the source selected. device’s specification. TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Device Frequency Operation ADCS2:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz 2 TOSC 000 100 ns(2) 400 ns(2) 1.6 µs 6 µs 4 TOSC 100 200 ns(2) 800 ns(2) 3.2 µs 12 µs 8 TOSC 001 400 ns(2) 1.6 µs 6.4 µs 24 µs(3) 16 TOSC 101 800 ns(2) 3.2 µs 12.8 µs 48 µs(3) 32 TOSC 010 1.6 µs 6.4 µs 25.6 µs(3) 96 µs(3) 64 TOSC 110 3.2 µs 12.8 µs 51.2 µs(3) 192 µs(3) RC 011 2-6 µs(1) 2-6 µs(1) 2-6 µs(1) 2-6 µs(1) Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical TAD time of 4 µs. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. TABLE 20-2: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LF DEVICES) AD Clock Source (TAD) Device Frequency Operation ADCS2:ADCS0 4 MHz 2 MHz 1.25 MHz 333.33 kHz 2 TOSC 000 500 ns(2) 1.0 µs(2) 1.6 µs(2) 6 µs 4 TOSC 100 1.0 µs(2) 2.0 µs(2) 3.2 µs(2) 12 µs 8 TOSC 001 2.0 µs(2) 4.0 µs 6.4 µs 24 µs(3) 16 TOSC 101 4.0 µs(2) 8.0 µs 12.8 µs 48 µs(3) 32 TOSC 010 8.0 µs 16.0 µs 25.6 µs(3) 96 µs(3) 64 TOSC 110 16.0 µs 32.0 µs 51.2 µs(3) 192 µs(3) (1) (1) (1) RC 011 3-9 µs 3-9 µs 3-9 µs 3-9 µs(1) Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical TAD time of 6 µs. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. DS41159D-page 246 2004 Microchip Technology Inc.
- 249. PIC18FXX8 20.4 A/D Conversions 20.4.1 A/D RESULT REGISTERS Figure 20-4 shows the operation of the A/D converter The ADRESH:ADRESL register pair is the location after the GO bit has been set. Clearing the GO/DONE where the 10-bit A/D result is loaded at the completion bit during a conversion will abort the current conver- of the A/D conversion. This register pair is 16 bits wide. sion. The A/D Result register pair will not be updated The A/D module gives the flexibility to left or right justify with the partially completed A/D conversion sample. the 10-bit result in the 16-bit result register. The A/D That is, the ADRESH:ADRESL registers will continue Format Select bit (ADFM) controls this justification. to contain the value of the last completed conversion Figure 20-3 shows the operation of the A/D result justi- (or the last value written to the ADRESH:ADRESL fication. The extra bits are loaded with ‘0’s. When an registers). After the A/D conversion is aborted, a 2 TAD A/D result will not overwrite these locations (A/D wait is required before the next acquisition is started. disable), these registers may be used as two general After this 2 TAD wait, acquisition on the selected purpose 8-bit registers. channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 20-3: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2107 0 7 0765 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified 2004 Microchip Technology Inc. DS41159D-page 247
- 250. PIC18FXX8 20.5 Use of the ECCP Trigger acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The An A/D conversion can be started by the “special event appropriate analog input channel must be selected and trigger” of the ECCP module. This requires that the the minimum acquisition done before the “special event ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro- trigger” sets the GO/DONE bit (starts a conversion). grammed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ If the A/D module is not enabled (ADON is cleared), the DONE bit will be set, starting the A/D conversion and the “special event trigger” will be ignored by the A/D module Timer1 (or Timer3) counter will be reset to zero. Timer1 but will still reset the Timer1 (or Timer3) counter. (or Timer3) is reset to automatically repeat the A/D FIGURE 20-4: A/D CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. TABLE 20-3: SUMMARY OF A/D REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u (1) PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 — CMIF(1) — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000 PIE2 — CMIE(1) — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000 IPR2 — CMIP(1) — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111 ADRESH A/D Result Register xxxx xxxx uuuu uuuu ADRESL A/D Result Register xxxx xxxx uuuu uuuu ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 TRISA — PORTA Data Direction Register -111 1111 -111 1111 PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -000 LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear. DS41159D-page 248 2004 Microchip Technology Inc.
- 251. PIC18FXX8 21.0 COMPARATOR MODULE The CMCON register, shown in Register 21-1, controls the comparator input and output multiplexers. A block Note: The analog comparators are only diagram of the comparator is shown in Figure 21-1. available on the PIC18F448 and PIC18F458. The comparator module contains two analog com- parators. The inputs to the comparators are multiplexed with the RD0 through RD3 pins. The on-chip voltage reference (Section 22.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RD0/PSP0 C2 VIN- connects to RD2/PSP2 0 = C1 VIN- connects to RD1/PSP1 C2 VIN- connects to RD3/PSP3 bit 2-0 CM2:CM0: Comparator Mode bits Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 249
- 252. PIC18FXX8 21.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section 27.0 “Electrical Characteristics”. tors. The CMCON register is used to select these modes. Figure 21-1 shows the eight possible modes. Note: Comparator interrupts should be disabled The TRISD register controls the data direction of the during a Comparator mode change; comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur. FIGURE 21-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM2:CM0 = 000 CM2:CM0 = 111 A VIN- D VIN- RD1/PSP1 RD1/PSP1 VIN+ C1 Off (Read as ‘0’) VIN+ C1 Off (Read as ‘0’) RD0/PSP0 A RD0/PSP0 D A VIN- D VIN- RD3/PSP3 RD3/PSP3 VIN+ C2 Off (Read as ‘0’) VIN+ C2 Off (Read as ‘0’) RD2/PSP2 A RD2/PSP2 D Two Independent Comparators with Outputs Two Independent Comparators CM2:CM0 = 011 CM2:CM0 = 010 A VIN- A VIN- RD1/PSP1 RD1/PSP1 A VIN+ C1 C1OUT VIN+ C1 C1OUT RD0/PSP0 RD0/PSP0 A RE1/AN6/WR/C1OUT A VIN- RD3/PSP3 A VIN- RD3/PSP3 A VIN+ C2 C2OUT C2OUT RD2/PSP2 A VIN+ C2 RD2/PSP2 RE2/AN7/CS/C2OUT Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 A VIN- A VIN- RD1/PSP1 RD1/PSP1 VIN+ C1 C1OUT VIN+ C1 C1OUT RD0/PSP0 A RD0/PSP0 A RE1/AN6/WR/ C1OUT A VIN- RD3/PSP3 C2 C2OUT A VIN- RD2/PSP2 D VIN+ RD3/PSP3 VIN+ C2 C2OUT RD2/PSP2 D RE2/AN7/CS/C2OUT One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 A VIN- A RD1/PSP1 RD1/PSP1 CIS = 0 VIN- VIN+ C1 C1OUT RD0/PSP0 A CIS = 1 RD0/PSP0 A VIN+ C1 C1OUT RE1/AN6/WR/C1OUT A RD3/PSP3 VIN- CIS = 0 RD2/PSP2 A CIS = 1 C2 C2OUT D VIN- VIN+ RD3/PSP3 VIN+ C2 Off (Read as ‘0’) RD2/PSP2 D CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch DS41159D-page 250 2004 Microchip Technology Inc.
- 253. PIC18FXX8 21.2 Comparator Operation 21.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 21-2 along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference for the compara- the digital output. When the analog input at VIN+ is less tors. Section 22.0 “Comparator Voltage Reference than the analog input VIN-, the output of the comparator Module” contains a detailed description of the module is a digital low level. When the analog input at VIN+ is that provides this signal. The internal reference signal is greater than the analog input VIN-, the output of the used when comparators are in mode CM<2:0> = 110 comparator is a digital high level. The shaded areas of (Figure 21-1). In this mode, the internal voltage the output of the comparator in Figure 21-2 represent reference is applied to the VIN+ pin of both comparators. the uncertainty due to input offsets and response time. 21.4 Comparator Response Time 21.3 Comparator Reference Response time is the minimum time, after selecting a An external or internal reference signal may be used new reference voltage or input source, before the depending on the comparator operating mode. The comparator output has a valid level. If the internal ref- analog signal present at VIN- is compared to the signal erence is changed, the maximum delay of the internal at VIN+ and the digital output of the comparator is voltage reference must be considered when using the adjusted accordingly (Figure 21-2). comparator outputs. Otherwise, the maximum delay of the comparators should be used (Section 27.0 “Electrical Characteristics”). FIGURE 21-2: SINGLE COMPARATOR 21.5 Comparator Outputs VIN+ + The comparator outputs are read through the CMCON Output register. These bits are read-only. The comparator VIN- - outputs may also be directly output to the RE1 and RE2 I/O pins. When enabled, multiplexors in the output path of the RE1 and RE2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and VININ– V- the response time given in the specifications. VIN+ VIN+ Figure 21-3 shows the comparator output block diagram. The TRISE bits will still function as an output enable/ Output disable for the RE1 and RE2 pins while in this mode. Output The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the Port register, all pins 21.3.1 EXTERNAL REFERENCE SIGNAL configured as analog inputs will read as a When external voltage references are used, the ‘0’. Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input according to the parators operate from the same or different reference Schmitt Trigger input specification. sources. However, threshold detector applications may 2: Analog levels on any pin defined as a dig- require the same reference. The reference signal must ital input may cause the input buffer to be between VSS and VDD and can be applied to either consume more current than is specified. pin of the comparator(s). 2004 Microchip Technology Inc. DS41159D-page 251
- 254. PIC18FXX8 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + - CxINV To RE1 or RE2 pin Bus Q D Data Read CMCON EN Set CMIF Q D bit From Other EN Comparator CL Read CMCON Reset 21.6 Comparator Interrupts Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a The comparator interrupt flag is set whenever there is read operation is being executed (start of a change in the output value of either comparator. the Q2 cycle), then the CMIF (PIR2 Software will need to maintain information about the register) interrupt flag may not get set. status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF The user, in the Interrupt Service Routine, can clear the bit (PIR2 register) is the Comparator Interrupt Flag. The interrupt in the following manner: CMIF bit must be reset by clearing ‘0’. Since it is also a) Any read or write of CMCON will end the possible to write a ‘1’ to this register, a simulated mismatch condition. interrupt may be initiated. b) Clear flag bit CMIF. The CMIE bit (PIE2 register) and the PEIE bit (INTCON A mismatch condition will continue to set flag bit CMIF. register) must be set to enable the interrupt. In addition, Reading CMCON will end the mismatch condition and the GIE bit must also be set. If any of these bits are allow flag bit CMIF to be cleared. clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. DS41159D-page 252 2004 Microchip Technology Inc.
- 255. PIC18FXX8 21.7 Comparator Operation During 21.8 Effects of a Reset Sleep A device Reset forces the CMCON register to its Reset When a comparator is active and the device is placed state, causing the comparator module to be in the in Sleep mode, the comparator remains active and the Comparator Reset mode, CM<2:0> = 000. This interrupt is functional if enabled. This interrupt will ensures that all potential inputs are analog inputs. wake-up the device from Sleep mode when enabled. Device current is minimized when analog inputs are While the comparator is powered up, higher Sleep present at Reset time. The comparators will be currents than shown in the power-down current powered down during the Reset interval. specification will occur. Each operational comparator will consume additional current, as shown in the com- 21.9 Analog Input Connection parator specifications. To minimize power consumption Considerations while in Sleep mode, turn off the comparators, CM<2:0> = 111, before entering Sleep. If the device A simplified circuit for an analog input is shown in wakes up from Sleep, the contents of the CMCON Figure 21-4. Since the analog pins are connected to a register are not affected. digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 21-4: ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC AIN CPIN I LEAKAGE VA VT = 0.6V ±500 nA 5 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage I LEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage 2004 Microchip Technology Inc. DS41159D-page 253
- 256. PIC18FXX8 TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR2 — CMIF(1) — EEIF BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000 PIE2 — CMIE(1) — EEIE BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000 (1) IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -000 LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu TRISE IBF(1) OBF(1) IBOV(1) PSPMODE(1) — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’ Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear. DS41159D-page 254 2004 Microchip Technology Inc.
- 257. PIC18FXX8 22.0 COMPARATOR VOLTAGE 22.1 Configuring the Comparator REFERENCE MODULE Voltage Reference Note: The comparator voltage reference is only The comparator voltage reference can output 16 distinct available on the PIC18F448 and voltage levels for each range. The equations used to PIC18F458. calculate the output of the comparator voltage reference are as follows. This module is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor EQUATION 22-1: ladder is segmented to provide two ranges of CVREF If CVRR = 1: values and has a power-down function to conserve CVREF = (CVR<3:0>/24) x CVRSRC power when the reference is not being used. The where: CVRCON register controls the operation of the CVRSS = 1, CVRSRC = (VREF+) – (VREF-) reference, as shown in Register 22-1. The block CVRSS = 0, CVRSRC = AVDD – AVSS diagram is shown in Figure 22-1. The comparator and reference supply voltage can EQUATION 22-2: come from either VDD and VSS, or the external VREF+ If CVRR = 0: and VREF-, that are multiplexed with RA3 and RA2. The CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC comparator reference supply voltage is controlled by the CVRSS bit. where: CVRSS = 1, CVRSRC = (VREF+) – (VREF-) CVRSS = 0, CVRSRC = AVDD – AVSS The settling time of the Comparator Voltage Reference must be considered when changing the RA0/AN0/ CVREF output (see Table 27-4 in Section 27.2 “DC Characteristics”). REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin 0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits When CVRR = 1: CVREF = (CVR3:CVR0/24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 255
- 258. PIC18FXX8 FIGURE 22-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 1 CVRSS = 0 16 Stages CVREN 8R R R R R CVRR 8R CVRSS = 1 CVRSS = 0 RA2/AN2/VREF- CVR3 RA0/AN0/CVREF 16-to-1 Analog MUX (From CVRCON<3:0>) or CVREF of Comparator CVR0 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit CVREN (CVRCON register). This Reset on the top and bottom of the resistor ladder network also disconnects the reference from the RA2 pin by (Figure 22-1) keep VREF from approaching the refer- clearing bit CVROE (CVRCON register) and selects the ence source rails. The voltage reference is derived high-voltage range by clearing bit CVRR (CVRCON from the reference source; therefore, the VREF output register). The CVRSS value select bits, CVRCON<3:0>, changes with fluctuations in that source. The absolute are also cleared. accuracy of the voltage reference can be found in Section 27.0 “Electrical Characteristics”. 22.5 Connection Considerations 22.3 Operation During Sleep The voltage reference module operates independently of the comparator module. The output of the reference When the device wakes up from Sleep through an generator may be connected to the RA0/AN0 pin if the interrupt or a Watchdog Timer time-out, the contents of TRISA<0> bit is set and the CVROE bit (CVRCON<6>) the CVRCON register are not affected. To minimize is set. Enabling the voltage reference output onto the current consumption in Sleep mode, the voltage RA0/AN0 pin, with an input signal present, will increase reference should be disabled. current consumption. Connecting RA0/AN0 as a digital output, with CVRSS enabled, will also increase current consumption. The RA0/AN0 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 22-2 shows an example buffering technique. DS41159D-page 256 2004 Microchip Technology Inc.
- 259. PIC18FXX8 FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) RA0/AN0 CVREF Module • + • CVREF Output – Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration CVRCON<3:0> and CVRCON<5>. TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TRISA — TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. 2004 Microchip Technology Inc. DS41159D-page 257
- 260. PIC18FXX8 NOTES: DS41159D-page 258 2004 Microchip Technology Inc.
- 261. PIC18FXX8 23.0 LOW-VOLTAGE DETECT Figure 23-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage In many applications, the ability to determine if the decreases. When the device voltage equals voltage VA, device voltage (VDD) is below a specified voltage level the LVD logic generates an interrupt. This occurs at is a desirable feature. A window of operation for the time TA. The application software then has the time, application can be created, where the application until the device voltage is no longer in valid operating software can do “housekeeping tasks” before the range, to shutdown the system. Voltage point VB is the device voltage exits the valid operating range. This can minimum valid operating voltage specification. This be done using the Low-Voltage Detect module. occurs at time TB. The difference TB – TA is the total This module is a software programmable circuitry, time for shutdown. where a device voltage trip point can be specified. The block diagram for the LVD module is shown in When the voltage of the device becomes lower than the Figure 23-2. A comparator uses an internally gener- specified point, an interrupt flag is set. If the interrupt is ated reference voltage as the set point. When the enabled, the program execution will branch to the selected tap output of the device voltage crosses the interrupt vector address and the software can then set point (is lower than), the LVDIF bit is set. respond to that interrupt source. Each node in the resistor divider represents a “trip point” The Low-Voltage Detect circuitry is completely under voltage. The “trip point” voltage is the minimum supply software control. This allows the circuitry to be “turned voltage level at which the device can operate before the off” by the software which minimizes the current LVD module asserts an interrupt. When the supply consumption for the device. voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal, setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 23-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). FIGURE 23-1: TYPICAL LOW-VOLTAGE DETECT APPLICATION VA VB Voltage Legend: VA = LVD trip point VB = Minimum valid device operating voltage TA TB Time 2004 Microchip Technology Inc. DS41159D-page 259
- 262. PIC18FXX8 FIGURE 23-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVDL3:LVDL0 LVDCON Register 16-to-1 MUX LVDIF LVDEN Internally Generated Reference Voltage, 1.2V Typical The LVD module has an additional feature that allows The other input is connected to the internally generated the user to supply the trip voltage to the module from an voltage reference (parameter #D423 in Section 27.2 external source. This mode is enabled when bits “DC Characteristics”). This gives users flexibility, LVDL3:LVDL0 are set to ‘1111’. In this state, the com- because it allows them to configure the Low-Voltage parator input is multiplexed from the external input pin Detect interrupt to occur at any voltage in the valid LVDIN to one input of the comparator (Figure 23-3). operating range. FIGURE 23-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVDL3:LVDL0 LVDCON Register 16-to-1 MUX LVDIN LVDEN Externally Generated Trip Point LVD VxEN BODEN EN BGAP DS41159D-page 260 2004 Microchip Technology Inc.
- 263. PIC18FXX8 23.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry. REGISTER 23-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.45V min.-4.83V max. 1101 = 4.16V min.-4.5V max. 1100 = 3.96V min.-4.2V max. 1011 = 3.76V min.-4.08V max. 1010 = 3.57V min.-3.87V max. 1001 = 3.47V min.-3.75V max. 1000 = 3.27V min.-3.55V max. 0111 = 2.98V min.-3.22V max. 0110 = 2.77V min.-3.01V max. 0101 = 2.67V min.-2.89V max. 0100 = 2.48V min.-2.68V max. 0011 = 2.37V min.-2.57V max. 0010 = 2.18V min.-2.36V max. 0001 = 1.98V min.-2.14V max. 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS41159D-page 261
- 264. PIC18FXX8 23.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This 1. Write the value to the LVDL3:LVDL0 bits means that the LVD module does not need to be (LVDCON register) which selects the desired constantly operating. To decrease the current require- LVD trip point. ments, the LVD circuitry only needs to be enabled for 2. Ensure that LVD interrupts are disabled (the short periods where the voltage is checked. After doing LVDIE bit is cleared or the GIE bit is cleared). the check, the LVD module may be disabled. 3. Enable the LVD module (set the LVDEN bit in Each time that the LVD module is enabled, the circuitry the LVDCON register). requires some time to stabilize. After the circuitry has 4. Wait for the LVD module to stabilize (the IRVST stabilized, all status flags may be cleared. The module bit to become set). will then indicate the proper state of the system. 5. Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure 23-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 23-4: LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated TIRVST Reference Stable LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated TIRVST Reference Stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS41159D-page 262 2004 Microchip Technology Inc.
- 265. PIC18FXX8 23.2.1 REFERENCE VOLTAGE SET POINT 23.3 Operation During Sleep The internal reference voltage of the LVD module may be When enabled, the LVD circuitry continues to operate used by other internal circuitry (the Programmable during Sleep. If the device voltage crosses the trip Brown-out Reset). If these circuits are disabled (lower point, the LVDIF bit will be set and the device will wake- current consumption), the reference voltage circuit up from Sleep. Device execution will continue from the requires a time to become stable before a low-voltage interrupt vector address if interrupts have been globally condition can be reliably detected. This time is invariant enabled. of system clock speed. This start-up time is specified in electrical specification parameter #36. The low-voltage 23.4 Effects of a Reset interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 23-4. A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off. 23.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static cur- rent. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 2004 Microchip Technology Inc. DS41159D-page 263
- 266. PIC18FXX8 NOTES: DS41159D-page 264 2004 Microchip Technology Inc.
- 267. PIC18FXX8 24.0 SPECIAL FEATURES OF Sleep mode is designed to offer a very Low-Current Power-Down mode. The user can wake-up from Sleep THE CPU through external Reset, Watchdog Timer wake-up or There are several features intended to maximize through an interrupt. Several oscillator options are also system reliability, minimize cost through elimination of made available to allow the part to fit the application. external components, provide power-saving operating The RC oscillator option saves system cost while the modes and offer code protection. These are: LP crystal option saves power. A set of configuration bits is used to select various options. • Oscillator Selection • Reset 24.1 Configuration Bits - Power-on Reset (POR) - Power-up Timer (PWRT) The configuration bits can be programmed (read as ‘0’) - Oscillator Start-up Timer (OST) or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting - Brown-out Reset (BOR) at program memory location 300000h. • Interrupts The user will note that address 300000h is beyond the • Watchdog Timer (WDT) user program memory space. In fact, it belongs to the • Sleep configuration memory space (300000h-3FFFFFh) • Code Protection which can only be accessed using table reads and • ID Locations table writes. • In-Circuit Serial Programming Programming the Configuration registers is done in a All PIC18FXX8 devices have a Watchdog Timer which manner similar to programming the Flash memory. The is permanently enabled via the configuration bits or EECON1 register WR bit starts a self-timed write to the software controlled. It runs off its own RC oscillator for Configuration register. In normal operation mode, a added reliability. There are two timers that offer TBLWT instruction, with the TBLPTR pointed to the necessary delays on power-up. One is the Oscillator Configuration register, sets up the address and the Start-up Timer (OST), intended to keep the chip in data for the Configuration register write. Setting the WR Reset until the crystal oscillator is stable. The other is bit starts a long write to the Configuration register. The the Power-up Timer (PWRT) which provides a fixed Configuration registers are written a byte at a time. To delay on power-up only, designed to keep the part in write or erase a configuration cell, a TBLWT instruction Reset while the power supply stabilizes. With these two can write a ‘1’ or a ‘0’ into the cell. timers on-chip, most applications need no external Reset circuitry. TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111 300002h CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (1) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1000 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: See Register 24-11 for DEVID1 values. 2004 Microchip Technology Inc. DS41159D-page 265
- 268. PIC18FXX8 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 — — OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/OSC2 configured as RA6 110 = HS oscillator with PLL enabled/clock frequency = (4 x FOSC) 101 = EC oscillator w/OSC2 configured as RA6 100 = EC oscillator w/OSC2 configured as divide-by-4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS41159D-page 266 2004 Microchip Technology Inc.
- 269. PIC18FXX8 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 Note: The Watchdog Timer postscale select bits configuration used in the PIC18FXXX devices has changed from the configuration used in the PIC18CXXX devices. bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-4: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-Voltage ICSP enabled 0 = Low-Voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause Reset 0 = Stack Full/Underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state 2004 Microchip Technology Inc. DS41159D-page 267
- 270. PIC18FXX8 REGISTER 24-5: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code-protected 0 = Block 2 (004000-005FFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code-protected 0 = Block 1 (002000-003FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000200-001FFFh) not code-protected 0 = Block 0 (000200-001FFFh) code-protected Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-6: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code-protected 0 = Boot Block (000000-0001FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS41159D-page 268 2004 Microchip Technology Inc.