5 Clock Tree Design Techniques to Optimize SerDes Performance for Networking and Data Centers
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The document discusses five clock tree design techniques to enhance the performance of high-speed serpentine data rates ranging from 10 to 56 Gbps in networking and data center applications. It highlights key timing requirements, jitter and phase noise considerations, and the challenges of optimizing clock tree designs for performance, cost, and size. Additionally, it provides guidelines for defining clock trees, managing power supply noise, and selecting appropriate timing devices to meet specific jitter and phase noise specifications.
![Si5345/44/42 Any-Frequency Jitter Attenuators
Optical networking
Wireless infrastructure
ANY input frequency to ANY combination of output frequencies
100 fs (int); 150 fs (frac) RMS phase jitter [12kHz -20MHz]
Jitter/wander attenuation down to 0.1 Hz
Automatic hitless input switching
Free-run, locked, holdover; status monitoring: LOL, LOS, OOF
DCO mode: 0.001 ppb step resolution
DSPLL
IN0
IN_SEL
IN1
IN2
IN3/
FB_IN
÷FRAC
÷FRAC
÷FRAC
÷FRAC
XTAL
XBXA
OSC
Optional
External
Feedback
Multi
Synth
OUT0÷INT
OUT1÷INT
OUT2÷INT
OUT3÷INT
OUT4÷INT
OUT5÷INT
OUT6÷INT
OUT7÷INT
OUT8÷INT
OUT9÷INT
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Si5344
Si5342
Si5345
NVM
I2
C/SPI
Control/
Status
Part Number
Clock Inputs/
Outputs
Input
Frequency (MHz)
Output
Frequency
(MHz)
Phase
Jitter
(fs RMS)
PLL
Bandwidth
Package
Si5342 4/2
0.008
to
750 MHz
0.001
to
1028 MHz
100
integer
150
fractional
0.1 Hz
to
4 kHz
Q44FN 7x7mm
Si5344 4/4 Q44FN 7x7mm
Si5345 4/10 6Q4FN 9x9mm
APPLICATIONS
FEATURES
Synchronous Ethernet
Servers / storage](https://image.slidesharecdn.com/5clocktreedesigntechniquestooptimizeserdesperformancefornetworkinganddatacentersbysiliconlabs-171018200952/85/5-Clock-Tree-Design-Techniques-to-Optimize-SerDes-Performance-for-Networking-and-Data-Centers-39-320.jpg)
5 Clock Tree Design Techniques to Optimize SerDes Performance for Networking and Data Centers
- 1. 5 Clock Tree Design Techniques to Optimize 10/25/40/56 Gb/s SerDes Performance for Networking and Data Centers O C T O B E R 2 0 1 7
- 2. Timing requirement overview in 10G-100G design Clock tree definition Jitter and Phase Noise Design challenges: jitter and phase noise budgets Power supply noise rejection Driving long clock traces Optimizing for performance, cost, size constraints Timing solutions for high-speed clock trees Agenda
- 3. Timing Requirements in 10G-100G Design
- 4. Common Frequencies and Requirements Protocol/System Clock Frequency Jitter Requirement (Max) 10/25/40GbE PHY 161.1328125MHz 350fs RMS 322.265625MHz 257.8125MHz 28G SerDes 125MHz 300fs RMS 156.25MHz 312.5MHz 56G SerDes 156.25MHz 150fs RMS PCIe Gen3/4 100MHz 1ps / 0.5ps RMS CCIX / NVLink 100MHz / 156.25MHz <0.3ps RMS Memory/CPU 133.3333MHz >1ps RMS 156.25MHz 133.33MHz w/ -0.5% SS 155.52MHz FPGA 312.5MHz 50MHz Switch SoC Memory PHY 4 2 2 2
- 5. Jitter, Phase Noise, and Phase Jitter Jitter is the deviation in time from an ideal reference clock Time domain measurement Phase noise is the noise on a reference clock Frequency domain measurement Integrating the area under the curve across a defined band yields RMS phase jitter
- 6. Keysight E5052B spectrum analyzer Frequency measured: 155.52MHz Phase Noise, in dBc/Hz Integrated RMS Phase Jitter Filter mask Phase noise curve Reading A Phase Noise Plot
- 7. FPGA and Switch SoC Timing Requirements Xilinx FPGAs Intel/Altera FPGAs Frequency Offset GTY Transceiver QPLL GTH Transceiver QPLL 10 kHz -112 dBc/Hz -111 dBc/Hz 100 kHz -128 dBc/Hz -130 dBc/Hz 1 MHz -145 dBc/Hz -136 dBc/Hz Frequency Offset Stratix 10 GX/SX Arria 10 GX/SX/GT Stratix V GX/GS/GT Arria V GT/ST 100 Hz -82 dBc/Hz -80 dB/Hz 1 kHz -102 dBc/Hz -110 dBc/Hz 10 kHz -112 dBc/Hz -120 dBc/Hz 100 kHz -128 dBc/Hz -120 dBc/Hz 1 MHz -145 dBc/Hz -130 dBc/Hz FPGA suppliers specify reference clock performance requirements as Phase Noise 156.25MHz common SerDes reference Clock Additional reference clocks needed on most platforms for I/O and data buses
- 8. Switch SoC Timing Requirements IC Supplier Phase Jitter (Max) Broadcom Trident II/III 300fs RMS Broadcom Tomahawk II 150fs RMS Barefoot Tofino 300fs RMS Cavium xPliant 300fs RMS Switch SoC suppliers specify reference clock performance requirements as Phase Jitter 156.25MHz common SerDes reference Clock 28G SerDes require <300fs RMS 56G SerDes require <150fs RMS
- 9. PCI-Express and Other Data Bus Requirements PCI-Express endpoints require a 100MHz HCSL reference clock -0.5% spread spectrum may be used to reduce system EMI CCIX is a new standard that leverages a lot of similar specifications as PCI- Express, but requires a higher performance reference clock to support higher bandwidth. OpenCapi and NVLink are typically used in server and storage applications based in nVidia and IBM architectures. PCI-Express Alternative Data Buses Revision Data Rate Frequency Max Jitter Spec Gen1 2.5G 100MHz 108 ps P-P Gen2 5G 3.1 ps RMS Gen3 8G 1 ps RMS Gen4 16G 0.5ps RMS Data Rate Frequency Max Jitter Spec CCIX 25G 100MHz 0.3 ps RMS NVLink 25G 156.25MHz 0.25 ps RMS OpenCapi 25G 133MHz 0.5 ps RMS
- 10. Defining A Clock Tree
- 11. List all reference clocks needed for the various ICs in the design Gather additional information from reading through datasheets Determine if additional features or functions are needed: Selectable frequency Spread spectrum Synchronizing to an input clock Jitter attenuation Hitless switching Holdover Pin/OE control Frequency Requirements Frequency # Outs Format Reference Voltage Jitter / Phase Noise 155.52MHz 1 LVDS FPGA 1.8V 100Hz, -70dBc/Hz 10kHz, -100dBc/Hz 1Mhz, -120dBc/Hz 156.25MHz 4 LVDS Switch SoC 3.3V 150fs RMS 50MHz 1 LVCMOS Switch SoC 2.5V 4ps 50MHz 1 LVCMOS Switch Soc 2.5V 2ps 133.33MHz 2 LVDS System / memory 2.5V 500fs RMS 312.5MHz 2 LVPECL PHY 3.3V 300fs RMS
- 12. Types of Timing Devices Crystal Single-ended sine wave output LVCMOS XO Single-ended square wave output Differential XO Differential or complementary square wave output Clock Generator Up to 12 differential or single-ended square wave outputs. Added features/capability
- 13. Synchronous Vs. Asynchronous Design Asynchronous Timing ArchitectureSynchronous Timing Architecture PHYs PHYs Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 PHYs PHYs Si5332 Clock Generator PHYs PHYs Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 PHYs PHYs Si5345 Jitter Attenuator Backplane Clock
- 14. Jitter and Phase Noise Budgets
- 15. Between IC manufacturers Between standards and IC manufacturers Between timing IC suppliers Temp range Integer only vs fractional frequencies Typical vs Max Other Considerations: Buffers Power supply noise Pay Close Attention to Specifications
- 16. Understanding Margin Si52202/04/08/12 PLL (w/SSC) XIN/CLKIN DIFFn÷ I2C XOUT REF HW Input Control Spread Spectrum Frequency Select PWRGD/ PWRDNb OSC 2 to 12 VDD_IO OEbn Revision PCI-SIG Si522xx Units Gen1 86 21 ps ps P-P Gen2 Low Band 3 0.9 ps RMS Gen2 Hi Band 3.1 1.4 ps RMS Gen3 1 0.3 ps RMS Gen3 SRIS 1 0.39 ps RMS Gen4 0.5 0.3 ps RMS Gen4 SRIS 0.5 0.41 ps RMS Check jitter requirements specified by endpoint as well
- 17. Understanding Filter Masks Compare datasheet filter masks 12kHz-20MHz is the most common Data bus filter masks can be very specific Use PCIe Jitter Tool to simplify measurements
- 18. Si54x Oscillators for PAM4 Transceiver Modules 80fs RMS phase jitter provides margin On-chip regulation ensures low jitter operation Eliminates power supply filtering Simplifies layout and design Small form factor 3.2 x 5mm package VDD Gearbox TX RX PAM/NRZ Transceiver Retimeror Si540 XO TX RX Driver Laser Mux TIA PD Demux 100G/200G Optical Module
- 19. Some IC manufacturers only specify maximum phase noise limits for reference clocks Silicon Labs offers an online calculator simplifying conversion from phase noise to phase jitter Available on Silicon Labs website Phase Noise to Jitter Calculator
- 20. Power Supply Noise Rejection
- 21. Switching power supplies ripple at the switching frequency and harmonics SoCs, FPGAs, processors, and other ICs create ripple around their clocking rates as they switch from one sequential state to another. These factors negatively affect jitter performance on clocks using the same power rails Power Supply Noise Effects
- 22. High Noise Rejection Ensures Reliable Operation <0.1 ps of additive jitter Filter the noise to maximize jitter performance LDOs, capacitor networks, and ferrite beads Poor filtering can destroy jitter budget margin Review timing supplier recommendations
- 23. Factor regulation into your jitter, PCB, cost budgets External components may be required Integrated regulation simplifies system design Achieve optimized jitter performance On-Chip Noise Regulation Saves Board Space and Cost Si5332 1uF 0.1uF VDD or VDDO pin 1.8V-3.3V Component Si5332 Competitor A Capacitors 18 63 Ferrite Bead --- 1 External LDO --- 1
- 24. Driving Long Clock Traces
- 25. Distributed vs Centralized Clock Tree Architecture Centralized Timing ArchitectureDistributed Timing Architecture PHYs PHYs 10/25/100G Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 PHYs PHYs Si5332 Clock Generator PHYs PHYs 10/25/100G Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 Si53306 Buffer Si535 XO Si53306 Buffer Si545 XO Si510 XO Si545 XO PHYs PHYs
- 26. Synchronous vs asynchronous design Processor, FPGA, switch SoC timing requirements Jitter and/or phase noise requirements Connectors and cables PCIe Data bus architecture (Common clock vs SRIS) PCB area and system cost System EMI Considerations In Selecting Clock Tree Architecture
- 27. Pros Short clock trace lengths Ability to source from multiple vendors Cons BOM Cost Multi-chip solution consumes PCB area Difficult to meet 56G SerDes jitter requirements No added feature capabilities: Spread spectrum, frequency control, clock margining, LOS/LOL, signal integrity tuning Distributed Clock Trees PHYs PHYs 10/25/100G Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 Si53306 Buffer Si535 XO Si53306 Buffer Si545 XO Si510 XO Si545 XO PHYs PHYs
- 28. Pros Clock consolidation into a single IC Jitter performance can meet 28/56G SerDes Reduced board space Signal integrity tuning features High immunity to board/power supply noise Cons Clock traces may be long, layout dependent Centralized Clock Trees PHYs PHYs 10/25/100G Switch SoC 312.5MHz 125MHz 4 25MHz or 50MHz FPGA 156.25MHz 4 PHYs PHYs Si5332 Clock Generator
- 29. Clock generators provide in-system programmability features via I2C Amplitude tuning Skew tuning Frequency tuning Slew rate control NVM configuration overwrite options CBPROG-DONGLE Signal Integrity Tuning Features Within Clock Generators
- 30. HCSL Push-Pull Driver Architecture Legacy current mode driver Push-pull driver Silicon Labs HCSL Push-Pull Driver PCI Express Device L1 L1' L2 L2' L1 RIREF L1' HCSL Output Driver L5 RS RS L3' L3 L4 L4' PCI Express Device RT RT 4 resistors required per differential output Current source resistor Push-Pull Benefits 60% lower power No termination resistors No IREF resistor Can drive longer clock traces AN871 - Theoretical AN951 - Practical
- 31. Cost, Performance, PCB Area Constraints
- 32. Challenges Faced: 56G SerDes jitter requirements Shrinking PCB area Jitter vs power consumption Frequency flexibility: fractional clocks The Balancing Act Cost Performance Board Space Power
- 33. Total PCB area required vs IC package size Carefully read jitter performance specs External power filtering components External vs internal loop filters VCXO vs crystal reference source Not All Timing ICs Are Created Equal: Solution Cost vs IC Cost Backplane PHY/ SerDes PHY/ SerDes Si5345 PHY/ SerDes PHY/ SerDes Other JA Clock External Loop Filter External VCXO Example: Timing Line Card using Jitter Attenuator
- 34. Clock Tree Solutions For High-Speed Clock Trees
- 35. Complete Timing Portfolio Leader in high performance clocks and oscillators Frequency flexibility + ultra-low jitter Best-in-class integration single IC clock trees Highly programmable with quick-turn samples XO/VCXO Clock BuffersClock Generators Jitter Attenuating ClocksSynchronization Wireless Clocks
- 36. Si54x Ultra SeriesTM Crystal Oscillators (XO) Ultra low jitter: 80 fs RMS Any frequency from 200 kHz – 1.5 GHz Single/Dual/Quad options, 3.2x5mm Better stability and aging than SAW oscillators 1-2 week sample lead time High quality, 100% tested Built-in power supply noise rejection Ideal for 28G / 56G SerDes DSPLL Pin XO Fixed Frequency XTAL Frequency Flexible DSPLL Flexible Output Formats < 50 fs of additive jitter World’s Lowest Jitter, Any Frequency XO
- 37. Optical networking Wireless infrastructure Si5341/40 Low Jitter Any-Frequency Clocks ANY input frequency to ANY combination of output frequencies 100 fs (int); 140 fs (frac) RMS phase jitter (12kHz -20MHz) Configurable outputs: LVPECL, LVDS, LVCMOS, HCSL, CML Glitchless, dynamic on-the-fly output frequency switching Customizable using ClockBuilder Pro -40⁰C to +85⁰C operation FB_IN IN0 IN_SEL IN1 IN2 XB XA XTAL ÷INT ÷INT ÷INT OSC Multi Synth OUT0÷INT OUT1÷INT OUT2÷INT OUT3÷INT OUT4÷INT OUT5÷INT OUT6÷INT OUT7÷INT OUT8÷INT OUT9÷INT Multi Synth Multi Synth Multi Synth Multi Synth Si5340 Si5341 PLL ÷INT NVM I2 C/SPI Control/ Status Part Number Clock Inputs/ Outputs Input Frequency (MHz) Output Frequency (MHz) Phase Jitter (fs RMS) PLL Bandwidth Package Si5340 4/4 10 to 750 MHz 0.001 to 1028 MHz 100 integer; 140 fractional 1 MHz Q44FN 7x7mm Si5341 4/10 6Q4FN 9x9mm APPLICATIONS FEATURES Servers / storage 100GbE switches
- 38. Si5332 Any Frequency Clock Generators for 10/25/50/100G Si5332, 8-Output NVM Control Low Jitter PLL OUT0 VDDO0 VDDO3 OUT4 OUT1 VDDO1 OUT2 VDDO2 ÷INT ÷INT ÷INT ÷INT VDDO4 OUT6÷INT VDDO5 OUT7÷INT OUT3÷INT OUT5÷INT CLKIN_3 CLKIN_2 XTAL OSC ÷INT Multi Synth1 INT4 Multi Synth0 INT3 INT2 INT1 INT0 I2C HW Input Pins Generates any mix of output frequencies Consolidates XOs, clocks, and buffers User-defined HW input pins Frequency select, SSC, OE control Two independent SSCG domains Optional embedded reference crystal Part Number No. of Clock Outputs Input Frequency Output Frequency Phase Jitter (fs RMS) # Control Pins Package Si5332 6 / 8 / 12 10 MHz to 250 MHz 10 MHz to 312.5 MHz 230 5 / 7 / 7 32-QFN, 40- QFN, 48-QFN Si5357 (LVCMOS only) 12 10 MHz to 170 MHz 10 MHz to 170 MHz 230 5 32-QFN Enterprise switches/routers 10/25/50/100 GbE switches Low phase jitter 230 fs RMS (integer) 500 fs RMS (fractional) HCSL, LVDS, LVPECL, LVCMOS formats High PSNR simplifies external filtering 1.8V – 3.3V operation APPLICATIONS FEATURES Servers/storage Industrial and broadcast video
- 39. Si5345/44/42 Any-Frequency Jitter Attenuators Optical networking Wireless infrastructure ANY input frequency to ANY combination of output frequencies 100 fs (int); 150 fs (frac) RMS phase jitter [12kHz -20MHz] Jitter/wander attenuation down to 0.1 Hz Automatic hitless input switching Free-run, locked, holdover; status monitoring: LOL, LOS, OOF DCO mode: 0.001 ppb step resolution DSPLL IN0 IN_SEL IN1 IN2 IN3/ FB_IN ÷FRAC ÷FRAC ÷FRAC ÷FRAC XTAL XBXA OSC Optional External Feedback Multi Synth OUT0÷INT OUT1÷INT OUT2÷INT OUT3÷INT OUT4÷INT OUT5÷INT OUT6÷INT OUT7÷INT OUT8÷INT OUT9÷INT Multi Synth Multi Synth Multi Synth Multi Synth Si5344 Si5342 Si5345 NVM I2 C/SPI Control/ Status Part Number Clock Inputs/ Outputs Input Frequency (MHz) Output Frequency (MHz) Phase Jitter (fs RMS) PLL Bandwidth Package Si5342 4/2 0.008 to 750 MHz 0.001 to 1028 MHz 100 integer 150 fractional 0.1 Hz to 4 kHz Q44FN 7x7mm Si5344 4/4 Q44FN 7x7mm Si5345 4/10 6Q4FN 9x9mm APPLICATIONS FEATURES Synchronous Ethernet Servers / storage
- 40. Features ANY format input/output translation Ultra-low additive jitter (<100fs) Integrated muxes, dividers, level shifters Simplified clock distribution Up to 10 differential outputs Si533xx Universal Clock Buffers Pin Universal Clock Buffer Output Clocks Input Clocks Bank A Bank B DIV DIV Multi-Format Drivers
- 41. Features 1.5V – 1.8V low power PCIe clocks Family of 2, 4, 8, and 12 output devices 400 fs max RMS phase jitter (CLK Gen) PCIe Gen 1/2/3/4 compliant Supports SRIS and Common Clock architectures Push-pull output drivers I2C-controlled, HW pins for SSC, Frequency Select, OE per output PCIe Gen 1/2/3/4 Clock Generators/Buffers Low Jitter PLL PCIe Clock Generator PCIe Clock Outputs DIVOSC 25MHz PCIe Fanout Buffers Up to 19 PCIe Clock Outputs
- 42. S I L A B S . C O M Thank you.