![ADDRESSING MODE
ADDRESSING MODE DEFINITION
EXAMPLE
(8086)
EXAMPLE
(8051)
IMMEDIATE
ADDRESSING MODE
DATA IS GIVEN IN THE
INSTRUCTION ITSELF
MOV AX, 05 MOV A, #05
DIRECT
ADDRESSING MODE
MEMORY ADDRESS IS
GIVEN DIRECTLY IN
THE INSTRUCTION
ITSELF
MOV AX, [05] MOV A,05
REGISTER
ADDRESSING MODE
BOTH SOURCE AND
DESTINATION
OPERANDS ARE
REGISTERS
MOV AX,BX MOV A,B
REGISTER INDIRECT
ADDRESSING MODE
OFFSET ADDRESS IS
SPECIFIED THROUGH
POINTER REGISTER OR
INDEX REGISTER
MOV AL,(BP)
XOR (DI),CL
MOV A,@R0
BASE PLUS INDEX
REGISTER
ADDRESSING MODE
BASE REGISTER AND
NDEX REGISTER ARE
USED TO ACCESS
DATA INDIRECTLY.
MOV (BX + DI),AL
ADDRESS IS
LOCATED AS
((DS X 10)+(BX+DI)
AL
NIL
REGISTER RELATIVE
ADDRESSING MODE
OFFSET IS
CALCULTAED USING
BASE REGISTER OR
INDEX REGISTER PLUS
DISPLACEMENT
MOV AX,(DI +06)
AX ((DS X
10)+(DI+06)
NIL
BASE PLUS INDEX
REGISTER RELATIVE
ADDRESS OF
OPERAND IS
CALCULTAED BASE
MOV (BX+DI+2),CL NIL](https://image.slidesharecdn.com/8051microcontroller-210515072021/85/8051-microcontroller-41-320.jpg)
8051 microcontroller
- 2. S.No. Microprocessor Microcontroller 1 Microprocessor contains ALU, Control unit, different registers and interrupts circuit. Microcontroller contains microprocessor, memory, IO interfacing circuit, peripheral devices such as AD converter, serial IO timer, etc. 2 Many instructions to move data between memory and CPU One or two instructions to move data between memory and CPU 3 One or two bit handling instructions Many bit handling instructions 4 Access time for memory or IO device is more Access time for memory or IO device is less 5 Microprocessor based systems require more hardware Microcontroller based systems require less hardware 6 Microprocessor based systems is more flexible from design point of view Microcontroller based systems less flexible from design point of view 7 Single memory for code and data Separate memory for code and data 8 Less number of pins are multifunction More number of pins are multifunction
- 3. 8051 ARCHITECTURE FEATURES 4096 bytes of onchip program memory 128 bytes of on chip data memory Four register banks 128 user defined software flags 64 kilobytes each program and external RAM addressability One us instruction cycle with 12 MHZ crystal 32 bidirectional IO lines organised as four ports Multiple mode, high speed programmable serial port Two multiple mode 16 bit timer/counters
- 4. Two level prioritised interrupt structure Full depth stack for subroutine return linkage and data storage Direct byte and bit addressability Binary or decimal aritmetic Signed overflow detection and parity computation Hardware multiple and divide in 4us. 8051 ARCHITECTURE It consists of 4 ports. They are port 0,port 1, port 2, port 3. Port is a slot where data is stored or read. The data from port is transferred to CPU through buffer. The data from CPU is transferred to port through latch. Port 0: It is 8 bit port. It is used general IO port. It is used as multiplexed address and data bus. Port 1: It is 8 bit port. It is used general IO port.
- 5. Port 2: It is 8 bit port. It is used general IO port. It is used as higher order address bus. Port 3: It is 8 bit port. It is used general IO port. It is used for interrupt , timer or counter signal, serial data transfer, RD and WR A and B register REGISTER A: It is an 8 bit register It is called accumulator register. One of the operand is stored in accumulator and the result is stored in accumulator. REGISTER B: It is an 8 bit register It is general purpose register. It is used for hardware multiply and divide operation. DATA POINTER: It is 16 bit register. It has high byte(DPH) and low byte (DPL). It is used as base register in indirect jumps, look up table instructions and externa data transfer.
- 6. PROGRAM COUNTER: It is 16 bit program counter It is used to point to the address of next instruction to be executed. OSC: Osc refers to oscillator. It is used to generate clock signal. Frequency of operation is 12 MHZ. PSEN: It is program store enable. It is used to store program in external memory. It is active low signal. For 0 it stores program in external memory. For 1 , no operation takes place. EA : It is external access. It is used to access the data from external from memory. It is active low signal. For 0 it access the program from external memory. For 1 , no operation takes place. RST: It is used to reset the 8051. It is high for atleast 2 machine cycles while oscillator is running. Vcc: Supply voltage is +5v. GND – ground is 0v.
- 7. Power supply current is 125 mA. PSW: Program Status Word Buffer is used to get the data input from port. Latch is used to out the data through port. RAM : Random Access Memory. It is used to store data. PCON – Power Control SCON – Serial Control TMOD – Timer Mode Register TCON – Timer Control Register SBUF – Serial Buffer
- 8. SPECIAL FUNCTIONAL REGISTERS: The group of registers implemented to perform special functions and are located immediately above 128 bytes of RAM are called special function registers. It monitors the operation of microcontroller. Some of the SFRs are DPTR DPH DPL P0 P1 P2 P3 TMOD TCON TH0
- 9. TH1 TL0 TL1 SBUF PCON
- 10. PSW REGISTER: Program Status Word register It is also known as flag register B7 B6 B5 B4 B3 B2 B1 B0 CY AC F0 RS1 RS0 OV - P P – parity flag. It is defined by number of ones present in the accumulator. P=0; number of ones are even. P=1; number of ones are odd. OV – overflow flag It is set when result of signed number operation is too large causing higher order bit to overflow into the sign bit.
- 11. RS1- RS0 – Register bank selection RS1 RS0 BANK SELECTION 0 0 00-07 H 0 1 08-0F H 1 0 10-17 H 1 1 18-1F H CY CARRY FLAG It is set when there is an overflow out of 8th bit. AC – Auxilaary Carry Flag It is set when there is an overflow out of bit 3 from lower nibble to higher nibble.
- 12. 8051 IO PORT STRUCTURE It consists of 32 bidirectional IO pins configured as 4 IO ports. Each port consists of latch output driver and input buffer. PORT 0: Port 0 consists of 8 pins. It is used as general IO port. It is also used as multiplexed address and data bus. Port 0 is used as lower order address bus. It is used to access external memory.
- 13. PORT 1: Port 1 consists of 8 pins. It is used as general IO port.
- 14. PORT 2: Port 2 consists of 8 pins. It is used as general IO port. Port 2 is used as higher order address bus. PORT 3: Port 3 consists of 8 pins. It is used as general IO port. Port 3 is multifunctional.
- 15. They are used to perform special functions such as external interrupts, two counter inputs, two special data lines and two timing control strobes.
- 16. SYMBOL POSITION ALTERNATE USE RD P3.7 EXTERNAL MEMORY READ SIGNAL WR P3.6 EXTERNAL MEMORY WRITE SIGNAL T1 P3.5 EXTERNAL TIMER 1 INPUT T0 P3.4 EXTERNAL TIMER 0 INPUT INT 1 P3.3 EXTERNAL INTERRUPT 1 INPUT INT0 P3.2 EXTERNAL INTERRUPT 0 INPUT TXD P3.1 SERIAL DATA OUTPUT RXD P3.0 SERIAL DATA INPUT
- 18. DATA TRANSFER INSTRUCTION It is used to transfer data from one register to another register, register to memory location. MOV A, RN Data from register is copied to Accumulator. Eg . MOV A, R0 MOV A, DIRECT Data from memory address is copied to Accumulator. EG. MOV A,30H MOV A, @Ri Data from address in Ri is copied to Accumulator. EG. MOV A, @R0 MOV A, # DATA Data is loaded to Accumulator. EG. MOV A,# 05 MOV RN, A Data from Accumulator is copied to Register. Eg . MOV R0, A MOV RN, DIRECT Data from memory location is copied to Register. Eg . MOV R0, 50
- 19. MOV RN, # DATA Load Data to Register. Eg . MOV R0, #05 MOV DIRECT, A Copy the contents from accumulator to memory location. Eg. MOV 30, A MOV DIRECT, RN Copy the contents from register to memory location. Eg. MOV 30, R0 MOV DIRECT, DIRECT Copy the contents from one memory location to another memory location. Eg. MOV 30, 40 MOV DIRECT, @RI Copy the contents from address specified by register to another memory location. Eg. MOV 30, @R0 MOV DIRECT, # DATA Load the data to specified memory location. Eg. MOV 30, #05 MOV @RI, A Copy the contents of accumulator to the address specified by register. Eg. MOV @R0,A
- 20. MOV @RI, DIRECT Copy the contents from the address to the address specified by register. Eg. MOV @R0, 30 MOV @RI, # DATA Load the data to the address specified by register. Eg. MOV @R0, #30 MOV DPTR, # DATA 16 Load data pointer with 16 bit constant Eg . MOV DPTR, # 1234 DATA TRANSFER WITH STACK PUSH DIRECT PUSH B The stack pointer is incremented by 1. Stores the content of register B in internal RAM location addressed by stack pointer. SP=SP+1 SP = DIRECT POP DIRECT POP ACC Stack pointer is decremented by 1. It copies the contents of RAM location addressed by stack pointer to accumulator. SP=SP-1 DIRECT = SP
- 21. Some times bits may be transferred. MOV C, BIT BIT IS MOVED TO CARRY FLAG C BIT MOV BIT, C CARRY FLAG BIT IS MOVED TO ADDRESS LOCATION SPECIFIED. BIT C ACCUMULATOR SPECIFIC TRANSFERS XCH A, BYTE It is used to exchange the contents of accumulator with those indicated variable. XCH A, RN XCH A, DIRECT XCH A, @ Ri XCHD A, @Ri It is used to exchange the lower order nibble of accumulator with that of internal RAM location indirectly specified by the specific register. A(3-0) Ri (3-0)
- 22. 8 BIT DATA TRANSFER MOVX A, @Ri It is used to transfer data between accumulator and a byte external to the data memory. MOVX @ Ri, A 16 BIT DATA TRANSFER MOVX A, @DPTR Here 16 bit data is transferred between data pointer register and accumulator MOVX @DPTR, A Here 16 bit data is transferred between data pointer register and accumulator MOVC instruction is used to load the accumulator with a byte code or a constant from the program memory. MOVC A, @ A+ DPTR A A+DPTR MOVC A, @A+PC A A+PC
- 23. ARITHMETIC INSTRUCTIONS ADDITION ADD A, SRC BYTE It is used to add destination operand A with source operand and store the result in destination operand. EG. ADD A, R0 Contents of A and R0 are added and stored in accumulator. A A +R0 ADD A, 05 Contents of A and content present in address location 05 are added and stored in accumulator. A A + CONTENT IN 05 ADD A, @ R0 Contents of A and content present in address location pointed by R0 are added and stored in accumulator. A A + CONTENT POINTED BY R0 ADD A, #05 Contents of A and data 05 are added and stored in accumulator. A A +05
- 24. ADDITION WITH CARRY ADDC A, SRC BYTE It is used to add destination operand A with source operand along with carry and store the result in destination operand. Carry flag is affected. EG. ADDC A, R0 Contents of A and R0 are added along with carry and stored in accumulator. A A +R0 +C ADDC A, 05 Contents of A and content present in address location 05 are added along with carry and the result is stored in accumulator. A A + CONTENT IN 05 +C ADDC A, @ R0 Contents of A and content present in address location pointed by R0 are added along with carry and the result is stored in accumulator. A A + CONTENT POINTED BY R0 +C ADDC A, #05 Contents of A and data 05 are added along with carry and the result is stored in accumulator A A +05 +C
- 25. INCREMENT It is used to increment the variable by 1. INC A A A +1 INC R0 R0 R0 +1 INC DIRECT DIRECT DIRECT +1 INC @R0 R0 R0 +1 INC DPTR DPTR DPTR +1
- 26. SUBTRACTION WITH BORROW SUBB A, SRC BYTE It is used to subtract destination operand A with source operand along with borrow and store the result in destination operand. Carry flag is affected. EG. SUBB A, R0 Contents of A and R0 are subtracted along with carry and the result is stored in accumulator. A A –C-R0 SUBB A, 05 Contents of A and content present in address location 05 are subtracted along with carry and the result is stored in accumulator. A A –C- CONTENT IN 05 SUBB A, @ R0 Contents of A and content present in address location pointed by R0 are subtracted along with carry and the result is stored in accumulator. A A –C- CONTENT POINTED BY R0 SUBB A, #05 Contents of A and data 05 are subtracted along with carry and the result is stored in accumulator A A –C- 05
- 27. DECREMENT It is used to decrement the variable by 1. DEC A A A -1 DEC R0 R0 R0 -1 DEC DIRECT DIRECT DIRECT -1 DEC @R0 R0 R0 -1 DEC DPTR DPTR DPTR -1 MULTIPLICATION It is used to multiply two datas MUL AB Two unsigned 8 bit numbers are obtained in A and B register. They are multiplied. The lower order 8 bits are stored in accumulator register The higher order 8 bits are stored in B register. If the product is greater than 255 bits then overflow flag is set.
- 28. DIVISION It is used to divide two datas DIV AB Two unsigned 8 bit numbers are obtained in A and B register. They are divided. The quotient is stored in accumulator register The remainder is stored in B register. DAA DECIMAL ADJUST ACCUMULATOR FOR ADDITION It is used in case of BCD addition where the value 6 is added to the result to get correct BCD value. If the value of lower nibble is greater than 9, AC flag is set, then 6 is added to ACC. If the value of higher nibble is greater than 9, AC flag is set, then 6 is added to ACC. LOGICAL OPERATION Two operand instruction AND LOGIC ANL DEST BYTE, SRC BYTE It used to perform AND logic of source and destination operand and store the result in destination operand.
- 29. ANL A, RN A A & R0 ANL A, R0 ANL A, DIRECT A A & DIRECT ANL A, 05 ANL A, @RI A A & CONTENT POINTED BY RI ANL A,@R0 ANL A, #DATA A A & DATA ANL A,# 05 ANL C, BIT C C & BIT ANL C, /BIT C C & BIT OR LOGIC ORL DEST BYTE, SRC BYTE It used to perform OR logic of source and destination operand and store the result in destination operand. ORL A, RN A A | R0
- 30. ORL A, R0 ORL A, DIRECT A A | DIRECT ORL A, 05 ORL A, @RI A A | CONTENT POINTED BY RI ORL A,@R0 ORL A, #DATA A A | DATA ORL A,# 05 ORL C, BIT C C | BIT ORL C, /BIT C C | BIT XOR LOGIC XRL DEST BYTE, SRC BYTE It used to perform XOR logic of source and destination operand and store the result in destination operand. XRL A, RN A A + R0 XRL A, R0
- 31. XRL A, DIRECT A A + DIRECT XRL A, 05 XRL A, @RI A A+ CONTENT POINTED BY RI XRL A,@R0 XRL A, #DATA A A + DATA XRL A,# 05
- 32. NOP NO OPERATION EXECUTION CONTINUES AT THE FOLLOWING INSTRUCTION. NO FLAGS ARE AFFECTED. PC PC+1 CONDITIONAL JUMP JB BIT, REL. IF THE INDICATED BIT IS 1 JUMP TO THE ADDRESS GIVEN. OTHERWISE PROCEED TO THE NEXT INSTRUCTION. PC PC+3 IF BIT =1 THEN PC PC+REL JBC BIT,REL JUMP IF BIT IS SET AND CLEAR BIT IF THE INDICATED BIT IS 1 JUMP TO THE ADDRESS GIVEN. OTHERWISE PROCEED TO THE NEXT INSTRUCTION. IN EITHER CASE CLEAR THE DESIGNATED BIT PC PC+3 IF BIT =1 THEN BIT 0 PC PC+REL
- 33. JC REL JUMP IF CARRY IS SET IF THE CARRY FLAG IS SET JUMP TO THE ADDRESS INDICATED, OTHERWISE PROCEED WITH THE NEXT INSTRUCTION NO FLAGS ARE AFFECTED PC PC+2 IF C =1 THEN PC PC+REL JNB BIT,REL JUMP IF BIT NOT SET IF THE INDICATED BIT IS A “0’, BRANCH TO THE INDICATED ADDRESS. OTHERWISE PROCEED TO THE NEXT INSTRUCTION. NO FLAGS AFFFECTED. PC PC+3 IF BIT =0 THEN PC PC+REL JNC REL JUMP IF CARRY IS NOT SET IF THE CARRY FLAG IS “0” JUMP TO THE ADDRESS INDICATED, OTHERWISE PROCEED WITH THE NEXT INSTRUCTION PC PC+2 IF C =0 THEN PC PC+REL
- 34. JNZ REL JUMP IF ACCUMULATOR IS NOT ZERO IF ANY BIT OF ACCUMULATOR IS “1”, JUMP TO THE ADDRESS INDICATED, OTHERWISE PROCEED WITH THE NEXT INSTRUCTION PC PC+2 IF A NOT EQUALS TO “0” THEN PC PC+REL JZ REL JUMP IF ACCUMULATOR IS ZERO IF ALL BITS OF ACCUMULATOR IS “0”, JUMP TO THE ADDRESS INDICATED, OTHERWISE PROCEED WITH THE NEXT INSTRUCTION PC PC+2 IF A = “0” THEN PC PC+REL CJNE <DES.BYTE><SRC BYTE>, REL. COMPARE AND JUMP IF NOT EQUAL IT COMPARES TWO DATA, IF TWO DATAS ARE NOT EQUAL THEN JUMP TO THE ADDRESS INDICATED. CJNE A, DIRECT, REL THE ACCUMULATOR CONTENT AND CONTENT PRESENT IN ADDRESS LOCATION ARE COMPARED
- 35. , IF THEY ARE NOT EQUAL THEN IT BRANCH TO THE ADDRESS INDICATED. PC PC+3 IF (DIRECT <A) PC PC +REL AND C 0 OR IF (DIRECT >A) PC PC +REL AND C 1 CJNE A, #DATA, REL THE ACCUMULATOR CONTENT AND IMMEDIETE DATA ARE COMPARED , IF THEY ARE NOT EQUAL THEN IT BRANCH TO THE ADDRESS INDICATED. PC PC+3 IF (DATA <A) PC PC +REL AND C 0 OR IF (DATA >A) PC PC +REL AND C 1 CJNE RN, #DATA, REL THE REGISTER CONTENT AND IMMEDIETE DATA ARE COMPARED , IF THEY ARE NOT EQUAL THEN IT BRANCH TO THE ADDRESS INDICATED. PC PC+3 IF (DATA <RN)
- 36. PC PC +REL AND C 0 OR IF (DATA >RN) PC PC +REL AND C 1 CJNE @RI, #DATA, REL THE CONTENT POINTED BY REGISTER VALUE AND IMMEDIETE DATA ARE COMPARED , IF THEY ARE NOT EQUAL THEN IT BRANCH TO THE ADDRESS INDICATED. PC PC+3 IF (DATA <RI) PC PC +REL AND C 0 OR IF (DATA >RI) PC PC +REL AND C 1 DJNZ <BYTE>, <REL ADDR> DECREMENT AND JUMP IF NOT ZERO. IT DECREMENTS BY 1 THE CONTENTS OF THE LOCATION INDICATED AND BRANCHES TO THE ADDRESS INDICATED BY THE SECOND OPERAND IF THE RESULTING VALUE IS NOT ZERO. DJNZ RN, REL IT DECREMENTS THE CONTENT OF RN AND BRANCHES TO THE ADDRESS IF RESULT IS NOT ZERO. PC PC+2 RN RN -1
- 37. IF RN>0 OR RN<0 PC PC +REL DJNZ DIRECT, REL PC PC+2 DIRECT DIRECT -1 IF DIRECT>0 OR DIRECT <0 PC PC +REL
- 38. ACALL: ABSOLUTE CALL IT UNCONDITIONALLY CALLS A SUBROUTINE LOCATED AT THE INDICATED ADDRESS. ACALL IS A 2 BYTE INSTRUCTION. PC IS INCREAMENTED BY 2 TO POINT TO THE NEXT INSTRUCTION. DESTINATION ADDRESS IS OBTAINED BY SUCCESSIVELY CONCATENATING THE FIVE HIGH ORDER BITS OF THE INCREAMENTED PC, OPCODE BITS 7-5, AND SECOND BYTE OF THE INSTRUCTION. THE SUBROUTINE MUST BE WITHIN THE SAME 2K BLOCK OF THE PROGRAM MEMORY. NO FLAGS AFFECTED. PC PC +2 SP SP+1 SP PC (7-0) SP SP +1 SP PC (15-8) PC (10-0) PAGE ADDRESS LCALL ADDR 16: LONG CALL LCALL IS A 3 BYTE INSTRUCTION. PC IS INCREAMENTED BY 3 TO POINT TO THE NEXT INSTRUCTION. PC PC +3 SP SP+1 SP PC (7-0) SP SP +1 SP PC (15-8) PC (10-0) ADDRESS 15-0
- 39. RET RETURN FROM SUBROUTINE IT POPS THE RETURN ADDRESS FROM THE STACK AND LOADS INTO THE PC. PROGRAM CONTINUES AT THE RESULTING ADDRESS. PC 15-8 SP SP SP-1 PC7-0 SP SP SP-1 RETI RETURN FROM INTERRUPT IT POPS THE RETURN ADDRESS FROM THE STACK AND LOADS INTO THE PC AND RESTORES THE INTERRUPT LOGIC TO ACCEPT ADDITIONAL INTERRUPTS AT THE SAME PRIORITY LEVEL. PROGRAM CONTINUES AT THE RESULTING ADDRESS. PC 15-8 SP SP SP-1 PC7-0 SP SP SP-1 AJMP ADDR ABSOLUTE JUMP IT TRANSFERS THE PROGRAM EXECUTION TO THE INDICATED ADDRESS OBTAINED BY SUCCESSIVELY CONCATENATING THE FIVE HIGH ORDER BITS OF THE INCREAMENTED PC, OPCODE BITS 7-5, AND SECOND BYTE OF THE INSTRUCTION. THE SUBROUTINE MUST BE WITHIN THE SAME 2K BLOCK OF THE PROGRAM MEMORY. PC PC+2 PC (10-0) PAGE ADDRESS
- 40. LJMP ADDR 16 IT CAUSES AN UNCONDITIONAL BRANCH TO THE INDICATE ADDRESS. NO FLAGS AFFECTED. PC ADDR 15-0 SJMP REL. SHORT JUMP PROGRAM CONTROL BRANCHES UNCONDITIONALY TO THE ADDRESS INDICATED. THE BRANCH DESTINATION IS COMPUTED BY ADDING THE SIGNED DISPLACEMENT IN THE SECOND INSTRUCTION BYTE TO THE PC, AFTER INCREMENTING THE PC TWICE. PC PC+2 PC PC+REL JMP @A+DPTR JUMP INDIRECT 8 BIT UNSIGNED CONTENTS OF THE ACCUMULATOR ARE ADDED TO THE 16 BIT DATA POINTER AND THE RESULTINFG SUM IS LOADED TO THE PROGRAM COUNTER
- 41. ADDRESSING MODE ADDRESSING MODE DEFINITION EXAMPLE (8086) EXAMPLE (8051) IMMEDIATE ADDRESSING MODE DATA IS GIVEN IN THE INSTRUCTION ITSELF MOV AX, 05 MOV A, #05 DIRECT ADDRESSING MODE MEMORY ADDRESS IS GIVEN DIRECTLY IN THE INSTRUCTION ITSELF MOV AX, [05] MOV A,05 REGISTER ADDRESSING MODE BOTH SOURCE AND DESTINATION OPERANDS ARE REGISTERS MOV AX,BX MOV A,B REGISTER INDIRECT ADDRESSING MODE OFFSET ADDRESS IS SPECIFIED THROUGH POINTER REGISTER OR INDEX REGISTER MOV AL,(BP) XOR (DI),CL MOV A,@R0 BASE PLUS INDEX REGISTER ADDRESSING MODE BASE REGISTER AND NDEX REGISTER ARE USED TO ACCESS DATA INDIRECTLY. MOV (BX + DI),AL ADDRESS IS LOCATED AS ((DS X 10)+(BX+DI) AL NIL REGISTER RELATIVE ADDRESSING MODE OFFSET IS CALCULTAED USING BASE REGISTER OR INDEX REGISTER PLUS DISPLACEMENT MOV AX,(DI +06) AX ((DS X 10)+(DI+06) NIL BASE PLUS INDEX REGISTER RELATIVE ADDRESS OF OPERAND IS CALCULTAED BASE MOV (BX+DI+2),CL NIL
- 42. ADDRESSING MODE REGISTER PLUS INDEX REGISTER PLUS DISPLACEMENT STRING ADDRESSING MODE ACCESSING STRING OPERANDS MOV SB NIL REGISTER SPECIFIC ADDRESSING MODE SPECIFC REGISTERS SUCH AS ACCUMULATORS ARE INVOLVED NIL SWAP A INDEX PROGRAM CAN BE ACCESSED USING EITHER DPTR OR PC INDEX REGISTERS NIL MOVC A, @A+DPTR STACK ADDRESSING MODE STACK INSTRUCTIONS SUCH AS PUSH AND POP ARE INVOLVED NIL PUSH 04 (R4) ADDRESS OF REGISTERS NEED TO BE GIVEN PUSH 06(R6)