8086_architecture MMC PPT.ppt

Block diagram of Digital Computer

Functions performed by Microprocessor
All the functions performed by microprocessors are
broadly divided into three categories:
1. Microprocessor Initiated operations
2. Internal data operations
3. Externally or peripheral initiated operations
3

Microprocessor Initiated operations
 Memory Read
 Memory write
 I/O Read
 I/O write

Communication
For communicating with memory and Input/output
devices microprocessor has to follow these steps:
1. Identify the memory location of memory or port
address of peripheral.
2. Send Control Signal.
3. Actual communication of data or information.

Internal Data Operations
1. Store data bits internally.
2. Perform arithmetic and logical operations.
3. Test for conditions.
4. Sequence the execution of instructions.
5. Store data temporarily during execution in the defined
R/W memory locations called the stack.

Internal Data Operations
To perform these operations, the microprocessor
requires registers, an arithmetic logic unit (ALU) and
control logic, and internal buses (path for information
flow).

Accumulator
 The accumulator is an 8-bit register that is part of the
arithmetic logic unit (ALU).
 This register is used to store 8-bit data and to perform
arithmetic and logical operations.
 The result of an operation is stored in the
accumulator. The accumulator is also identified as
register A.

Flags
 The ALU includes five flip-flops that are set or reset
according to data conditions in the accumulator and
other registers.
 The microprocessor uses them to perform the third
operation; namely testing for data conditions.

Program Counter (PC)
 This 16 bit register deals with the fourth operation,
sequencing the
execution of instructions. This register is a memory
pointer.
 Memory locations have 16-bit address, and that is why this
is a 16-bit register.
 The microprocessor uses this register to sequence the
execution of instructions. The function of the program
counter is to point to the memory address from which the
next byte is to be fetched.
 When a byte (machine code) is being fetched the program
counter is incremented by one to point to the next memory
location.

Stack Pointer (SP)
 The stack pointer is also a 16-bit register used as a
memory pointer; initially, it will be called the stack
pointer register to emphasize that it is a register.
 It is pointer of a memory location in R/W memory,
called the stack.
 The beginning of the stack is defined by loading a 16-
bit address in the stack pointer (register).

Externally Initiated Operations
1. READY
2. RESET
3. INTERRUPTS
4. HOLD/ HLDA

History
 Microprocessor journey started with a 4-bit processor called
4004; it was made by Intel Corporation in 1971.
 It was 1st single chip processor. Then the idea was extended
to 8-bit processors like 8008, 8080 and then 8085 (all are
Intel products).
 8085 was a very successful one among the 8-bit processors;
however its application is very limited because of its slower
computing speed and other quality factors.

INTRODUCTION
8086 is an enhanced version of 8085 that has been developed by
Intel in 1976.
It is a 16 bit Microprocessor. It has a powerful instruction set and it
is capable to providing multiplication and division operations
directly. It has 20 address lines and 16 data lines. So it can access
up to 1 MB of memory.
It supports two modes of operation: first is maximum mode and
second is minimum mode. Minimum mode is applicable for system
that has a single processor and maximum mode is used for the
multiprocessor system.

Features of 8086
1. 8086 is a 40 pin IC.
2. It is a 16-bit processor.
3. Its operating voltage is 5 volts.
4. Its operating frequency is 5 MHz
5. Total memory addressing capacity is 1MB (external).
6. It has 16-bit data bus and 20-bit address bus.
7. It has fourteen 16-bit registers.
8. Higher throughput (speed): Throughput is a measure of
total units of information a system can process in a given
amount of time .

Block Diagram of Intel 8086
 The 8086 CPU is divided into two independent functional
units:
 Bus Interface Unit (BIU)
 Execution Unit (EU)

Bus Interface Unit (BIU)
The function of BIU is to:
 Fetch the instruction or data from memory
 Write the data to memory
 Write the data to the port
 Read data from the port

Execution Unit (EU)
The functions of execution unit are:
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
The EU contains the control circuitry to perform various
internal operations.

Software Model of the 8086 Microprocessors
22

8086 Registers
23
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX

General Purpose Registers
 Normally used for storing temporary results
 Each of the registers is 16 bits wide (AX, BX, CX, DX)
 Can be accessed as either 16 or 8 bits AX, AH, AL
24
AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest
Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX
– Base Register
– Also serves as an address register
25

• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations
• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations
26

Pointer and Index Registers
• All 16 bits wide, L/H bytes are not accessible
• Used as memory pointers
– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained
in register SI to register AH
• IP is not under direct control of the programmer
27

Flag Register
28
Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign
6 are status flags
3 are control flag

8086 Programmer’s Model
29
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EU registers

The Stack
• The stack is used for temporary storage of information
such as data or addresses.
• When a CALL is executed, the 8086 automatically
PUSHes the current value of CS and IP onto the stack.
 Other registers can also be pushed
 Before return from the subroutine, POP instructions
can be used to pop values back from the stack into the
corresponding registers.
30

INTEL 8086 - Pin Details
33
Ground
Clock
Power Supply
5V  10%
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
clks

34
Address/Data Bus:
Contains address
bits A15-A0 when ALE
is 1 & data bits D15 –
D0 when ALE is 0.
Address Latch Enable:
When high,
multiplexed
address/data bus
contains address
information.

35
INTERRUPT
Non - maskable
interrupt
Interrupt request
Interrupt
acknowledge

36
Direct
Memory
Access
Hold
acknowledge
Hold

37
Address/Status Bus
Address bits A19 –
A16 & Status bits S6
– S3

38
Bus High Enable/S7
Enables most
significant data bits
D15 – D8 during read
or write operation.
S7: Always 1.
BHE#, A0:
0,0: Whole word
(16-bits)
0,1: High byte
to/from odd address
1,0: Low byte
to/from even address
1,1: No selection

39
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins

Minimum Mode- Pin Details
40
Read Signal
Write Signal
Memory or
I/0
Data Bus
Enable
Data
Transmit/Receive

Maximum Mode - Pin Details
41
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
S2 S1 S0
000: INTA’
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive

42
DMA
Request/Grant
Lock Output
Lock Output
Used to lock peripherals
of the system
Activated by using the
LOCK: prefix on any
instruction

43
Queue Status
Used by numeric
coprocessor (8087)
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode

PHYSICAL MEMORY PARTITIONING
44

READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.

‘Read’ Cycle timing Diagram for Minimum Mode
48

‘Write’ Cycle timing Diagram for Minimum Mode
49

Maximum Mode 8086 System
 Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.
 The Memory, Address Bus, Data Buses are shared resources
between the two processors.
 The control signals for Maximum mode of operation are
generated by the Bus Controller chip 8788.
 The three status outputs S0*, S1*, S2* from the processor are
input to 8788.
 The outputs of the bus controller are the Control Signals,
namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE
etc.
51

Memory Read timing in Maximum Mode
52

Memory Write timing in Maximum Mode
53

1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
Instruction Set
55
8086 supports 6 types of instructions.

Data Transfer Instructions
56
8086 Microprocessor
Instructions that are used to transfer data/ address in to registers,
memory locations and I/O ports.
Generally involve two operands: Source operand and Destination
operand of the same size.
Source: Register or a memory location or an immediate data
Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit
data can be moved to 16-bit register/ memory.

57
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1
MOV mem, reg1
MOV reg2, mem
(reg2)  (reg1)
(mem)  (reg1)
(reg2)  (mem)
MOV reg/ mem, data
MOV reg, data
MOV mem, data
(reg)  data
(mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1
XCHG mem, reg1
(reg2)  (reg1)
(mem)  (reg1)

58
PUSH reg16/ mem
PUSH reg16
PUSH mem
(SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
(SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg16/ mem
POP reg16
POP mem
MA S = (SS) x 1610 + SP
(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
MA S = (SS) x 1610 + SP
(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2

59
IN A, DX
IN AL, DX
IN AX, DX
PORTaddr = (DX)
(AL)  (PORT)
PORTaddr = (DX)
(AX)  (PORT)
IN A, addr8
IN AL, addr8
IN AX, addr8
(AL)  (addr8)
(AX)  (addr8)
OUT DX, A
OUT DX, AL
OUT DX, AX
PORTaddr = (DX)
(PORT)  (AL)
PORTaddr = (DX)
(PORT)  (AX)
OUT addr8, A
OUT addr8, AL
OUT addr8, AX
(addr8)  (AL)
(addr8)  (AX)

Arithmetic Instructions
60
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADD reg2, reg1
ADD reg2, mem
ADD mem, reg1
(reg2)  (reg1) + (reg2)
(reg2)  (reg2) + (mem)
(mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data
ADD mem, data
(reg)  (reg)+ data
(mem)  (mem)+data
ADD A, data
ADD AL, data8
ADD AX, data16
(AL)  (AL) + data8
(AX)  (AX) +data16

61
ADC reg2/ mem, reg1/mem
ADC reg2, reg1
ADC reg2, mem
ADC mem, reg1
(reg2)  (reg1) + (reg2)+CF
(reg2)  (reg2) + (mem)+CF
(mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data
ADC mem, data
(reg)  (reg)+ data+CF
(mem)  (mem)+data+CF
ADDC A, data
ADD AL, data8
ADD AX, data16
(AL)  (AL) + data8+CF
(AX)  (AX) +data16+CF

62
SUB reg2/ mem, reg1/mem
SUB reg2, reg1
SUB reg2, mem
SUB mem, reg1
(reg2)  (reg1) - (reg2)
(reg2)  (reg2) - (mem)
(mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data
SUB mem, data
(reg)  (reg) - data
(mem)  (mem) - data
SUB A, data
SUB AL, data8
SUB AX, data16
(AL)  (AL) - data8
(AX)  (AX) - data16

63
SBB reg2/ mem, reg1/mem
SBB reg2, reg1
SBB reg2, mem
SBB mem, reg1
(reg2)  (reg1) - (reg2) - CF
(reg2)  (reg2) - (mem)- CF
(mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data
SBB mem, data
(reg)  (reg) – data - CF
(mem)  (mem) - data - CF
SBB A, data
SBB AL, data8
SBB AX, data16
(AL)  (AL) - data8 - CF
(AX)  (AX) - data16 - CF

64
INC reg/ mem
INC reg8
INC reg16
INC mem
(reg8)  (reg8) + 1
(reg16)  (reg16) + 1
(mem)  (mem) + 1
DEC reg/ mem
DEC reg8
DEC reg16
DEC mem
(reg8)  (reg8) - 1
(reg16)  (reg16) - 1
(mem)  (mem) - 1

65
MUL reg/ mem
MUL reg
MUL mem
For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AL) x (mem8)
For word : (DX)(AX)  (AX) x
(mem16)
IMUL reg/ mem
IMUL reg
IMUL mem
For byte : (AX)  (AL) x (reg8)
For word : (DX)(AX)  (AX) x (reg16)
For byte : (AX)  (AX) x (mem8)
For word : (DX)(AX)  (AX) x
(mem16)

66
DIV reg/ mem
DIV reg
DIV mem
For 16-bit :- 8-bit :
(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder
(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

67
IDIV reg/ mem
IDIV reg
IDIV mem
(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder
(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

68
CMP reg2/mem, reg1/
mem
CMP reg2, reg1
CMP reg2, mem
CMP mem, reg1
Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0
If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0
If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0
If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

69
8086 Microprocessor
CMP reg/mem, data
CMP reg, data
CMP mem, data
Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0
If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0
If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

70
CMP A, data
CMP AL, data8
CMP AX, data16
Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0
If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0
If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

Logical Instructions
71
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

Logical Instructions
72
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

String Manipulation Instructions
73
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison, scan, load and
store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW. S represents
string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and that of the
destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

74
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE
(Repeat CMPS or SCAS
until ZF = 0)
REPNZ/ REPNE
(Repeat CMPS or SCAS
until ZF = 1)
While CX  0 and ZF = 1, repeat execution
of string instruction and
(CX)  (CX) – 1
While CX  0 and ZF = 0, repeat execution
of string instruction and
(CX)  (CX) - 1

75
MOVS
MOVSB
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

76
CMPS
CMPSB
CMPSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0
If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation
For word operation
Compare two string byte or string word

77
SCAS
SCASB
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0
If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0
If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Scan (compare) a string byte or word with accumulator

78
LODS
LODSB
LODSW
MA = (DS) x 1610 + (SI)
(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1
If DF = 1, then (SI)  (SI) – 1
MA = (DS) x 1610 + (SI)
(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2
If DF = 1, then (SI)  (SI) – 2
Load string byte in to AL or string word in to AX

79
STOS
STOSB
STOSW
MAE = (ES) x 1610 + (DI)
(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1
If DF = 1, then (DI)  (DI) – 1
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2
If DF = 1, then (DI)  (DI) – 2
Store byte from AL or word from AX in to string

Mnemonics Explanation
STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode
mem/ reg
Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086
LOCK Lock bus during next instruction
Processor Control Instructions
80

Control Transfer Instructions
81
Transfer the control to a specific destination or target instruction
Do not affect flags
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/
disp16
Unconditional jump
 8086 Unconditional transfers

82
 8086 signed conditional
branch instructions
 8086 unsigned conditional branch
instructions
Checks flags
If conditions are true, the program control is transferred to the
new memory location in the same segment by modifying the
content of IP

83
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JG disp8
Jump if greater
JNLE disp8
Jump if not less or
equal
JGE disp8
Jump if greater than
or equal
JNL disp8
Jump if not less
JL disp8
Jump if less than
JNGE disp8
Jump if not greater
than or equal
JLE disp8
Jump if less than or
equal
JNG disp8
Jump if not greater
 8086 signed conditional
branch instructions
 8086 unsigned conditional branch
instructions
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JA disp8
Jump if above
JNBE disp8
Jump if not below or
equal
JAE disp8
Jump if above or
equal
JNB disp8
Jump if not below
JB disp8
Jump if below
JNAE disp8
Jump if not above or
equal
JBE disp8
Jump if below or
equal
JNA disp8
Jump if not above

84
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 0
 8086 conditional branch instructions affecting individual flags

Memory mapping vs. I/O mapping
85

Addressing Modes
87
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted in an instruction
are known as addressing modes.

Register Addressing Modes
88
The instruction will specify the name of the register which holds the data to
be operated by the instruction.
Example:
MOV CL, DH
The content of 8-bit register DH is moved to another 8-bit register CL
(CL)  (DH)

Immediate Addressing
89
In immediate addressing mode, an 8-bit or 16-bit data is specified as part of the
instruction
Example:
MOV DL, 08H
The 8-bit data (08H) given in the instruction is moved to DL
(DL)  08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is moved to AX register
(AX)  0A9FH

Direct Addressing
90
Here, the effective address of the memory location at which the data operand is
stored is given in the instruction.
The effective address is just a 16-bit number written directly in the instruction.
Example:
MOV BX, [1354H]
MOV BL, [0400H]
The square brackets around the 1354H denotes the contents of the memory location.
When executed, this instruction will copy the contents of the memory location into
BX register.
This addressing mode is called direct because the displacement of the operand from
the segment base is specified directly in the instruction.

Register Indirect Addressing
91
In Register indirect addressing, name of the register which holds the effective address
(EA) will be specified in the instruction.
Registers used to hold EA are any of the following registers: BX, BP, DI and SI.
Content of the DS register is used for base address calculation.
Example: MOV CX, [BX]
Operations:
EA = (BX)
BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
Note : Register/ memory
enclosed in brackets refer to
content of register/ memory

Based Addressing
92
In Based Addressing, BX or BP is used to hold the base value for effective address and a signed 8-bit or
unsigned 16-bit displacement will be specified in the instruction.
In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value.
When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is used.
Example:
MOV AX, [BX + 08H]
Operations:
0008H  08H (Sign extended)
EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA), (AH)  (MA + 1)

Indexed Addressing
93
SI or DI register is used to hold an index value for memory data and a signed 8-bit or unsigned 16-bit
displacement will be specified in the instruction.
Displacement is added to the index value in SI or DI register to obtain the EA.
In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value.
Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA + 1)

Based Indexed Addressing
94
In Based Index Addressing, the effective address is computed from the sum of a base
register (BX or BP), an index register (SI or DI) and a displacement.
Example:
MOV DX, [BX + SI + 0AH]
Operations:
000AH  0AH (Sign extended)
EA = (BX) + (SI) + 000AH
BA = (DS) x 1610
MA = BA + EA
(DX)  (MA) or,
(DL)  (MA), (DH)  (MA + 1)

String Addressing
95
Employed in string operations to operate on string data.
The effective address (EA) of source data is stored in SI register and the EA of destination is stored in
DI register.
Segment register for calculating base address of source data is DS and that of the destination data is ES
Example: MOVS BYTE
Operations:
Calculation of source memory location:
EA = (SI) BA = (DS) x 1610 MA = BA + EA
Calculation of destination memory location:
EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
(MAE)  (MA)
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1

I/O Port Addressing
These addressing modes are used to access data from standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port address is directly specified in the instruction.
Example: IN AL, [09H]
Operations: PORTaddr = 09H
(AL)  (PORT) Content of port with address 09H is moved to AL register
In indirect port addressing mode, the instruction will specify the name of the register which
holds the port address. In 8086, the 16-bit port address is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port whose address is specified by DX register.
96

Relative Addressing
97
In this addressing mode, the effective address of a program instruction is specified relative
to Instruction Pointer (IP) by an 8-bit signed displacement.
Example: JZ 0AH
Operations:
000AH  0AH (sign extend)
If ZF = 1, then
EA = (IP) + 000AH
BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to new address calculated above.
If ZF = 0, then next instruction of the program is executed.

Implied Addressing
98
Instructions using this mode have no operands. The instruction itself will specify the
data to be operated by the instruction.
Example: CLC
This clears the carry flag to zero.

Addressing Modes : Memory Access
100

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