A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
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The document discusses a 100 MHz–2 GHz closed-loop analog in-phase/quadrature correction circuit designed for digital clock generation in a 130-nm CMOS process. It achieves phase error correction within 1.5° at 1 GHz and 3° at 2 GHz, consuming 5.4 mA from a 1.2 V supply, with a compact active area of 102μm×95μm. The architecture addresses duty cycle distortion and has been validated in two applications.
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A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
- 1. A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS ABSTRACT: A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked loop- type architecture for quadrature error correction. The circuit corrects the phase error to within a1.5°upto1GHzandtowithin3°at2GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-µm mixed-mode CMOS with an active area of 102µm×95µm. The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool. SOFTWARE IMPLEMENTATION: Tanner tool