A 12 bit 40-ms s sar adc with a fast-binary-window dac switching scheme

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A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching
Scheme
Abstract:
This paper presents a 12-bit 40-MS/s successive approximation register analog-to-digital
converter (ADC) for ultrasound imaging systems. By incorporating a fast binary window
digital-to-analog converter (DAC) switching technique, the problematic most significant
bit transition glitch was removed to improve linearity without increasing the input
capacitance or using a calibration scheme. A hybrid DAC was also developed to
overcome the yield problem that occurs when a tiny unit capacitance is used in the DAC.
Moreover, a reference buffer was used to accelerate the DAC settling to achieve high
speed conversion. The prototype ADC was fabricated using a 130-nm CMOS technology.
The ADC core occupied an active area of 0.1 mm 2
and consumed a total power of 1.32
mW when a 1.2-V supply was used at a conversion rate of 40 MS/s. The measured peak
signal-to-noise-and-distortion ratio and spurious free dynamic range were 64 and 77.5
dB, respectively. The peak effective number of bits was 10.33, which is equivalent to a
Walden figure-of-merit of 25.6 fJ/conversion step.
Software Implementation:
 TANNER EDA
Existing System:
Currently, the advantages of successive approximation register (SAR) analog-to-digital
converters (ADCs) have been demonstrated to include high energy efficiency and small
footprints through the use of thin CMOS technologies. Internal digital-to-analog
converters (DACs) play a crucial role in realizing linearity in high-resolution SAR ADCs.
Most SAR ADCs use capacitor DACs (C-DACs) to maintain high accuracy and fast

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operation. In SAR ADCs, capacitor arrays are used for both track-and-hold and DAC
operations. The total capacitance of C-DACs determines the accuracy of the ADC. In
general, a high total capacitance can meet both noise and DAC linearity requirements
However, input and reference buffers consume a substantial amount of power. Therefore,
developing methods for reducing total capacitance is crucial for facilitating the
integration of ADCs into low-power electronics. Several techniques have been proposed
to further reduce the total capacitance of C-DACs. Capacitor calibration compensates for
the capacitor mismatch in C-DACs. Calibration schemes are designed to correct errors by
using digital post processing at the cost of additional power consumption. A capacitor-
swapping SAR ADC was employed to improve the DAC linearity by interchanging half
of the total capacitance with the other half. The complementary error caused by the most
significant bit (MSB) capacitor switching was randomly swapped to reduce the third-
order harmonic distortion. The spurious-free dynamic range (SFDR) was effectively
enhanced; however, the signal-to-noise-and distortion ratio (SNDR) was not improved
because the errors due to the capacitor mismatch were not eliminated. In two additional
comparators were used with programmable threshold levels for the first four window
comparisons. Moreover, the subsequent conversion cycles used another main comparator.
However, the offset deviation among these three comparators introduced additional
errors, and the programmable threshold levels required additional precision circuits. In a
two-step decision (TSD) SAR ADC was proposed to provide a smaller window and
compensate for the DAC settling error. However, the use of 23 cycles to implement a 12-
bit SAR ADC limited the operation speed of the ADC. Finally, in a previously proposed
binary window (BW) SAR ADC was proposed to linearize the DAC linearity. However,
four additional conversion cycles were used to reduce the operation speed.
This paper presents a fast BW (FBW) DAC switching technique to implement a 12-bit
40-MS/s SAR ADC by using a 130-nm CMOS technology. Fig. 1 shows The 12-bit SAR
ADC using a conventional DAC switching scheme. The proposed FBW DAC switching

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scheme contains the same window function as that in and achieves a faster operating
speed. In contrast, the proposed scheme utilizes only one additional conversion cycle to
implement the window function the SNDR loss due to the capacitor mismatch. Fig. 2.
shows Least favorable SNDR versus the unit capacitance of a binary C-DAC (capacitor
array consisting of 2 11
unit capacitors).
Fig. 1. The 12-bit SAR ADC using a conventional DAC switching scheme.

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Fig. 2. Least favorable SNDR versus the unit capacitance of a binary C-DAC (capacitor array consisting
of 2 11
unit capacitors).
Disadvantages:
 Less Energy Efficiency
 Less speed conversion
Proposed System:
Proposed ADC Architecture
Fig. 3 shows the Proposed FBW-SAR DAC switching operation flowchart and Fig. 4
displays the proposed FBW-SAR ADC architecture. The ADC consists of a differential
bootstrapping switch, a hybrid DAC with a reference buffer, a dynamic comparator, and
an FBW-SAR controller. To suppress the bonding wire effect, a pseudo-differential input
buffer is applied to operate this ADC. A self-timed clocking scheme is used to accelerate

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Fig. 3. Proposed FBW-SAR DAC switching operation flowchart
Fig. 4. Proposed FBW-SAR ADC architecture.

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the ADC conversion and avoid the need for a high-frequency clock source. A differential
bootstrap switch is applied to maintain an SFDR of more than 85 dB. After the first five
bits, b0, b1, b2, b3, and b4, are determined using the window conversion cycles, the
following LSB conversion cycles use the monotonic switching scheme to yield the
remaining output bits, b4C, b5,..., b10C, b11.
Moreover, b4C and b10C, which are redundant bits, are used to compensate for DAC
settling errors. Finally, a digital error correction encoder is applied to generate the 12-bit
ADC output DO. As displayed in Fig. 4, two capacitor banks—CP and CN— are used for
a differential operation. In this paper, the p-terminal capacitor array is selected. The split-
capacitor architecture is applied to maintain a small common-mode voltage variation.
Each of the first four MSB capacitors (CP1–CP4) is divided into two small, equal
capacitors (e.g., CP1a = CP1b = CP1/2) to maintain a favorable SFDR and simplify the
DAC control signals. To avoid the need for full-binary capacitor arrays, a hybrid DAC
was proposed to reduce the total capacitance from 2048 to 140 C. A multiple reference
buffer is proposed to reduce the ratio between the MSB and LSB capacitors.
The details of the DAC are presented. A 50% duty ratio clock signal (CK) was used to
simplify the clock generation circuit. To mitigate the process, supply voltage, and
temperature (PVT) variations, an adaptive sampler was utilized to automatically adjust
the duty ratio of the sampling clock, cks. When the last conversion cycle is completed, a
flag is enabled to trigger the rising edge of cks. The falling edge of cks is controlled by
the falling edge of CK. At the worst PVT variation condition (SS, 1.15 V, and 125 °C),
the duty ratio of cksis reduced to 30%, as revealed by the
Table I
Window - SAR ADC comparison

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Fig. 5. Dynamic comparator schematic
simulation results. The short tracking time causes less than 1.5 dB SNDR loss at the
Nyquist rate.
Window-SAR ADC Comparison
Two window switching schemes have been proposed for SAR ADCs. Table I
summarizes the results obtained after comparing four DAC switching schemes by
behavior simulation results. Here, the conventional switching scheme is used as a basis.
The TSD-SAR DAC switching scheme uses 11 additional conversion cycles to
implement a 12-bit SAR ADC. The INL and SNDR of the TSD-SAR DAC switching
scheme are improved by 13% and 1.3 dB, respectively, compared with those of the
conventional DAC switching scheme. The BW-SAR DAC switching scheme uses four
additional conversion cycles to implement a 12-bit SAR ADC. Moreover, the INL and

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SNDR of the BW-SAR DAC are improved by 30% and 3 dB, respectively. In this paper,
the proposed FBW-SAR DAC switching scheme uses only one additional cycle to
implement a 12-bit SAR ADC and obtains the same SNDR as that of the BW-SAR ADC.
Compared with the conventional SAR ADC, the FBW-SAR ADC exhibits better linearity
and SNDR.
Circuit implementation
Dynamic Comparator
The comparator was designed to satisfy both noise and speed requirements. Fig. 5
presents the circuit schematic of the dynamic comparator employed in this paper. This
circuit is similar to that in, but with the following modifications. The comparator
comprises a dynamic preamplifier, a dynamic latch, and a ready circuit to yield the self-
timed signal Rdy. The preamplifier uses a p-type input pair to enable the use of a low
final common-mode voltage. However, the comparator encounters a slight speed
reduction. The constant current operation (Ma) is used to compensate for the dynamic
offset due to the monotonic switching during the last 8-bit conversion cycles. On the
basis of the simulation results, the dynamic offset is only 0.37 mV during the SA process.
The wrong decision caused by the residual dynamic offset can be compensated by the
second redundant bit. The reset transistor (Mb) is used for eliminating the memory effect
between comparisons. The transistor also maintains a constant comparator input
capacitance at the sampling phase in the full-scale input range. In this paper, the
simulated input-referred noise was 0.31 mV · r/min, which is equivalent to 0.7 LSB. The
Monte Carlo simulation results reveal that the peak-to-peak offset voltage is 29 mV. The
simulation results reveal that the comparison delay range is from 270 to 520 ps for the
comparator input voltage at the typical PVT condition (TT, 1.2 V, and 27 °C). At the
worst PVT variation condition (SS, 1.15 V, and 125 °C), the comparison delay range is
from 320 to 850 ps.

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Advantages:
 High energy Efficiency
 High speed conversion
References:
[1] Z. Zhu, Z. Qiu, M. Liu, and R. Ding, ―A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power
scalable SAR ADC in 0.18 μm CMOS,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp.
689–696, Mar. 2015.
[2] W. Liu, P. Huang, and Y. Chiu, ―A 12 b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC
achieving over 90 dB SFDR,‖ in IEEE ISSCC Dig. Tech. Paper, Feb. 2010, pp. 380–381.
[3] A. H. Chang, H.-S. Lee, and D. Boning, ―A 12 b 50 MS/s 2.1 mW SAR ADC with redundancy and
digital background calibration,‖ in IEEE ESSCIRC Dig. Tech. Paper, Sep. 2013, pp. 109–112.
[4] T. Morie et al., ―A 71 dB-SNDR 50 MS/s 4.2 mW CMOS SAR ADC by SNR enhancement
techniques utilizing noise,‖ in IEEE ISSCC Dig. Tech. Paper, Feb. 2013, pp. 272–273.
[5] C. C. Lee, C.-Y. Lu, R. Narayanaswamy, and J. B. Rizk, ―A 12 b 70 MS/s SAR ADC with digital
startup calibration in 14 nm CMOS,‖ in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2015, pp. 62–63.
[6] C.-C. Liu, ―A 0.35 mW 12 b 100 MS/s SAR-assisted digital slope ADC in 28 nm CMOS,‖ in IEEE
ISSCC Dig. Tech. Paper, Feb. 2016, pp. 462–463.
[7] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, ―A 10-bit 50- MS/s SAR ADC with a
monotonic capacitor switching procedure,‖ IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740,
Apr. 2010.
[8] Y.-H. Chung, M.-H. Wu, and H.-S. Li, ―A 12-bit 8.47-fJ/conversion-step capacitor-swapping SAR
ADC in 110-nm CMOS,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 10–18, Jan. 2015.
[9] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, and C.-M. Huang, ―A 1 V 11 fJ/conversion-step 10
bit 10 MS/s asynchronous SAR ADC in 0.18 μm CMOS,‖ in Symp. VLSI Circuits Dig. Tech. Papers,
Jun. 2010, pp. 241–242.

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[10] Y.-H. Chung, C.-W. Yen, and M.-H. Wu, ―A 24-μW 12-b 1-MS/s SAR ADC with two-step
decision DAC switching in 110-nm CMOS,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.
24, no. 11, pp. 3334–3344, Nov. 2016.
[11] Y.-H. Chung, C.-W. Yen, and P.-K. Tsai, ―A 12-bit 10-MS/s SAR ADC with a binary-window
DAC switching scheme in 180-nm CMOS,‖ Int. J. Circuit Theory Appl., vol. 46, no. 4, pp. 748–763,
Apr. 2018. [Online]. Available: https://doi.org/10.1002/cta.2424.
[12] S.-W. M. Chen and R. W. Brodersen, ―A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm
CMOS,‖ IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006.
[13] C.-C. Liu et al., ―A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation,‖ in
IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386–387.

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