A high accuracy programmable pulse generator with a 10-ps timing resolution

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A High-Accuracy Programmable Pulse Generator With a 10-ps Timing
Resolution
Abstract:
Automatic test equipment must have high-precision and low-power pulse generators
(PGs) for testing memory and device-under-test ICs. This paper describes a high-
accuracy and wide-data-rate-range PG with a 10-ps time resolution. The PG comprises an
edge combiner (EC) and a multiphase clock generator (MPCG). The EC can produce an
arbitrary waveform through 32 phase outputs of the MPCG. The EC adopts a one/zero
detector and phase selection logic to define an operational data rate range and a timing
resolution, respectively. Therefore, the EC uses the phase selection logic to combine the
period window of the one/zero detector with the MPCG output phases. The EC also uses
a countdown counter for a wide operational range. In the MPCG, a multiphase oscillator
(MPO) adopts a ring oscillator scheme with sub feedback loops to extend its maximum
operational frequency. The MPO also uses a phase error corrector to reduce the output
phase error resulting from process and layout mismatches. Thus, the PG can obtain high
accuracy waveforms owing to small phase errors. The test chip was implemented using a
0.13-µm CMOS process. The core area and power consumption of the PG were measured
to be 250 × 300 µm2
and 18.7 mW, respectively. The data rate range of the PG was
determined to be from 3.2 kHz to 893 MHz. The time resolution and average accuracy of
the PG were measured to be 10 ps and ±0.3 LSB, respectively.
Software Implementation:
 Modelsim
 Xilinx 14.2
Existing System:

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Automatic test equipment (ATE) and measurement instruments are representative
examples of a chip tester. The core block of such test equipment is the timing formatter,
which is a pulse generator (PG), and can create patterns for test chips. Electronic test
equipment can generate arbitrary waveforms for the measurement of test chips. PGs are
often used to generate input signals for test chips; moreover, the PGs have a high time
resolution of less than 10 ps. However, such PGs are large instruments and are not
suitable for multichannel applications. PGs implemented by field-programmable gate
arrays (FPGAs) or systems on chips (SoCs) can be applied to some specific applications
such as multichannel signal inputs or low power consumption. Thus, developing a
superior-performance SoC-based chip tester is important for ATE. Integrated circuit (IC)-
based PGs are often used for IC testing. Thus, they facilitate determining the multi
channels and are suitable for specific applications. Therefore, the time resolution, in
addition to high accuracy, high data rate, and low power consumption, is an equally
important factor for this type of PG. The wide data rate range can be useful for all types
of test equipment applications. Moreover, an IC-type PG is easy to design for specific
applications. FPGAs are widely used in chip-testing equipment. The configuration of
FPGAs is typically programmed using a hardware description language.
FPGAs can be implemented and integrated with test equipment perfectly. FPGA-based
PGs can achieve a wide data rate range and multi channels. However, application-specific
ICs require high speed and low power consumption. Timing Vernier architectures are
adopted to obtain high linearity. Timing Vernier schemes can minimize the core area and
power for high speed operations. A phase-locked loop (PLL) and delay-locked loop
(DLL) have been proposed to reduce process, voltage, and temperature variations.
PLL/DLL-based PGs also operate at a high data rate of a few gigahertz. In an active noise
canceller was proposed to reduce supply noise. This PG adopts a fine delay cell to extend
the time resolution of 1.83 ps. The PG adopts time-to-digital converters (TDCs) to extend
the time resolution for high-speed applications. TDC-based PGs can achieve gigahertz

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operation with an enhanced time resolution. In coarse and fine stage schemes were
proposed to achieve a low-power PG. This paper proposes a PG with wide data rate range
and high timing accuracy for testing platforms. The proposed PG has a time resolution of
10 ps and a high-accuracy waveform. The operating frequency ranges from a few
kilohertz to hundreds of megahertz.
Disadvantages:
 Accuracy is lower
 Phase error corrector is not reduced
Proposed System:
Proposed pulse generator architecture
Fig. 1 shows the block and timing diagrams of the proposed PG. This PG comprises two
main circuits: an edge combiner (EC) and a multiphase clock generator (MPCG).

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Fig. 1. Block and timing diagrams of the proposed PG.
The EC can create arbitrary waveforms and comprises a phase selection logic, one/zero
detector, a least significant bit (LSB) register, load controller, multiplexer (MUX), and
divider. The MPCG defines the time resolution and creates edge signals. This MPCG is a
32-phase PLL scheme at 3.125 GHz (320 ps); thus, the time resolution of the PG is 10 ps,
serving as the phase resolution of the MPCG output. The multiphase outputs (P31:0) and
speed of the MPCG are important factors for determining the time resolution of the PG.
The EC combines the MPCG output phases to create an arbitrary waveform through the
controlled code (D24:0). The outputs of the LSB register and the phase selection logic are

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sent to the MUX to combine the output signal of the EC as E C out. The signal, Load, is
the clock signal for the FPGA memory, and the controlled code from the FPGA (D24:0)
is fed to the EC. Thus, the delay time between pulse signals can be defined through
D24:0. The signal, Event, can define the high or low levels of the PG output that depend
on the rising edge of E C out. For test platform applications, the Event is a testing pattern
for the test chip’s work function
Fig. 1 presents the timing diagram of the PG. When Start is high, the PG is activated and
begins operation. The controlled code (D24:0) defines the pulse delay time of the EC
output (E C out). The PG output (Event) from E C out is divided by 2. Thus, the two
rising edge signals (E C out) can define one PG output (Event). The maximum data rate
of the PG depends on the minimum pulse delay time between the two rising edge signals
of E C out. The signal, Load, can retime and read the controlled code, D24:5, to be the
one/zero detector input. The load controller also controls the operation of the PG. The
one/zero detector uses a countdown counter to count the controlled code, D24:5. The
countdown counter output, CD19:0, is also shown in Fig. 1. When the countdown counter
counts the last two LSB bits, the last bit is defined as the signal, Zero, and the second-last
bit is defined as the signal, One. The phase selection logic combines the period window
(One) of the one/zero detector and the output
Fig. 2. Block diagram of the one/zero detector

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Fig. 3. Circuitry of the one/zero controller.
hases (P31:0) of the MPCG. The one/zero detector counts the MPCG period through the
20-bit countdown counter. This detector can create the period window, which defines the
n-cycle time of the MPCG output. The phase selection logic can select the output phases
of the MPCG to be the inputs of the MUX (PS31:0). Then, the LSB register defines the
edge trigger signal through the LSB bits (D4:0). Thus, the time resolution of the PG is
defined as the phase resolution of the MPCG. To combine the selected output phases
(PS31:0) with the LSB register outputs (Sel31:0), the MUX output can be determined
through the controlled code (D24:0). Therefore, the EC output (EC out) is selected
depending on the phase selection logic and the LSB register outputs.
Proposed Edge Combiner
The proposed EC adopts the one/zero detector and phase selection logic to achieve a
small pulse delay time and a small time resolution error (TRE). Fig. 2 presents the block
diagram of the one/zero detector. The countdown counter sets the value of the controlled

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code, D24:5, to be the initial value of the counter. When the count of the countdown
counter is zero, the signals, One and Zero, are created to feed the phase selection logic
and the load controller. The counter input (Clk CD) can count the MPCG period (P0)
until the counter output (CD19:0) equals zero through the controlled code, D24:5. Fig. 3
shows the circuitry of the one/zero controller. This controller comprises two parts: an
MSB bit group and an LSB bit group. The MSB bit group (CD19:4) adopts an
asynchronous counter and can extend the maximum pulse delay time by increasing the bit
number of the countdown counter. This technique can extend the maximum pulse delay
time while maintaining the shortest latency delay. The LSB bit group (CD3:0) is a critical
path of the one/zero controller. If the counter output, CD19:0, is small, the signals, One
and Zero, must have a short delay time. Thus, their delay path must be as short as
possible. The signals CD1 and

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Fig. 4. Circuitry of the countdown counter
CD0 are defined as One and Zero, respectively. The clock signal (ClkCD) is defined
through the MPCG output (P0) and Zero. The signal Zero also defines the signals Load,
Load OZD, and Load LSB. The falling edge of Load must be slower than that of CD4 to
maintain the PG functions, as shown in the simulated results in Fig. 3. Fig. 4 shows the
circuitry of the countdown counter. To ensure timing issues of PG’s operation, CD1 and
CD0 must use the synchronous counter, ensuring that CD1 and CD0 have the same delay
time. This counter adopts a countdown mode; it can always count to ―one‖ and ―zero.‖
Consequently, the EC can start functioning before ―zero.‖ In this paper, the EC chooses

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to count to ―one‖ and the pulse delay time can be short. The countdown counter can adopt
the asynchronous counter to extend the maximum pulse delay time without increasing the
latency delay time.
Advantages:
 Accuracy is higher
 Phase error corrector is reduced.
References
[1] Tektronix. (2016). Arbitrary Waveform Generators-AWG4000 Series Datasheet. [Online].
Available: http://tw.tek.com/sites/tek.com/files/media/media/resources/AWG4000-Arbitrary-Waveform-
GeneratorsDatasheet-76W602550_2.pdf
[2] Agilent Technologies. (2009). Agilent 81100 Family of Pulse Pattern Generators. [Online].
Available: http://literature.cdn.keysight.com/ litweb/pdf/5980-1215E.pdf
[3] Tektronix. (2012). Arbitrary Waveform Generators—AWG5000 Series Datasheet. [Online].
Available: http://tw.tek.com/sites/tek.com/files/ media/media/resources/76W_22260_9.pdf
[4] SRS Stanford Research Systems. (2006). DG535 Digital Delay and Pulse Generator. [Online].
Available: http://www.thinksrs.com/ downloads/PDFs/Catalog/DG535c.pdf
[5] Analog Devices. (2007). Quad Pin Timing Formatter-ADATE207. [Online]. Available:
http://www.analog.com/media/en/technicaldocumentation/data-sheets/ADATE207.pdf
[6] M. Goto, J. O. Barnes, and R. E. Owens, ―CMOS programmable delay Vernier,‖ Hewlett-Packard J.,
vol. 45, pp. 51–58, Oct. 1994.
[7] L. Miari, S. Antonioli, I. Labanca, M. Crotti, I. Rech, and M. Ghioni, ―Eight-channel fully adjustable
pulse generator,‖ IEEE Trans. Instrum. Meas., vol. 64, no. 9, pp. 2399–2408, Sep. 2015.
[8] P. Chen, P. Y. Chen, J. S. Lai, and Y. J. Chen, ―FPGA Vernier digital-totime converter with 1.58 ps
resolution and 59.3 minutes operation range,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6,
pp. 1134–1142, Jun. 2010.

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[9] J. Kohno, T. Akiyama, D. Kato, and M. Imamura, ―A high linearity compact timing Vernier for
CMOS timing generator,‖ in Proc. IEEE Int. Test Conf., Nov. 2010, pp. 1–8.
[10] B. Arkin, ―Realizing a production ATE custom processor and timing IC containing 400
independent low-power and high-linearity timing verniers,‖ in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 348–349.

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