Design of a unified timing signal generator (utsg) for pulsed radar

International Journal of Electronics and Communication Engineering & TechnologyAND
INTERNATIONAL JOURNAL OF ELECTRONICS (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), (IJECET)
COMMUNICATION ENGINEERING & TECHNOLOGY © IAEME

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 3, Issue 1, January- June (2012), pp. 252-261
IJECET
© IAEME: www.iaeme.com/ijecet.html
Journal Impact Factor (2011): 0.8500 (Calculated by GISI)
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DESIGN OF A UNIFIED TIMING SIGNAL GENERATOR (UTSG)
FOR PULSED RADAR

Sanjay M Trivedi
Scientist/Engineer, Space Applications Centre,
Ahmedabad 380 015, India. Ph . 079-26915235,
Email: sanjay@sac.isro.gov.in
B. S. Raman
Scientist/Engineer, Space Applications Centre,
Ahmedabad 380 015, India. Email : bsraman@sac.isro.gov.in
Pinal Engineer
Assistant Professor, Sardar Vallabhbhai National Institute of Technology Surat,
India, Email :pinalengineer@gmail.com
Dr. Mihir Shah
Assistant Professor, Vishvakarma Govt. Engg.College Chandkheda,
Ahmedabad, India. Email: mihirec@gmail.com

ABSTRACT
This paper presents the design of a software defined hardware module called Unified
Timing Signal Generator (uTSG) for pulsed RADAR (Radio Detection and Ranging). It is a
digital programmable multifunction timer generating timings for pulsed radar control
applications and is developed using VHDL, Xilinx FPGA (XCV300) being the primary
targeted implementation frontend. The tools used for building and testing the software
modules are Xilinx ISE 10.1i and ModelSim XE III 6.3c. A test bench was written
to generate golden references. The design was evolved, translated into the target hardware
and the timing performance captured on oscilloscope and correlated successfully with the
golden references.
Keywords: FPGA, VHDL, RADAR, PRI, FSM, uTSG.

252

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME

I. INTRODUCTION
Any modern pulsed RADAR has the following basic functions for which control timings
with a reference marker need to be generated [1]:
1. Transmission of a pulse of electromagnetic waves of a chosen description in terms of
say frequency or bandwidth and power level, during a designated time slot, and
repeating the same at designated repetition interval (PRI).
2. Receiving the radar echo and quantizing the same in a time window with a precisely
defined timing relationship with the transmitted pulse.
3. Transmit / Receive of any intra-PRI calibration timing pulses as identified in the
requirements.
4. In case of beam-steered antennas, beam switching signals would be required.

These requirements have been met traditionally by either dedicated functional code or by
custom logic design (implemented either in programmable logic blocks or by discreet logic
elements). Most controllers of such applications now-a-days sport FPGAs or other
programmable logic [2]. An elegant and methodical approach to the above timing
requirement would be a generic configurable hardware timing generator realized in a FPGA.
Such a ‘software defined hardware’ timing block would provide flexibility and
customization and yet be a generic entity covering all type of timing generation
requirements. It will be a platform independent module readily available for integration
into various hardware defining environments thereby speeding up the design process.
Several architectures [2] [3] [6] may be possible for basic timing signal generation
however they cannot cover all requirements. This paper develops one such unified generic
timing unit, uTSG using a delayed-mono stable pulse generator as the core logical
building block using VHDL[(Very High Speed Integrated Circuit) Hardware
Description Language][4].

II. OVERVIEW OF FUNCTIONAL MODULES
Unified Timing Signal generator module developed and tested by authors generates the
sequence of pulses with reference to external trigger signal with the feature like
programmable pulse sequence, pulse widths and inter pulse delay.

Delayed Mono Stable (DMS) Pulse Generator:
Standard design implemented as part of counter/timer [2][6] do not have delayed triggering
feature. The proposed design is unique which generates an output signal of programmable
width after programmable delay with reference to a reference signal. The design is based on
software or hardware triggered mono stable pulse generator. Reference trigger signal gives
trigger to mono stable pulse generator. Output signal is at default value ‘0’.The pulse
generation is derived using two counters corresponding to references 1. OFF Time Counts 2.
ON Time Counts. Both reference times are programmable through registers. On trigger,
both counters loaded with zero value and OFF counter starts up counting. There is a clock
input for counter operation. On maturity of OFF counter Output signal changes as per
Figure 1 Delayed Mono Stable Pulse. Next, the ON counter starts and the output holds ‘1’
value till the count matures to ON Time. At end output turns to default value ‘0’.

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Figure 1 Delayed Mono Stable Pulse
Thus the uTSG is based on a delayed mono stable architecture. The block supports four
modes to cover all types of RADAR timing control signal requirements usually
encountered. The technology symbol diagram of the design is as per Figure 2 uTSG
Interface Detail: RTL Schematic.
The Reference trigger signal is an input signal used to start / synchronize the timing
function. It is optional in case of free running signal generation. The data and control
interface allows convenient connectivity of the unit on to a local bus. time_sig_out signal is
the desired output. clk_mc is input control clock for interface and master clock of local bus.
clk_tg is timing signal clock input on which the FSM of uTSG runs. reset_n signal is
master reset on local bus to put uTSG in to reset condition. rd(Read), wr(Write) and
cs(Chip select) are control signals to interface the uTSG to a local bus. Address[4:0] bus is
to address 26 registers of the uTSG and bidirectional data bus data_mc[7:0] to configure
uTSG. There are two bytes for mode and control definition and four bytes per DMS
generation. No of register required is based on multiple windows mode 4 to cover six
window generations.

Figure 2 uTSG Interface Detail: RTL Schematic

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Operating Modes:
1. Oscillator
In this mode, pulse train for OFF period counts and ON period counts is generated. ON
TIME and OFF TIME are two programmable registers holds counts for ON/OFF period.
Generation is software controlled by enable / disable flag. It is independent of the
reference signal input. PRI reference in pulsed RADAR can be generated using this
mode. Figure 3 FSM Mode-1 describes FSM flow of state machine.

Figure 3 FSM Mode-1
FSM_M1 state is wait state or reset state waiting for software enable to occur. The
output signal is in reset condition i.e. logic level ‘0’. On setting of enable =1 bit in
configuration register, two counters, OFF counter and ON counter, are made zero and the
state of the unit changes to OFF_TIME state. In this state the OFF counter is
incremented on every state clock. It may be noted that the output remains in ‘0’ level
during this state. When OFF counter equals to OFF time the state machine advances to
the state of ON_TIME.
In ON_TIME state output level changes to ‘1’ and the ON counter increments on every
state clock. When the ON Counter equals ON Time, the output changes back to ‘0’ level
and state machine parks itself in FSM_M1 state, If enable flag = 1 then it repeats the
cycle.

2. Burst Mode

This mode generates multiple pulses of same duration for N times on every reference
trigger pulse. N is a programmable pulse-counter. The duration is defined by the sum of
OFF period counts and ON period counts. The loop of generation of the pulse is
repeated N times on every reference trigger. Basic reference signal generated by mode 1
is used for reference input. Output Transmit pulse / Receive data window can be
generated using this mode. Figure 4 FSM Mode 2 describes the flow of the state
machine in this mode.

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Figure 4 FSM Mode 2
3. Counter Mode
In this mode a counter counts input reference occurrences for N times. This N is a
programmable Pulse Count. On the first, and thereafter once every N occurrences of
reference only, one delayed mono shot pulse is generated. This kind of timing is often
required for synchronizing signals in beam-steering applications of active antennas.
Figure 5 FSM Mode 3 describes this FSM state flow.
PRF_counter is a variable that counts input trigger. First time it is initialised with value
N and so first time it completes basic loop of OFF_TIME and ON_TIME.
Second occurrence of trigger will not allow loop to execute in case of N>1.

Figure 5 FSM Mode 3
4. Multiple Windows
In this mode multiple delayed pulses of different programmable durations can be
generated with reference to input trigger pulse, as illustrated in Figure 6 FSM Mode 4.
Each pulse is referred to as one window. There are multiple ON/OFF times
corresponding to different windows. The pulse generation repeats itself for the
programmed number of windows and each time the corresponding ON/OFF times is

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compared. This mode meets requirement of a control signal, encountered in scanning
radar systems with time-sensitive data capture for received data, multiple calibration
data and auxiliary data on every scan.

Figure 6 FSM Mode 4

III. Test setup and Results
Although the basic concept of this design can be realized and tested in simulation
environment, in this exercise the soft design is developed, simulated and actually
implemented in hardware to make sure that there are no implementation related issues.
A single-board RADAR controller card developed for radar control applications is used
for testing of this implementation. The following are the details of simulation,
implementation and testing.
The RADAR controller card is based on a Xilinx FPGA xcv300-4pq240[5] and a
microcontroller 80c51F020[6]. Microcontroller is used to interface serially through
UART with external RS232 interface and internally to generate Address / Data and
control bus for interfacing with uTSG design. There are four elements in total test setup
as shown in Figure 7 Test Setup.
1. A PC running GUI based control program is used to send commands to the uTSG
running in the target single-board controller card. The utility program allows saving
and retrieval of configuration files on PC for testing purpose. Once a configuration
selected or entered, command string gets transmitted through communication port
(COM Port). This software is developed using Visual Basic 6 on MS-Windows XP
platform.
2. Multi output calibrated Programmable Power Supply from Agilent to generate +5V
DC, +3.3V DC and +2.5V DC.
3. FPGA Board.
4. Oscilloscope to measure and record the waveforms.

257


Figure 7 Test Setup
Functional testing of the Universal Timing Signal Generator module has been carried
out by creating a VHDL project with two instantiations of the uTSG module as shown in
Figure 8 Implementation Project View). Instances are named as uTSG1 and uTSG2. CD
is clock driver block and DEC is decoder to select uTSG1 and uTSG2. ISE 10.1i [7]
EDA tool is used for compilation and implementation of design.
The reference trigger input required for functional verification of the project was
generated using VHDL test bench. Stimulus was generated to run the first uTSG module
in the free running mode (Mode 1) & the second uTSG module to test rest of three
modes one by one. Register values were loaded with various count values and output
timing signal was observed in Modelsim simulator [8].

Figure 8 Implementation Project View

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Figure 9 Simulation Results, is the golden reference for the signals generated in all
operating modes. In Mode1, 10% duty cycle reference signal is generated by uTSG1 that
is serving as reference trigger signal to test other modes. uTSG2 running in different
modes 2 to 4. In mode 2 DMS, OFF time and ON time is of four counts and also repeat
pulse count is of value four. Mode 3 counter DMS simulation result indicates output
pulse generation on first and every fourth pulse of reference input signal. In mode 4
multi window output, multiple pulses of different ON time / OFF time are generated.

Figure 9 Simulation Results
Simulation is carried out in ModelSim simulator package [8]. Keeping the same
configuration data, implementation was done on FPGA of the single-board RADAR
Controller card. Figure 10 Implementation Results) is output captured on oscilloscope
for one by one mode.

Figure 10 Implementation Results

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The following basic RADAR signals, 1. Transmit Pulse (TX), 2. Tx Control Pulse that is
expanded pulse for protection switch, 3. Data Window for capturing received signal and
three switch specific control signals (Rx Sw Ctrl, STC0 and STC clock) are generated using
uTSG as per Figure 11 RADAR Control Signals.

Figure 11 RADAR Control Signals
Compressed view for multiple pulse simulation is in Figure 12 Multiple Pulses.

Figure 12 Multiple Pulses

IV. Cost Benefit Analysis
As has been described, this implementation of the uTSG is generic in nature with multiple
operating modes. Although the generic implementation has application level advantages,
there might be some penalty to pay for the advantages gained. Table 1 presents the resource
demand of the implementation for selected Xilinx device environments which have been the
mainstay implementation platforms in this study.

Table 1 Implementation Comparison
S.No. Mode of Fractional Approximate Resource utilization per
Operation Utilization Absolute instantiation of uTSG as part of a
of Resource few currently used Xilinx Devices
Resources Demand XQVR300 XQVR600 Virtex 4
(% of (Xilinx Virtex (6,144 (15,552 (152,064
uTSG Slice Level) Logical Logical Logical
Allocation) (per Cells) Cells) Cells)
Instantiation)
1 Mode 1 30 130 S/FFs
2 Mode 2 60 260 S/FFs

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3 Mode 3 80 340 S/FFs
4 Mode 4 90 390 S/FFs
5 Total 100 430 S/FFs 7% 3.5% ~ 1%
per uTSG Per uTSG Per uTSG

It can be seen that although in the lower order modes the fractional utilization of resources
allocated to the uTSG are on the lower side, the full resource demand of the uTSG
instantiation as a fraction of device resources is a small number at several to a few percent
for low density devices like the XQVR300 or 600, and falls rapidly for higher density
devices. The state of the Art is Virtex 7 device but it can be seen that beyond Virtex 4 the
resource demand is truly negligible and is unlikely to affect the gross functionality of the
rest of the logic that may be coded into the device in any of the applications.
The relative underutilization inside the allocation for uTSG is thus not a matter for concern
in most practical situations. However uTSG implementation can be trimmed and subset can
be used for application specific optimisation.

V. CONCLUSIONS
A Delayed Mono Stable pulse generator can serve as a basic element to generate multiple
delayed pulses with a common reference and serve the need of most pulsed radar timing
signal necessities.
The Unified Timing Signal Generator entity is tested for all modes and all options in
simulation and targeted results are achieved in actual implementation. One TSG unit
consumes a maximum of 7% of the resources of the low-density Xilinx device XCV300,
and the fractional resource demand rapidly falls for higher density devices and ceases to be a
concern for the state of the art devices.
Thus all critical timing signal requirements of a pulsed RADAR applications can be met
effectively with this generic uTSG approach reaping benefits of reduced extra-device
developmental resources including development cycle time.
Future work can be taken up for architecture dependent implementation and optimization for
different technology FPGA / ASIC.
VI. REFERENCES

[1] RADAR System Design Documents, Space Application Centre Ahmedabad.
[2] Mrs. Anudeepa S. Kholapure ,Dr. Arvind Agarwal, Mrs. Shikha Nema, Second
International Conference on Emerging Trends in Engineering and Technology, ICETET-
09.“Design of a Timing Signal Generator (TSG) for RADAR using FPGA”.
[3]TPU Time Processor Unit Reference Manual (Including The TPU2),Free Scale
Semiconductors, p.1.1.
[4] A VHDL Primer: Jayaram Bhasker,3rd Ed. ISBN-81-203-2366-1
[5] Xilinx® Virtex Datasheet, DS003-1 (v2.5 ) April 2, 2001
[6] Silabs Datasheet, C8051F34x, Rev. 1.0 8/06
[7] Xilinx® ISE Design Suite 10.1
[8] ModelSim XE III 6.3c Reference Documents.

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Design of a unified timing signal generator (utsg) for pulsed radar

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