Unit_5 – Sequential Circuits.pptx

Unit 5 – Sequential Circuits

Outline
› Introduction,
› Flip-Flops,
› Triggering of Flip-Flops,
› Analysis of Clocked Sequential Circuits,
› Applications of flip-flops,
› Flip-Flop Excitation Tables,
› Design Procedure,
› Design of Counters,
› Design with State Equations,
› Shift Register,
› Applications of Shift Registers

Introduction
› Basically switching circuits may be combinational or sequential
› Combinational circuits are those whose output levels at any
instant of time are dependent only on the levels present at the
inputs at that time.
› Any prior input level conditions have no effect on the present
outputs, because combinational logic circuits have no memory.
› On the other hand, sequential circuits are those whose output
levels at any instant of time are dependent not only on the levels
present at the inputs at that time, but also on the prior input level
conditions. It means, it has memory.

Contd.
› The most important memory
element is the Flip – flop (FF), which
is made up of an assembly of logic
gates.
› Each type of FF has special features
or characteristics necessary for
particular applications.
› A FF known more formally as a
bistable mutlivibrator, has two
stable states.
› It can remain in either of the states
indefinitely.

A 1 bit memory
› It has two stable states which are
known as the 1 state and the 0 state.
› It can be obtained by NAND or NOR
gates.
› It consists of two inverters G1 and G2
› The output of G1 is connected to the
input of G2 and output of G2 is
connected to the input of G1.
› Fig. shows cross coupled inverters
as a memory element…
› The outputs Q and Q’ are always
complementary.

Contd.
› The circuit has two stable states.
– Q =1  1 state (or set state)
– Q = 0  0 state (or reset state)
› If the circuit is in 1 state, it continues to remain in this state and
similarly if it is in 0 state, it continues to remain in this state.
› This property of the circuit is refereed to as memory i.e. It can
store 1 bit of digital information.
› Since this information is locked or latched in this circuit, so
circuit is also referred to as a latch.

Clocked RS Flip flop
Q S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Indeterminate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Indeterminate

Characteristics Table
› A characteristics table defines the logical properties of a flip flop by
describing its operation in tabular form.
› Q(t) refers to the present state prior to the application of a clock edge.
› Q(t+1) is the next state one clock period later.

Characteristic Equation
› The logical properties of a flip flop as described in the
characteristic table can be expressed also algebraically with a
characteristic equation.
› 𝑄 𝑡 + 1 = 𝑆 + 𝑅′
𝑄
› 𝑄 𝑡 + 1 = 𝐷
› 𝑄 𝑡 + 1 = 𝐽𝑄′
+ 𝐾′
𝑄
› 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄 = 𝑇𝑄′
+ 𝑇′
𝑄

Triggering of Flip flop
› The state of a flip flop is switched by a momentary change in the input signal.
› This momentary change is called a trigger and the transition it causes is said
to trigger the flip flop.
› Flip flop is more sensitive to the pulse transition rather than the pulse
duration.
› The pulse goes from 0 to 1  positive edge Or rising edge
from 1 to 0  negative edge Or falling edge

Contd.
› The clocked flip flops are triggered during the positive edge of the
pulse, and the state transition starts as soon as the pulse reaches the
logic 1 level.
› The new state of the flip flop may appear at the output terminals while
the input pulse is still 1.
› If the other inputs of the flip flop change while the clock is still 1, the flip
flop will start responding to these new values and a new output state
may occur.
› When this happens, the output of one flip flop cannot be applied to the
inputs of another flip flop when both are triggered by the same clock
pulse.
› However, if we can make the flip flop respond to the positive (or
negative) edge transition only, instead of the entire pulse duration,
then the multiple transition problem can be eliminated.

FF Excitation tables
› The characteristic table is useful for analysis and for defining the
operation of the flip flop.
› It specifies the next state when the input and present state are
known.
› During the design process we usually know the transition from
present state to next state and wish to find the flip flop input
conditions that will cause the required transition.
› For this reason, we need a table that lists the required inputs for
a given change of state, such a list is called an excitation table.

Unit_5 – Sequential Circuits.pptx

Design of Counters
› A sequential circuit that goes through a prescribed sequence of
states upon the application of input pulses is called a counter.
› A counter that follows the binary sequence is called a binary
counter.
› An n-bit binary counter consists of n flip flops and can count in
binary from 0 to 2n -1

Counter with Non binary sequence
› A counter with n flip-flops may have a binary sequence of less
than 2n states.
› A BCD counter counts the binary states from 0000 to 1001 and
returns to 0000 to repeat the sequence.
› Other counters may follow an arbitrary sequence that may not be
the straight binary sequence.
› In any case, the design procedure is the same.

Design a counter that has a repeated sequence of
six states as listed in Table

MSI Counters
› Two categories:
– Ripple counters
– Synchronous counters
› In a ripple counter, the FF output transition serves as a source
for triggering other FFs.
– In other words, the CP inputs of all FFs (except the first) are
triggered not by the incoming pulses but rather by the transition
that occurs in the other FFs.
› In a synchronous counter, the input pulses are applied to all CP
inputs of all FFs.
– The change of state of a particular FF is dependent on the present
state of other FFs.

Binary Ripple Counters
› A binary ripple counter consists of a series connection of
complementing flip-flops (T or JK type), with the output of each of
FF connected to the CP input of the next higher order FF.
› The FF holding the least significant bit receives the incoming
count pulses.
› The diagram of a 4-bit binary ripple counter is shown in figure 7-
12.

BCD Ripple Counter
› A decimal counter follows a sequence of ten states and returns
to 0 after the count of 9.
› Such a counter must have at least 4 FFs to represent each
decimal digit.

Synchronous Up/Down 3 – bit Counter

Shift Registers
› A register capable of shifting its binary information either to the
right or to the left is called a shift register.
› The logical configuration of a shift register consists of a chain of
FFs connected in cascade, with the output of one FF connected to
the input of the next FF.
› All FFs receive a common clock pulse that causes the shift from
one stage to the next.
› Data may be available in parallel form or in serial form.

Contd.
› The Q output of a given FF is connected to the D input of the FF at its right.
› Each clock pulse shifts the contents of the register one bit position to the right.
› The serial input determines what goes into the leftmost FF during the shift.
› The serial output is taken from the output of the rightmost FF prior to the application of a pulse.
› Thus, a unidirectional shift register can function either as a Shift-right or as a Shift-left register.

Types of shift register
1. Serial in – Serial out (SISO)
2. Serial in – Parallel out (SIPO)
3. Parallel in – serial out (PISO)
4. Parallel in – Parallel Out (PIPO)

PISO
› The signal shift/load’ allows
1. The data to be entered in parallel form into the register
2. The data to be shifted out serially from terminal Q4.

Contd.
› When shift/load’ line is HIGH, gates G1, G2 and G3 are disabled but
gates G4, G5 and G6 are enabled allowing the data bits to shift right
from one stage to the next.
› When shift/load’ line is LOW, gates G4, G5 and G6 are disabled,
whereas gates G1, G2 and G3 are enabled allowing the data input to
appear at the D inputs of the respective FFs.
› When a clock pulse is applied, these data bits are shifted to the Q
output terminals of the FFs and therefore, data is inputted in one step.
› The OR gate allows either the normal shifting operation or the
parallel data entry depending on which AND gates are enabled by the
level on the Shift/Load’ input.

Applications of Shift Registers
1. Time Delays
2. Serial / Parallel Data Conversion
3. Ring Counters

1. Time Delays
› It can be used to delay the arrival of serial data by a specific number of
clock pulses.
› The total time delay can be controlled by adjusting the clock frequency
and by prescribing the number of stages in the register.
› In practice, the clock frequency is fixed and the total delay can be
adjusted only by controlling the number of stages through which the
data is passed.
› By using a SIPO register and by taking the serial output at any one of
the intermediate stages, we have the flexibility to delay the output by
any number of clock pulses equal to or less than the number of stages
in the register. (as shown in fig. 9.12 – can be used to delay the data by 4
clock pulses)

2. Serial / Parallel Data Conversion
› Data can be available either in serial or in parallel form.
› Transfer of data in parallel form is much faster than that in serial
form.
› But when large data is to be transmitted over long distances,
transmitting data on parallel lines is costly and impracticable.
› It is convenient and economical to transmit data in serial form,
since serial data transmission requires only one line.
› Shift registers are used for converting serial data to parallel
form, so that a serial input can be processed by a parallel system
and for converting parallel data to serial form, so that parallel
data can be transmitted serially.

3. Ring Counters
› It can be constructed by modifying the SISO registers.
› There are two types of ring counters.
1. Basic ring counter
• It can be obtained from SISO register by connecting the Q output of the
last FF to the D input of the first FF.
• Ring counter outputs can be used as a sequence of synchronizing
pulses.
• The ring counter is a decimal counter.
• It is a divide by N counter, where N is the number of stages.
2. Johnson counter
• It can be obtained from a SISO register by connecting the Q’ output of
the last FF to the D input of the first FF.

Ring Counter
› Circular shift register, with only
one FF being set at any particular
time, all others are cleared.
› Initial value, 1000

Contd.
› The single bit is shifted from one FF to the other to produce the
sequence of timing signals.
› Each FF is in the 1 state once every four clock pulses and
produces one of the four timing signals.
› Each output becomes a 1 after the negative-edge transition of a
clock pulse and remains 1 during the next clock pulse.

Johnson Counter
› K-bit ring counter circulates a single bit among the FFs to provide K
distinguishable states.
› The no. of states can be doubled if the SR is connected as a switch-tail ring
counter.
› Circular shift register with the complement output of the last FF connected to
the input of first FF.

Unit_5 – Sequential Circuits.pptx

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