A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
DOI :10.5121/vlsic.2010.1301 1
A High-Swing OTA with wide Linearity for design
of self-tunable linear resistor
Nikhil Raj, R.K.Sharma
Department of Electronics and Communication Engineering
National Institute of Technology, Kurukshetra
Haryana, 136119, India
nikhilquick@gmail.com, mail2drrks@gmail.com
ABSTRACT
Low power consumption, long battery life and portability are essential requirements of modern health
monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is
an basic building block for low power health monitoring products design. An modified design of OTA
which incorporates better linearity and increased output impedance has been discussed in this paper. The
proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency
applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at
power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low
voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The
circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM
3v3 level-53 model parameter and verified results through use of ELDO Simulator.
KEYWORDS
Bulk-input, Wilson mirror, Linear range, MOS resistor
1. Introduction
Device sizing is the latest trend in VLSI. Scaling down the channel length in CMOS technology
facilitates the submicrometer devices on single IC. Battery operated devices in medical electronics
like Ambulatory Brain Computer Interface (ABCI) systems, insulin pumps, hearing aids
essentially require low power designs using submicron devices.
Such rapid increase use of battery-operated portable equipment is realized with VLSI (very
large scale integrated) technologies. As the technology of biomedical instrumentation amplifier is
moving towards portability, lower power consumption is highly desirable for devices which
monitors patient whole day.
Small amplitude and low frequency range are special features of biological signals like ECG. In
order to process these signals low pass filters are used with sufficient large time constant, typically
for a capacitor value of less than 5pF which in turn require very high resistance. For example, in
ECG signal detection, low-pass filter required must have cut-off frequency less than 300 Hz for
which use of low-power continuous-time OTA-based filters are preferred [1]. However, major
limitation of conventional OTAs is its limited linear range. As device sizes are scaling down,
traditional saturation-based OTAs are facing design challenges to overcome poor linearity and
limited output impedance. Various techniques for extending linear range have been proposed

2
among which one is based on source-degeneration and multitanh principle [2]. An alternative
method forces to employ diodes as source degeneration elements to extend the linear range [3], but
using stacked diodes in series as degeneration elements increases the need of supply voltage. In
[4], the OTA uses 21-transistor operating in subthreshold mode gives a linear range of about 700
mV. Since the OTA is a current source device, the output impedance of the device must be high.
This work uses the OTA circuit proposed in [5] as reference. The current mirror part of this OTA
has been replaced with High-swing improved-Wilson current mirror circuit. The simulation of
modified OTA proved considerable improvements in linearity (upto 1.9 volt) as well as sufficient
increase in output impedance.
The proposed work has been organized into four sections. Section 2 covers detailed description
on working of proposed OTA; based on principle of bulk-driven MOS transistors. Section 3 is
detailed on implementation of modified OTA in design electronically tunable linear resistor using
MOS. The simulation results and conclusion has been discussed in section 4 and 5 respectively.
2. Proposed OTA
2.1 The referred OTA
The OTA is a transconductance type device, which means that the input voltage controls an
output current by means of the device transconductance, labeled m
g . This makes the OTA a
voltage controlled current source (VCCS). In the past few years, engineers have improved the
linearity of MOS transconductor circuits. Such improvement has been primarily in the area of
above-threshold, high-power, high-frequency, continuous time filters. The architecture of OTA is
shown in Fig. 1 which provides a linearity of 1.7 volt by combination of four techniques. Firstly,
the well terminals of the differential-pair transistors 1
W and 2
W is used as amplifier inputs.
Secondly, feedback techniques like source degeneration via 1
S and 2
S transistors whereas gate
degeneration via 1
GM and 2
GM provide further improvement. Finally, 1
B and 2
B used as bump
transistors. The bump-linearization technique is used to overcome parasitic effects which occur at
low input voltage, generally less than 1 volt.
Figure1. Basic OTA [5]

3
The P transistor act as bias current source and the remaining transistor 1
p
M , 2
p
M , 3
n
M and 4
n
M are
configured as simple current mirrors. Besides, there is an offset voltage adjustment which sets
OS
V around 5 mV less than DD
V . To improve OTA performance, simple current mirror used is
replaced by complex mirroring, that is, High-swing improved-Wilson current mirror. This
technique not only removes the offset voltage adjustment but increases output resistance compared
to case of simple current mirror.
The current equation for subthreshold MOS is given as
( )
1
0
gs T ws T
kV V k V V
I I e e
− − −
= (1)
for well-input MOS
( )
V g V
s w
T
V
I e
α
− −
(2)
( ) ( )
( ) ( )
2 2 1 1
2 2 1 1
V gV V gV
s w s w
T T
V gV V gV
s w s w
T T
V V
OUT d
V V
B T
I I I I e e
I I I I e e
− − − −
− − − −
+ −
+ −
− −
= = =
+ +
(3)
Solving
1
tanh
2
1
d T
d T
gV V
OUT d
gV V
B T
I gV
e
I V
e
 
−
= =  
+  
 (4)
where 2 1
d w w
V V V V V
+ −
= − = −
i.e. tanh
OUT
d
B
L
V
I I
V
 
 
 
= (5)
where out
I is the output current, B
I is the bias current of P transistor , L
V is the linear range of OTA
expressed as 2
L T
V V g
=  , where g is the overall reduced transconductance of OTA.
Analyzing the left half-circuit of Fig. 1, the overall transconductance g is reduced by a feedback
factor( )
1 1 1
p n
k k
+ + ,
i.e.
1
1 1 1
p n
k
g
k k
−
=
+ +
 (6)
where 1 p
k and 1 n
k are the loop gain of source degeneration and gate degeneration transistor
respectively. From tanh series expansion
3
tanh
2 2 24
x x x
= − + − − − ; it can be observed that if L
V
is made sufficiently high then cubic order term in the tanh series expansion can be easily neglected
thereby reducing distortions of non-linearity.
2.2 High-swing improved-Wilson current Mirror
A current mirror is characterized by the current level it produces, the small-signal ac output
resistance and voltage drop across it. The simple current mirror uses the principle that if gate-to-
source potentials of two identical MOS transistors are equal then their channel currents are equal.

4
In late 1967, George Wilson proposed a modified current mirror just by adding one extra transistor
which increases output impedance to appreciable amount and named the circuit as Wilson current
mirror. The Wilson current mirror implemented using three nMOS transistors is shown in Fig. 2
(a). The architecture consists of simple current mirror and a current to voltage converter connected
in the feedback loop. If there is any increase in output current due to output voltage variation, the
simple current mirror transistors senses this variation and feed back the current to input node
thereby reducing gate voltage of output transistor followed by reduction in original current
increase. But these current mirror suffered systematic gain error along with unequal voltages
across input and output transistors. To compensate systematic gain error, Barrie Gilbert; added a
fourth transistor in diode connected form in the input branch and later this circuit became famous
by name improved Wilson current mirror [6] as shown in Fig. 2 (b).
Figure2. (a) Wilson current mirror, (b) Modified Wilson current mirror
These circuits require an input voltage of two diode drops and output compliance voltage
incorporates a diode drop plus saturation voltage. Such diode drop made Wilson mirror
unattractive for low-power design units. To overcome this, a new Wilson topology was introduced
[7], which sense the output current at low input voltage of a diode drop plus a saturation voltage
whereas output senses only two saturation voltage. As seen from architecture, the diode connected
transistor on input side biased by current source b
I , causes the input voltage to decrease much
lower than gate voltage needed as in case of simple mirrors to sink input current. This makes it a
low voltage high-swing improved-Wilson current mirror as shown in Fig. 3. The mirror achieves
high output resistance by using negative feedback and is directly proportional to the magnitude of
the loop-gain of the feedback action from the output current to the gate of output transistor 3
n
M .
The transistor 1
n
M and 2
n
M samples the OUT
I and compares it with in
I . In combination with
current source load in
I , transistor 1
n
M act as a common source amplifier used to maintain gate
voltage of 3
n
M to avoid mismatching of OUT
I to in
I . Neglecting 2nd
order effects, the output
resistance out
r is approximated as
1 1 3
out m o o
r g r r
≈  (7)
where, 1
m
g and 1
o
r are transconductance and output resistance of 1
n
M whereas 3
o
r is output
resistance of 3
n
M .

5
Figure 3. High-swing improved Wilson current mirror
2.3 Modified OTA
The proposed architecture of OTA using high-swing improved-Wilson current mirror is shown
in Fig. 4. The architecture works on low supply thereby introducing appreciable reduction in
power consumption. A bias current generator circuit is attached to OTA which generates current in
the range of nanoamperes.
Figure 4. Proposed OTA using High-swing improved Wilson current mirror
Transistors 13 16
n n
M M
− and 11 12
p p
M M
− along with s
R comprises current generator circuit. As the
source-to-gate voltage of 11
P
M and 12
P
M are equal their corresponding currents are equal, i.e.

6
11 12
D D
I I
= (neglecting channel length modulation). Furthermore, it can be noted
that 13 11
D D
I I
= and 14 13
D D
I I
= .
The equation for drain current of MOS transistor is given by
( )2
1
2
D n ox GS Tn
W
I C V V
L
µ
= −  (8)
Solving for GS
V
( )
2 D
GS Tn
n ox
I
V V
C W L
µ
= + (9)
In Fig. 3
 , 13 , 14 , 14
GS n GS n D n S
V V I R
= + (10)
From (10)
( ) ( )
, 13 , 14
, 14
13 14
2 2
D n D n
D n S
n ox n ox
Mn Mn
I I
I R
C W L C W L
µ µ
= + (11)
Rearranging above expression and solving for , 12
D p
I by equating equivalent currents, the , 12
D p
I
is given as
( )
( )
( )
2
13
, 12 2
13 14
2 1
1 Mn
D p
n ox S
Mn Mn
W L
I
C W L W L
R
µ
 
 
= −
 
 
(12)
The output current bias
I , that is, , 13
D p
I is now the function of , 12
D p
I . By adjusting the aspect ratio
of 13
p
M relative to 12
p
M , desired bias
I can be obtained. The W L ratio of 13
p
M is kept four times
lower than 12
p
M , which results in output current , 13 , 12 4
D p bias D p
I I I
= = .
3. Self-tunable linear resistor using MOS
Electronically tunable linear resistors are highly versatile circuit elements. MOS transistors are
generally used for resistor modeling as when it is operated under triode mode behaves as a resistor
controlled by its gate terminal voltage. MOS being a four terminal device offers two control
parameters that is gate and bulk terminal to control resistor value. Through electronic tuning of
gate terminal voltage of MOS transistor, correspondingly electronic control on resistance can be
achieved. In the past, MOS resistors with approximately linear I-V characteristics were obtained
by operating the transistor in the ohmic (triode) region of strong inversion to exploit the resistive
nature of the channel. Generally, these approaches were limited by the small ohmic region and its
intrinsic non-linearities. Various techniques have been proposed to minimize nonlinear effects
associated with operating the MOS transistor in the ohmic strong inversion regime with good
results [8]-[9]. In regard to this, a MOS resistor is used that does not require triode operation [10].

7
MOS transistor R
M shown in Fig. 5, act as a self-tunable resistor when get tuned by capacitance
C connected at its gate terminal.
Figure 5. Electronically self-tuned linear resistor using MOS
To maintain resistor characteristics, a feedback network is configured at its gate terminal. The
two OTAs, OTA1 and OTA2 have same inputs X
V and Y
V connected to their input terminals in
alternative fashion and are biased by the same current source GM
I . The potential difference
X Y
V V
− across the MOS device R
M is sensed and converted into a current ,
OUT GM
I using a wide
linear range low power OTA for which the output current equation is of the form
( )
,
OUT GM M X Y
I G V V
= − (13)
Where, ( )
M GM L
G I V
= is the transconductance of OTA while GM
I and L
V are the biasing current
and linear range of the OTA respectively. These OTAs are configured in conjunction with diode
connected transistors M1 and M3 to produce two half-wave rectified currents that are proportional
to XY
V , voltage across the source-drain terminals of R
M . The rectified output currents are

8
mirrored via M2 and M4 to create a full wave rectified current. The saturation currents Xsat
I and
Ysat
I of R
M are proportionally replicated by sensing G
V , W
V , X
V and Y
V on the gate, well, source
and drain terminals of R
M buffered via source followers and applying potentials GX
V and GY
V
across the gate-source terminals of transistors X
M and Y
M . Transistors M7-M13 serve to compute
Xsat Ysat
I I
− or Ysat Xsat
I I
− and transistors M14-M17 compare Xsat Ysat
I I
− with a mirrored version of
output current using M6. Any difference between these two currents causes the capacitor C to
charge or discharge tuning the gate bias voltage G
V which equilibrates at a point where the two are
nearly equal via negative feedback action.
To overcome loading effect on terminals of MOS transistor R
M , source follower is employed
shown within dotted lines marked as SF in Fig. 5. The source follower has the capability to source
and sink large output currents. Its primary use is to buffer signals and provide low output
impedance to drive resistive loads while, at the same time handle large output voltage swing and
obtain low harmonic distortion. Traditional source have load drive capability limited to the
quiescent current in the buffer. In addition traditional source followers require too much power for
many applications. To reduce power dissipation (and area) required to reach a given output
resistance, composite source follower is used. The composite source follower comprises a current
source, PMOS (Msf3) configured to provide a (relatively) constant current to the rest of the circuit,
a source follower NMOS (Msf0, Msf2) configured to receive an input signal, a folded cascade
device PMOS (Msf4) connected to sense the drain current of the source follower, and a current
mirror device NMOS (Msf1) connected to multiply the sensed drain current for application to an
output load connected at the source follower output. It provides a four-fold increase in
transconductance which offer perfect tracking of input by output having no level shift problem as
compared to common voltage buffers. Being less complex circuitry, it is most effetely used in field
of low power architectures.
4. Simulation Results
The simulations were performed under normal condition (room temperature) on TSMC 0.18
micron technology using ELDO Spice Simulator. The bias current generator circuit generates
bias
I of 65nA at 10
S
R K
= Ω . The supply voltage is kept at 0.9 volt. Fig. 6 shows the transfer
characteristics of proposed OTA with enhance linearity to about ± 1.9 volt with no offset voltage
adjustment. Fig. 7 shows the ac response of OTA under no load condition. The achieved phase
margin is 55.332 degree and UGB of 342.30 KHz. Its low UGB supports it for use in biomedical
applications.

9
Figure 6. Transfer characteristic of proposed OTA
Figure 7. AC response of proposed OTA
When configured as follower integrator using 1 pf of load shown in Fig. 8, it tracks the input
perfectly with slight variation at low input voltage, that is, below 0.4 volt. The transfer
characteristic of MOS acting as linear resistor is shown in Fig. 9. The value of resistor is varied in
accordance to tuning the OTA bias current gm
I of OTA used in design.

10
Figure 8. Follower integrator DC characteristics at 1pF load
Figure 9. Transfer characteristic of self-tunable linear resistor using MOS
5. Conclusion
This paper explored the approach of low-voltage OTA design using the bulk-driven technique
and enhancement of output impedance using high-swing improved-Wilson current mirror. The
design of such low voltage, high performance OTA circuit on TSMC 0.18 micron technology
satisfies the required parameters for its implementation not only in power-saving devices but also
in biomedical portable devices. Further its application in design of tunable MOS resistor find
application in variable gain amplifiers, oscillators, balanced resistive bridges and analog filters.

11
Acknowledgment
The author would like to thank K.H.Wee and R. Sarpeshkar for the measurement assistance and
meaningful discussions on OTA and MOS resistor. The author also extend their thanks to B. A.
Minch for the measurement assistance of different CM circuits.
References
[1]S. Solis-Bustos, J. Silva-Martínez, F. Maloberti, and E. Sánchez-Sinencio, “A 60 db dynamic-range CMOS sixth-
order 2.4 Hz lowpass filter for medical applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
Conf., vol. 47, pp. 1391-1398, Dec. 2000.
[2]P. M. Furth and A. G. Andreou, “Linearised differential transconductor in subthreshold CMOS,” Electron. Lett., vol.
31, no. 7, pp. 547-554, 1995.
[3]L. Watts, D. A. Kerns, R. F. Lyon, and C. A. Mead, “Improved implementation of the silicon cochlea,” IEEE J.
Solid-State Circuits, vol. 27, no. 5, pp. 692–700, 1992.
[4] I. E. Opris and G. T. A. Kovacs, “Large-signal subthreshold CMOS transconductance amplifier,” Electronics
Letters, vol. 31, no. 9, pp. 718-720, April, 1995.
[5]R. Sarpeshkar, R. F. Lyon, and C. A. Mead, A low-power wide linear-range transconductance amplifier, Analog
Integrated Circuits Signal Processing, vol. 13, pp. 123–151, 1997.
[6]B. L. Hart and R. W. J. Barker, “D. C. Matching Errors in the Wilson Current Source,” Electronics Letters, vol. 12,
no. 15, pp. 389–390, 1976.
[7]B. Minch, “Low-Voltage Wilson Current Mirrors in CMOS,” in IEEE ISCAS, New Orleans, LA, USA, 2007, pp.
2220–2223.
[8]J. Ramirez-Angulo, M.S. Sawant, R.G. Carvajal and A. Lopez-Martin “Linearisation of MOS resistors using
capacitive gate voltage averaging,” Elec. Letters, vol. 41, no. 9, pp. 511-512, Apr. 2005.
[9]C. Popa, “Linearized CMOS active resistor independent on the bulk effect,” Proc. 17th Great Lakes Symposium on
VLSI, 2007.
[10]K. H.Wee and R. Sarpeshkar, “An electronically tunable linear or nonlinear MOS resistor,” IEEE Trans. Circuits
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Authors
Nikhil Raj received his M.Tech degree in Electronics and Communication Engineering with
specialization in VLSI Design from National Institute of Technology Kurukshetra, Haryana, India in 2009.
Currently, he is a lecturer with the Department of Electronics and Communication Engineering, NIT Kurukshetra,
India. After doing many research works in VLSI area, he is currently doing research in low power analog circuits.
R.K.Sharma received his M.Tech in Electronics and Communication engineering and
PhD degree in VLSI Design from National Institute of Technology Kurukshetra, India in 1993 and 2007,
respectively. Currently he is Associate Professor with the Department of Electronics and Communication
Engineering, NIT Kurukshetra, India. His main research interests are in the field of low power VLSI design,
electronic measurements, microprocessor and FPGA based measurement systems.

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