A Redundant Adder Architecture in Ternary Quantum-Dot Cellular Automata

A Redundant Adder Architecture
in Ternary Quantum-Dot Cellular
Automata
Bandan Kumar Bhoi, Neeraj Kumar Misra, Ipsita Dash and Ankita Patra
Abstract Now researchers are moving toward emerging technologies to replace the
conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of
them for high-performance computing circuits. Ternary QCA is one of the finest
research areas in this domain for replacement of binary logic. In this paper, we
proposed a new redundant adder architecture using Ternary QCA technology. Our
proposed architecture has 233 numbers of cells with an area of 0.35 µm2
. All the
proposed ternary logic layouts are implemented in TQCA designer tool.
Keywords Nanometer-scale · Full adder · Quantum-dot cellular automata ·
Complexity · Majority gate
1 Introduction
Quantum-dot Cellular Automata (QCA) are a technique which can overcome the lim-
itationsofcurrentCMOStechnologybyreplacingCMOSdeviceswith‘Quantum-dot
cells’ in which the idea is that ‘data are transferred from one cell to another by prop-
agating a polarization state rather than transferring current’ [1, 2]. Binary values,
i.e., 0 and 1 are only used in QCA technology. But in real world, logic values exist
in more than binary values, which are known as multivalue logic. The advantages of
these circuits are decrease in the input/output and low-cost faster arithmetic opera-
tions [3]. Among the multivalue logic circuits, ternary logic is most practical. This
ternary logic has three values, i.e., −1, 0, and 1. These −1, 0, and 1 are also known as
false, unknown, and true, respectively. Recently researchers have proposed different
models for ternary logic gates. In the model [4], majority logic gate is designed using
B. K. Bhoi (B) · I. Dash · A. Patra
Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology,
Burla 768018, India
e-mail: bkbhoi_etc@vssut.ac.in
N. K. Misra
Bharat Institute of Engineering and Technology, Hyderabad, India
e-mail: neeraj.mishra3@gmail.com
© Springer Nature Singapore Pte Ltd. 2020
S. C. Satapathy et al. (eds.), Smart Intelligent Computing and Applications,
Smart Innovation, Systems and Technologies 159,
https://doi.org/10.1007/978-981-13-9282-5_35
375

376 B. K. Bhoi et al.
ternary logic. Further, this gate is extended to AND and OR gate in ternary logic.
In the model [5], the pipelining technique is used to design majority gates, inverter,
corner wire, and fan out, which successfully solved the issues of elementary Ternary
QCAs.
Here, we are proposing a technique ‘The redundant binary adder by using ternary
QCA’ whose objective is to both increase in speed and minimize in power consump-
tion. A redundant binary representation allows addition without using a typical carry
so that the arithmetic operations are faster. The ternary logic is recently being con-
sidered to be an efficient technique due to its competitive advantages over binary
logic [6–10]. This adder can be used in the complicated digital circuits which will
be beneficial for the VLSI industry.
The remaining part of this paper is arranged in the following manner. Section 2
describes the basic idea and operating principle of Ternary QCA. Section 3 shows
the ternary implementation and simulation result of the proposed full-adder circuit.
Finally, the paper is concluded in Sect. 4.
2 Background of Ternary QCA
A balanced ternary logic is a type of multivalued logic system in which there are
three values, i.e., true, false, unknown (+1, 0, −1). Ternary logic has more advantages
over binary logic which uses only two values, i.e., true, and false. In Ternary QCA,
there are eight quantum-dots are present in each cell, and two mobile electrons
are tunneled between the quantum-dots. QCA do not operate by the transport of
electrons like the transistors but it operates by adjusting the electrons in a small area
of only a few square nanometers. There are four types of polarization possible in the
quantum-dot cells, i.e., −45° (−1), +45 (+1), 0° (0), 90° (0).The four different types
of polarizations have shown in Fig. 1.
Ternary gates are the basic elements used to implement the various digital circuits
based on Ternary QCA. Here, ternary wires and different types of ternary inverters
are explained [11].
A ternary wire can be created by a number of quantum-dot cells placing in a row.
When +1(+45◦
) or −1(−45◦
) is given to the input of the wire, the output value will
be the input value and the value of every cell will be identical to the input value. When
0(0◦
or 90◦
) is given to the input, the output value will be the input value but the
Fig. 1 Polarization in Ternary QCA cells

A Redundant Adder Architecture in Ternary Quantum-Dot … 377
value of every consecutive cell will change from 0◦
to 90◦
and 90◦
to 0◦
. Three types
of ternary inverters are proposed here, i.e., standard ternary inverter (STI), positive
ternary inverter (PTI), and negative ternary inverter (NTI). Positive ternary inverter
(PTI) is a type of ternary inverter in which when the input is given as +1, output will
be inverted to −1 and when the input is given as −1, output will be inverted to +1
and when the input is 0, output will be +1. Negative ternary inverter (NTI) is a type
of ternary inverter in which when the input is given as +1, it will be inverted to −1
and when the input is given as −1, it will be inverted to +1 and when the input is 0,
the output will be −1. Standard ternary inverter (STI) is a type of inverter in which
when the input is given as +1, the output will be −1 and when input is given as −1,
output will be +1 and when input is 0, output will be 0.
The figures and truth tables for the three types of inverter are shown in Fig. 2. In
all type of inverters, when input will be +1, output will be −1 and when input will
be −1, output will be +1. The only difference between these three ternary inverters
is that when the input has the value ‘0,’ the output of STI has the value ‘0’ and the
output of PTI has the value ‘+1’ and the output of NTI has the value ‘−1.’
Min gate is a majority gate in which one of the three inputs is fixed as −1. Output
of the min gate will be depending upon the majority inputs. Max gate is a majority
gate in which one of the three inputs is fixed as +1. Output of the max gate will be
depending upon the majority inputs. Ternary min/max gate is a type of majority gate.
As a majority gate has three inputs, the min/max gate has also three inputs. But
one of the three inputs of a min gate has a fixed value of ‘−1’ whereas the max gate
has a fixed value of ‘+1.’ So, output will depend upon majority of its inputs. The
truth tables and layout diagrams for min & max gates are given in Fig. 3. If one of
its inputs of a min gate is ‘0’ then it is called as clamp-down gate. Similarly, if one
of its inputs of a max gate is ‘0’ then it is called as clamp-up gate. When output of a
min gate is given to the input of a standard inverter, ‘antimin’ gate is formed whereas
when output of a max gate is given to the input of a standard inverter, ‘antimax’ gate
is formed [10, 11].
Fig. 2 Inverters a STI b PTI c NTI

Fig. 3 a Min gate b Max gate
A ternary decoder has a single input and multiple outputs. It is used to design
various complicated circuits like adders. A ternary decoder can be created by using
three different types of inverters and a min gate. Truth table and Ternary QCA layout
of a 1 input and 3 output decoder are detailed in Fig. 4. A ternary increment and
decrement gate can be implemented by using a decoder, two clamps-down gates,
and two antimax gates. Right shifting occurs in ternary increment gate whereas left
shift occurs in decrement gate. The truth table and layout diagrams for the increment
and decrement gate are given in Fig. 5 [11].
Fig. 4 Ternary decoder layout and truth table

Fig. 5 Ternary increment and decrement layout and truth Table
3 Proposed Redundant Adder
Redundant binary adders (RBA) are faster than traditional binary adders because
here, carry is not propagated to next stages. In addition, RBA takes a constant time
because each digit of the result can be calculated independently of one another.
It means each digit of the result can be calculated in parallel. The truth table of
redundant adder is shown in Table 1.
The below figure indicates how carry can be eliminated by adding two numbers
A and B. A and B have length of n digits and represented by (An−1 An−2,…,A1 A0)
and (Bn−1 Bn−2,…,B1 B0). Here, Sn−2 and Cn−2 are sum and carry result after adding
An−2 and Bn−2. Similarly, other sum and carry terms are shown in Fig. 6a. Here, X
is the final result after adding sum and carry in redundant number system.
Let assume, A = 101̄1 and B = 11̄10. The below figure explains the addition
operation. Here, after adding 101̄1 (decimal = 7) and 11̄10 (decimal = 6), the final
result is 101̄01 (decimal = 13) as shown in Fig. 6b. In redundant adder, sum and carry
functions are added in order to get carry-free addition. So, sum and carry function
will be calculated by using a ternary half adder. Then, the sum and carry function of
Table 1 Truth table of redundant adder
A B Sum Carry
−1 −1 0 −1
−1 0 −1 0
−1 +1 0 0
0 −1 −1 0
0 0 0 0
0 +1 +1 0
+1 −1 0 0
+1 0 +1 0
+1 +1 0 +1

Fig. 6 Redundant number
system a n-bit b 4-bit
example
the half adder will be given to the inputs of another half adder. Output of the second
half adder will be the sum function of redundant binary adder.
A ternary half adder comprises a sum and a carry. Sum output can be found
by using a decoder, an increment, a decrement, three min, and two max gates. All
these components can be implemented by using the ternary gates. The gate level
implementation of the sum output is given Fig. 7. A decoder can be implemented
by using a min gate and three different types of inverters, i.e., standard ternary
inverter (STI), positive ternary inverter (PTI), and negative ternary inverter (NTI).
An increment and decrement can be implemented by using a decoder, two clamps-
down gates (clamp-down gate is a min gate where one input is ‘0’), and two antimax
gates (antimax gate is a max gate where output is given to a standard inverter).
One of the two inputs of the half adder (A) is given to a decoder which has three
outputs. Another input (B) is given to the increment and decrement blocks. The three
outputs of the decoder are given to the one of the inputs of each min gate. Output of
the decrement is given to the input of first min gate. B is given to another input of
second min gate and output of the increment is given to another input of third min
gate. Then, outputs of the three min gate are given to a max gate. Output of the max
gate will be the sum output. The block diagram for the ternary half adder which has
been implemented by using ternary gates is shown below. The decoder consists of
one PTI, one STI, and one NTI along with a STI and a min gate. One of the inputs of
half adder (A1) is given to PTI then output of the PTI (P1) is given to a STI. Output
of the STI (K1) is one of the outputs of decoder. A1 is given to NTI whose output
(Q1) which is another output of decoder and is inverted by a STI which output is R1.
Then, P1 and R1 are given as the inputs of a min gate whose output (J1) is another
output of the decoder. So, three outputs of the first decoder are given as J1, K1 and
Q1.
The increment and decrement consist of a PTI, a STI, and a NTI along with a STI,
a min gate, two clamps-down gates and two antimax gates (max gate with inverter).
The second input of half adder (B1) is given to PTI which output (M1) is given to a
STI. Output of this STI is V1. B is given as the input of NTI and its output (N1) is
inverted by a STI. This inverted output (O1) and output of the PTI (M1) are given as
the inputs of min gate whose output is U1. V1 is given to a clamp-down gate whose
output is F1. Then, F1 and U1 are given to an antimax gate (max gate with a STI)
whose output will be G1. B1 is given to a NTI whose output is given to a clamp-down
gate. Output of the clamp-down gate is given to an antimax gate whose output is H1.
Then, one of the three outputs of the decoder (J1) and input B1 is given to a min gate

NT1
PT1 MIN
ST1 ST1
1
A
1
A 1
Q
1
P
1
R
1
J
1
K
NT1
PT1 MIN
ST1 ST1 Clamp Down
Clamp Down
Max
Max
ST1
ST1
1
U
1
V
1
F
1
E
1
G
1
H
1
B
1
M
1
B 1
N 1
O
1
U
1
V
Min
Min
Max
Min
Max
1
B
1
J
1
G
1
Q
1
H
1
K
1
X
1
Y 1
W
1
Z
1
S
NT1
NT1
Clamp Down
Clamp Down
Min
Max
Max
1
A
1
B
1
A
1
B
3
M
3
N
3
Q
3
R
3
P
1
T
1
C
PT1
NT1 ST1
Min
ST1
2
J
2
K
1
S
1
S
2
P
2
Q 2
R
NT1
PT1 MIN
ST1 ST1 Clamp Down
Clamp Down
Max
Max
ST1
ST1
1
M
1
N
2
G
2
H
2
U
2
V
2
F
2
E
2
U
1
C
1
C
2
O
2
V
Min
Min
Min
Max
Max
1
C
2
J
2
G
2
Q
2
H
2
K
2
X
2
Y
2
W
2
Z
2
S
Fig. 7 Block diagram of redundant full adder

whose output will be X1. Q1 and G1 are given to a min gate whose output will be
Y1. K1 and H1 will be given to a min gate whose output will be Z1. X1 and Y1 are
given to a max gate whose output will be W1. W1 and Z1 are given to another max
gate whose output will be the sum function S1.
The carry function comprises two NTI gates, two clamps down, one min gate,
and two max gates. The input A1 is given to a NTI whose output M2 is given to a
clamp-down gate. Output of the clamp-down gate is P3. Another input of the half
adder B2 is given to a NTI whose output N2 is given to a clamp-down gate. Output
of the clamp-down gate is Q2. A1 and B1 are given to a min gate whose output is R3.
R3 and Q3 are given to a max gate whose output is T1. Then, P3 & T1 are given to
another max gate whose output is the carry function C2. The two outputs S1 and C1
are given to another sum function of a half adder where S1 and C1 are added and the
Sum function of the redundant binary adder can be obtained.
Let take an example by taking A1 = + 1, B1 =+1
P1 = −1, Q1 = −1, R1 = 1, J1 = −1, K1 = 1
M1 = −1, N1 = −1, O1 = 1,U1 = −1, V1 = 1, E1 = −1, F1 = 0,
G1 = 0, H1 = −1
X1 = −1, Y1 = −1, Z1 = −1, W1 = −1, S1 = −1
M1 = −1, N1 = −1, P1 = −1, Q1 = −1, R1 = −1, T1 = 1, C1 = 1
P2 = 1, Q2 = 1, R2 = −1, J2 = −1, K2 = −1
C1 = 1, M2 = −1, N2 = −1, O2 = 1,U2 = −1, V2 = 1, E2 = −1, F2 = 0,
G2 = 0, H2 = −1
X2 = −1, Y2 = 0, Z2 = −1, W2 = 0, S2 = 0
In the above example, we have seen that by giving A = +1 and B = +1, the sum
output will be 0 and the carry output will be 1 which is the outputs of redundant
binary adder. In this way, all the inputs can be tested in the circuit.
In TQCA, layout of Fig. 8 has total 95 numbers of Ternary QCA cell for the first
stage sum output. In TQCA, layout of Fig. 8b has total 43 numbers of cells for carry
output. In TQCA, layout of Fig. 8c is same as earlier Fig. 8a, which is the layout of
final sum output. This layout has also 95 numbers of cells. Here, total layout area
is 0.35 µm2
. The total number of cells is (95 + 43 + 95) = 233. In this layout, the
delay of output is after four clock cycles. Therefore, the cost of the proposed ternary
redundant adder is = Area × Delay × Cell complexity = 0.35 µm2
× 4 × 233 =
326. All the proposed layouts are implemented in TQCA designer software tool [12].

Fig. 8 Redundant adder in Ternary QCA a First stage sum S1 b Carry C1 c Final sum S2 d Final
sum simulation result

4 Conclusion
Miniaturization and speed have become an arising focus area in emerging nano-
electronics domain, which motivate nanoelectronics domain interest nowadays for
compact and high-computation speed circuit design. While noticeable in state-of-
the-art technology for an adder has been reported in QCA, there is less amount
of work on ternary-based adder. This article has presented advancement in ternary
logic-based adders to improve the computation speed. Simulation results of these
adders are correctly verified in comparison with truth table. Ternary QCA approach
can be applied to the proposed architecture such as adder, decoder, and binary incre-
ment and decrement for efficiently. Therefore, these assure the new architectures a
potential candidate for miniaturization of nanocircuit design.
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