A Study On Double Gate Field Effect Transistor For Area And Cost Efficiency

ISSN 2349-7815
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
Vol. 2, Issue 2, pp: (55-59), Month: April 2015 - June 2015, Available at: www.paperpublications.org
Page | 55
Paper Publications
A Study On Double Gate Field Effect
Transistor For Area And Cost Efficiency
Arindam Chakraborty1
, Sima Baidya2
1,2
M.Tech Student, 1,2
West Bengal University of Technology, India
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the
title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are
simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal.
Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect
to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic
capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS
technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with
minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with
respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used
to successfully manufacture the new FET structure.
Keywords: Fabrication, Double Gate, MOSFET device, multifunctional MOS, TFT, CMOS Technology.
I. INTRODUCTION
For past few decades the challenge for VLSI has been integration of an ever increasing number of devices with high yield
and reliability. The law of Moore’s has been achieved by dramatic scaling of MOSFET physical dimensions which led to
gaining speed and density [1].The CMOS channel length is scaled to the nanometer regime for which the device begin to
lose their insulating properties as the thermal injection and quantum- mechanical tunneling phenomenon [2]. Hence
results to rapid rise of the standby power of the chip. When a limit is placed on the integration level as well as on the
switching speed for which a pessimistic predictions concerns the rate of technology process for semiconductor industry
[3]. To follow the Moore’s law new device structure had been proposed like double gate SOI MOSFET, D-channel
MOSFET [4] [5] perhaps these device requires more complex process technology but lacks in scalability [6]. In this
article an alternative approach to sustain the speed and density rate of modern integrated circuits [7], but in this approach
i.e. the proposal as stated in this work is based on increasing the functions of an individual MOSFET device neither by
shrinking its dimensions nor by adding more gates. By implementing the proposal as explained in these paper a series of
device can be produced, but in here the area had been constricted to Double Gate FET, which is having two functionality
pMOS and nMOS. This result to save silicon area and increases the circuit speeds.
II. STRUCTURE OF THE DEVICE
Fig.1 illustrated the cross -section structure of bulk double gate field effect transistor and this device is designed from a
bulk MOSFET by adding extra p-doped poly layer on the top of this device. For obtain the proper functionality of this
device, one of the n+ regions should be short circuited by the metal contact with one of the upper p+ regions in extra poly
layer. The extra p-poly layer has been doped for the formation of junction-less Thin Film Transistor (TFT) module on the
top of the MOSFET, as the final device is able to behave like an inverter or buffer rather than a bulk MOSFET. The gate
of the device controls at the same time as the conductivity of the upper and lower channels enables the switching from the
nMOS to the pMOS behavior depending on the voltage which is applied to the gate terminal. The complementary

ISSN 2349-7815
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Paper Publications
structure is also obtained by simply replacing the p-doped region with n-doped region and vice versa and this device is
formed by a p-channel MOS, whereas the Thin Film Transistor module behaves as a n-channel transistor. Normally for
obtained higher performance epitaxial silicon layer is used instead of poly-layer. Here in this case the single crystalline
silicon layer can be formed by using an epitaxial lateral overgrowth technique [8] where the single crystalline silicon seed
is growth through the metal contact by using undoped Selective Epitaxial Growth (SEG) process. This can be carried out
at less than 7000
C by applying any one of the H2/SiH4/Cl2 gas system. The alternative way is to use a Leaser-induced
Epitaxial Growth (LEG) technology [9], [10].
Fig.1 Structure of a Bulk Double Gate Field Effect Transistor
III. MODE OF OPERATION
The operation mode of the double gate controlled field effect transistor consider the situation in which the S (source)
terminal is connected to ground D(drain) terminal is connected to VDD.
When the gate voltage is less than the threshold voltage i.e. V tn (Vg<Vtn), whereas the p-doped poly layer on the top of
the gate allowing current to flow from the supply voltage to the output terminal. So the device behaves like a p-channel
fully Depleted SOI device with the Drain terminal as a source and metal contact as a drain.
When gate voltage (Vg) increases, the upper poly layer deplete until the p channel is completely pinched off, and the
electron channel under the lower gate - oxide increases. The width Wd of the depletion region is greater than the thickness
Xt of the poly layer when Vg is beyond the threshold voltage. This results the metal terminal is isolated from the supply
and the device behaves as a bulk n-channel MOS.
The upper Thin Film Transistor module to behave as an enhancement device rather than a depletion p channel Field
Effect Transistor if the combination of the chosen gate work function with relatively small thickness of the extra poly
layer , applied as such allows for the turning off of the device for relatively low gate values. The threshold voltage value
increases towards negative values, which enables the enhancement mode behavior by using n+ doped gate instead of P+
doped gate
IV. NUMERICAL SIMULATION
Double Gate FET operates as two enhancements n-channel and p-channel MOS, which are connected as shown in the fig
2.a. for more emphasis in fig 2.b. the simulation, had been carried out using Sentaurus (Synopsys) [11]. A rectangular
voltage is applied to the gate i.e. drain terminal to VDD and the source terminal connected to ground, the device behaves
as an inverter at the metal contact terminal which shows an inverted signal with respect to one of the applied to gate.
The proposed device consists of a bulk 0.18μm nMOS with a junction less TFT module. Furthermore there is a poly-
silicon of 100nm thick p-doped with boron concentration of 1016
cm-3
, the upper and lower gate of 5.2nm thickness. Hole

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assumed for a poly-silicon with mobility of 9cm2
/Vs [12], the mobility of TFT device with gate oxide of 5.3nm is in order
of 30cm2
/Vs [13]. Parameters like doping-dependent degradation, degradation due to high electric fields and interface
effects during the simulation. There are two types of threshold voltages of double gate nMOS are Vtn and Vtp, when VG is
less than Vtp behaves like a pMOS device with drain terminal as a source and hence the current goes from the drain
terminal to the metal contact terminal, in case where VG is greater than Vtn the device behaves as a bulk nMOS and hence
the current flows between the metal contact and the source terminals.
(a) (b)
Fig.2 nMos Double gate equivalent circuit (a), and TCAD device simulation results (b) obtained by applying a rectangular
voltage pulse to the gate of a Double Gate device drain at 2.8V and source connected to ground. The solid line shows the
behavior of the metal contact terminal.
V. FABRICATION AND EXPERIMENTAL RESULTS
The results from the simulations have shown that double gate FET was realized in 1.5μm CMOS technology with a 9
mask fabrication process
A. Fabrication Samples:
The device structure analyzed where p-doped silicon substrate of resistivity of 50-70 Ωcm, a p-well had been created with
2 X 1013
cm-2
with boron implant at 60keV for hosting the devices. In account of n+
type regions are formed with a 2 X
1015
cm-2
with arsenic implant at 110keV. The gate is of poly-silicon doped with 8 X1015
cm-2
phosphorus implant at
80keV. The poly gate formation and self-aligned n+
implant and poly re-oxidation a thin 100nm a Si Layer deposited at
5500
C. The layer is implanted with Boron (1012
cm-2
BF2 at 50 keV) to form a channel above the underlying poly gate in
addition to it a poly gate is etch used thereafter to define the device. The p+
contacts are simultaneously formed with other
p type layers with a 2X1015
cm-2
BF2 implant at 80 keV. Top and bottom of gate oxides thickness are 11nm and 21.5nm
respectively as indicated by ellipsometric measurements.
Fig 3a is the final result of the fabrication process, where the source and body terminals of device have shorted together
marked by SB i.e. the source terminal.
B. Results of Experiment:
When voltage is supplied to drain terminal i.e. VDD and the source (source and body terminals shorted) terminal connected
to ground. As shown in the Fig 3b. In this condition the device behaves as an inverter at the metal contact terminal an

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inverted signal with respect to the one applied to the gate. The gain measured of the device for supply voltage 1.5V was
greater than 40 in absolute value, the short circuit current is 5 X 10-11
A/μm, whereas the measured steady state leakage is
in the order of 3.6 X 10-14
A/μm which is very considering the utilized process Technology.
(a) (b)
Fig. 3. Micrograph of 1.5μm Double Gate MOS device (a) and DC measurements of the metal contact terminal voltage as a
function of the gate voltage in inverter mode (b), i.e. with the SB(Source Body) terminal connected to ground and drain at 2.8V
VI. CONCLUSIONS
In this work the device proposed seems to be an alternative approach focusing on increase the functions of a single device
rather than shrinking the dimensions of a bulk MOSFET or adding more control gates with a very complicated process
technology. The simulation results showed the electrical characteristics and details fabrication process which also
explains a fully compatible CMOS process can be used to successfully manufacture the new FET structure. Numerical
Based simulations showed details about the double gate FET behavior and the correlations existing between the different
geometrical and physical parameters of the device.
The proposed technology will also enable the fabrication of Static RAM cells with only 3 transistors rather than 6, with
minimum dimensions and single bit line, saving silicon area and increasing the memory performance in comparison with
the bulk CMOS technologies. It is also observed that combinational and sequential circuits using the proposed method,
with respect to CMOS show a drastic decrease of both device number and parasitic capacitances which results to
improvement of the circuit speed.
REFERENCES
[1] S. Koba et al., ―Channel length scaling limits of III–V channel MOSFETs governed by source–drain direct
tunneling,‖ Jpn. J. Appl. Phys., vol. 53, no. 4S, p. 04EC10, 2014.
[2] S. E. Thompson and S. Parthasarathy, ―Moore’s law: The future of Si microelectronics,‖ Mater. Today, vol. 9, no. 6,
pp. 20–25, 2006.
[3] Q. Xie et al., ―Comprehensive analysis of short-channel effects in ultrathin SOI MOSFETs,‖ IEEE Trans. Electron
Devices, vol. 60, no. 6,pp. 1814–1819, Jun. 2013.
[4] H.-S. P. Wong, ―Beyond the conventional transistor,‖ Solid State Electron., vol. 49, no. 5, pp. 755–762, 2005.
[5] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, USA: Wiley, 2007.
[6] J.-P. Colinge, FinFETs and Other Multi-Gate Transistors. New York, NY, USA: Springer-Verlag, 2007.

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[7] F. A. Marino and G. Meneghesso, ―Double-halo field-effect transistor—A multifunction device to sustain the speed
and density rate of modern integrated circuits,‖ IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4226–4234, Dec.
2011.
[8] K.-S. Lee et al., ―Low-temperature solid phase epitaxial regrowth of silicon for stacked static random memory
application,‖ Jpn. J. Appl. Phys., vol. 50, no. 1S1, p. 01AB06, Jan. 2011.
[9] Y.-H. Son et al., ―Laser-induced epitaxial growth (LEG) technology for high density 3-D stacked memory with high
productivity,‖ IEEE Symp. VLSI Technol., Jun. 2007, pp. 80–81.
[10] Brunets et al., ―Low-temperature fabricated TFTs on polysilicon stripes,‖ IEEE Trans. Electron Devices, vol. 56, no.
8, pp. 1637–1644, Aug. 2009.
[11] Sentaurus Device User’s Manual, Version G-2012, Synopsys, 2012.
[12] S. D. S. Malhi et al., ―p-channel MOSFET’s in LPCVD polysilicon,‖ IEEE Electron Device Lett., vol. 4, no. 10, pp.
369–371, Oct. 1983.
[13] N. Lifshitz and S. Luryi, ―Enhanced channel mobility in polysilicon thin film transistors,‖ IEEE Electron Device
Lett., vol. 15, no. 8, pp. 274–276,

A Study On Double Gate Field Effect Transistor For Area And Cost Efficiency

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