A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
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This document describes a new cache architecture that aims to reduce energy consumption in last-level caches (LLCs) through selectively powering down cache ways in a dynamic manner. It proposes a way-filtering technique to logically increase the cache associativity of powered-down LLCs without reducing performance. Experimental results show the dynamic scheme reduces LLC energy consumption by 34-40% and overall system energy by 9.2% compared to conventional static cache configurations. The architecture is analyzed and implemented using Modelsim and Xilinx ISE software.
A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
- 1. A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption ABSTRACT: Last-level caches (LLCs) help improve performance but suffer from energy overhead because of their large sizes. An effective solution to this problem is to selectively power down several cache ways, which, however, reduces cache associativity and performance and thus limits its effectiveness in reducing energy consumption. To overcome this limitation, we propose a new cache architecture that can logically increase cache associativity of way-powered-down LLCs. Our proposed scheme is designed to be dynamic in activating an appropriate number of cache ways in order to eliminate the need for static profiling to determine an energy-optimized cache configuration. The experimental results show that our proposed dynamic scheme reduces the energy consumption of LLCs by 34% and 40% on single- and dual-core systems, respectively, compared with the best performing conventional static cache configuration. The overall system energy consumption including CPU, L2 cache, and DRAM is reduced by 9.2% on quad- core systems. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
- 2. SOFTWARE IMPLEMENTATION: Modelsim Xilinx ISE