Summary - Adaptive Insertion Policies for High Performance Caching. Qureshi, et al.
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The document discusses adaptive insertion policies for high-performance caching, focusing on cache replacement strategies like LRU (Least Recently Used) and enhanced methods such as LRU Insertion Policy (LIP) and dynamic insertion policies (DIP). It analyzes the impact of these policies on cache performance using a variety of benchmarks and emphasizes the importance of workload adaptation and low overhead. The work highlights that the proposed methods show improvement while maintaining access times similar to traditional LRU caching.
Summary - Adaptive Insertion Policies for High Performance Caching. Qureshi, et al.
- 1. Adaptive Insertion Policies for High Performance Caching Qureshi, et al. EECE527 - Paper Summary Jose Pinilla
- 2. Cache Replacement Policies ● Victim Selection Policy ○ LRU ● Insertion Policy ○ MRU ○ LRU
- 3. LRU (Baseline) LRU replacement (commonly used):
- 4. Belady’s OPT Optimal page replacement algorithm (Changes Victim Selection Policy): LRU replacement (commonly used):
- 5. LIP (LRU Insertion Policy) LIP (LRU Insertion Policy) LRU replacement (commonly used): 7 7 0 7 1 0 2 1 0 3 1 0 4 1 0 2 1 0 3 1 0 3 2 0 3 2 1 0 2 1 0 7 1
- 6. Belady’s OPT LIP (LRU Insertion Policy) LRU replacement (commonly used): 7 7 0 7 1 0 2 1 0 3 1 0 4 1 0 2 1 0 3 1 0 3 2 0 3 2 1 0 2 1 0 7 1
- 7. Cyclic Reference Model for j = 1 to N instructions read (a1 ...aT ) for j = 1 to N instructions read (b1 ...bT ) Let there be an access pattern in which (a1 · · · aT )N is followed by (b1 · · · bT )N Cache Size K (K < T) N >> T N >> K/ϵ
- 8. Access Pattern: LRU Step 1 a1 a2 a3 aT K TN
- 9. Access Pattern: LRU Step 2 a1 a2 a3 aT K TN
- 10. Access Pattern: LRU Step X a1 a2 a3 aT K TN
- 11. Access Pattern: LRU Step X>T*N a1 a2 a3 aT TN b1 b2 b3 bT K TN
- 12. T Access Pattern: LIP Step 1 a1 a2 a3 aT TN b1 b2 b3 bT N K
- 13. T Access Pattern: LIP Step 2 a1 a2 a3 aT TN b1 b2 b3 bT N K-1
- 14. T Access Pattern: LIP Step X>T*N a1 a2 a3 aT TN b1 b2 b3 bT N K-1
- 15. Bimodal Insertion Control the percentage of incoming lines placed as MRU ϵ = Bimodal throttle parameter ϵ=1 => LRU ϵ=0 => LIP
- 20. Hit Rate Cache Size K (K < T) ϵ = Bimodal throttle parameter ϵ=1 => LRU ϵ=0 => LIP N >> T N >> K/ϵ
- 21. Benchmarks mcf art health 250M instructions obtained with SimPoint
- 22. Results 1 So they proved that it works…
- 23. Results 1 So they proved that it works… ...but don’t over do it (ϵ)...
- 24. Results 1 So they proved that it works… ...but don’t over do it (ϵ)... ...actually, let’s choose LRU on run-time sometimes.
- 25. DIP: Select Mechanism DIP - Global / DSS DIP - Set Dueling ATD: Auxiliary Tag Directory MTD: Main Tag Directory
- 26. DIP: Select Mechanism DIP - Global / DSS DIP - Set Dueling Dedicated-Set Selection Policy Static or Dynamic (+2 bits)
- 27. DIP: Select Mechanism DIP - Global / DSS DIP - Set Dueling Dedicated-Set Size Selection Policy
- 28. Run-time adaptation: PSEL values PSEL>=512 then LIP PSEL<512 then LRU
- 29. Hardware advantages ● LIP, BIP and DIP similar to current LRU approximations ● DIP does not require extra bits in the tag-store entry ● No major logic overhead means the cache access time is unaffected
- 30. Related Work R: Random, N: Random from the less recent half, F: Frequently ● Bypass ● Early Eviction ● Dynamic Exclusion
- 31. Remarks Retain some fraction of the working set Dynamically adapt to workloads and patterns Low overhead (Set dueling)
- 32. Questions?
- 33. Questions? What would be the behaviour if DIP used ATDs dedicated to LRU and LIP? ● Compare Amean Dynamic ϵ ● Can ϵ be extracted from PSEL?
- 34. References “Cache Replacement with Dynamic Exclusion”. Scott McFarling “Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching”. Qureshi et al. “Using SimPoint for Accurate and Efficient Simulation”. Perelman et al. “Adaptive Caching for High-Performance Memory Systems”. PhD Dissertation. Qureshi et al.
- 35. McFarling: Conflict Between Loops for i = 1 to 10 for j = 1 to 10 instruction a for j = 1 to 10 instruction b *(a10 b10 )10 = 0% (am ah 9 bm bh 9 )10 = 10% * ignoring loop Source: “Cache Replacement with Dynamic Exclusion”. Scott McFarling
- 36. McFarling: Conflict Between Loops Levels for i = 1 to 10 for j = 1 to 10 instruction a instruction b Direct-mapped (am ah 9 bm )10 = 18% Optimal am ah 9 bm (ah 10 bm )9 = 10% Source: “Cache Replacement with Dynamic Exclusion”. Scott McFarling
- 37. McFarling: Conflict within Loops for i = 1 to 10 instruction a instruction b Direct-mapped (am bm )10 = 100% Optimal am bm (ah bm )9 = 55% Source: “Cache Replacement with Dynamic Exclusion”. Scott McFarling