Advance Microprocessor application and its uses 2

EEN 15252: MICROPROCESSOR & APPLICATIONS
Lecture 19
Dr. Vishal Kumar Gaur

Microprocessor: 8085
The 8237 DMA Controller
Internal Registers
 The 8237 contains 344 bits of internal memory in the form of
registers.
Note: Each channel has its
own CAR, CWCR, BA and BWC.
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1. Current Address Register (CAR):
 Each channel has its own 16-bit current address register.
 This register hold the address of memory location to be accessed during current DMA
cycle.
 When a byte of data is transferred during a DMA operation, CAR is either
incremented or decremented depending on how it is programmed.
 It is read and write register.
 Divided into 2 parts: lower byte & higher byte
 In auto initialization mode, it initialized automatically with original address after EOP
Signal
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2.Current Word Count Register (CWCR): This current word count register programs a
channel for the number of bytes to transferred during a DMA action.
 Each channel has 16 bit current word count register.
 This register determines the number of transfers to be performed.
 The word count is decremented after each transfer the current count, indicate the
no. of pending transfer.
 When the value in the register reaches zero, a TC will be generated
 Divided into 2 parts: lower byte & higher byte.
 In auto initialization mode, it initialized automatically with original count value after EOP
signal.
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3. The base address (BA)
 Each channel has 16 bit base address register
 It is a write only register
 It hold original value of address during all DMA transfer i.e. the content of this
register not updated during DMA transfer
 When EOP is activated the 8237 transfer content of base register into current
address register in auto initialize mode.
 This register is written along with current address register during initialization format
is same as current address register
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4. Base word count register (BWCR)
 16 bit,write only,
 It hold original count value during all DMA cycle means content of this register
are not updated during DMA transfer.
 When EOP is activated the 8237 transfer content of this register into current word
register in auto initialization mode.
 This register is written along with current address register during initialization format
is same as current word register.
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5. Command Register (CR): It is 8-bit write only register.
This register programs the operation of the 8237 DMA controller.
i. Enable/Disable memory-to-memory transfer.
ii. Enable/Disable the DMA controller.
iii. Normal/Compressed timing.
iv. Fixed/Rotating priority.
v. Type of (active low/high) DMA request and acknowledge
signal.

5. Command Register (CR)
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6. Mode Register (MR): It is 8-bit write only register.
 It is used to set operative modes.
 It is used to program the following features of
each channel of 8237:
i. Read/Write/Verify transfer.
ii. Demand/Single/Block transfer mode.
iii. Single/Cascaded operation of 8237.
iv. Enable/Disable auto initialization.
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7.Mask Register Set/Reset (MRSR): It is 8-bit
write only register.
 It sets or clears the channel mask to
disable or
enable particular DMA channels.
8. Mask Register (MR): It is 8-bit write only register.
 It sets or clears all of the masks with one
command instead of individual channels as with
the MRSR.
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9. Status Register (MR): 8-bit read
only The status register
shows status of channel.
each
DMA
 The TC bits indicate if the channel has
reached its terminal count
(transferred all its bytes).
 When the terminal count is reached, the
DMA transfer is terminated for most
modes of operation.
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9. Status Register (MR): 8-bit read only
 Bits 0-3 indicate which channels have reached
a
terminal count and which channel has
pending DMA.
 These bits are clear automatically on reading
the status register and upon reset signal.
 Bits 4-7 are set whenever their
corresponding channel is requesting service.
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10. Request Register (RR): 8-bit write only
 It is used to request DMA through software
 Each channel has a request bit associated with
in the request register.
 Each register is set or reset separately.
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DMA Cycles:
 The 8237 is designed to operate in two major cycles: Idle Cycle and Active cycle
 Idle Cycle: When no channel is requesting service, the 8237 will enter the Idle cycle.
 In this cycle, the 8237 will sample the DREQ lines every clock cycle to determine if
any channel is requesting a DMA service.
 The device will also sample CS, looking for an attempt by the microprocessor to write or
read the internal registers of the 8237.
 When CS is low and HLDA is low, the 8237 enters the Program Condition. The processor
can now establish, change or inspect the internal definition of the part by reading from
or writing to the internal registers.
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DMA Cycles:
 Idle Cycle:
 Address lines A0 –A3 are inputs to the device and select which registers will be
read or written.
 The IOR and IOW lines are used to reads or writes the register.
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DMA Cycles:
 Active Cycle:
 When the 8237A is in the Idle cycle and a non-masked channel requests a DMA service,
the device will output an HRQ to the microprocessor and enter the Active cycle.
 It is in this cycle that the DMA service will take place, in one of three modes:
 Single Transfer Mode
 Block Transfer Mode
 Demand Transfer Mode

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Active Cycle:
1. Single Transfer Mode
 Transfers one data unit (like a byte or word) at a time.
 The DMA controller transfers a single piece of data from the source to the destination.
 After this one transfer, 8237 gives up control and waits for the processor to approve
the next transfer.
 Means, once it completes the transfer of one data item, it does not continue
automatically; it needs to be triggered again.
 Situations where data needs to be moved one piece at a time, often used with
slower peripherals or for precise control.

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Active Cycle:
1. Single Transfer Mode
 Once the transfer is complete, HRQ goes inactive, temporarily releasing the bus back
to the
processor. It allows the processor to use the bus, if needed.
 To start another transfer, the DMA controller reasserts the HRQ signal (again go active)
 And, upon receipt of a new HLDA, another single transfer will be performed.
 The controller keeps track of how many pieces of data (words) need to be transferred. After each transfer, this count is decremented
(reduced by one).
 The address for the next data item to be transferred is also updated after each transfer. Depending on whether you are transferring
data up or down in memory, the address will be incremented or decremented.

Active Cycle:
2. Block Transfer Mode
 The device is activated by DREQ to continue making transfers during the service until a
TC,
caused by word count going to FFFFH, or an external EOP is encountered.
 DREQ need only be held active until DACK becomes active. Again, an Auto-initialization
will occur at the end of the service if the channel has been programmed for it.
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Active Cycle:
3. Demand Transfer Mode
 Unlike Block Transfer Mode, where a large block of data is transferred in one go,
Demand
Transfer Mode is more flexible. It can handle data transfers that occur intermittently or
in small quantities.
 Sometimes, I/O device may need some time to process or handle the data
that was
transferred during the previous DMA service.
 If the I/O device was busy or unable to keep up with the data transfers (e.g., it
needed to
perform other operations or process data), there could be a pause or delay..

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Active Cycle:
3. Demand Transfer Mode
 After the I/O device has had a chance to catch up, the DMA service is re-established
by
means of a DREQ.
 During the time between services, when the microprocessor is allowed to
operate, the intermediate values of address and word count are stored in the
8237 Current Address and Current Word Count registers.

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Active Cycle:
Cascade Operation
 This mode is used to cascade more than one 8237 together for simple system expansion.
 The HRQ and HLDA signals from the additional 8237 are connected to the DREQ and
DACK signals of a channel of the initial 8237A.
 This allows the DMA requests of the additional device to propagate through the
priority network circuitry of the preceding device. The priority chain is preserved and
the new device must wait for its turn to acknowledge requests.
 Since the cascade channel of the initial 8237 is used only for prioritizing the additional
device, it does not output any address or control signals of its own.

Active Cycle:
Cascade Operation
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Transfer Types:
 Each of the three transfer modes can perform three different types of transfers.
 These are read, write, and verify.
 Write transfers move data from an I/O device to the memory by activating MEMW and
IOR.
 Read transfers move data from memory to an I/O device by activating MEMR and IOW.
 Verify transfers are pseudo transfers.
 In verify transfers, the 8237 operates as in Read or Write transfers generating
addresses, and responding to EOP, etc.
 However, the memory and I/O control lines all remain inactive. The ready input is
ignored in verify mode.
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Advance Microprocessor application and its uses 2

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