ALL FLOWS.pptx it's about Asic design flow
- 2. Steps Specifications Architecture Rtl coding Rtl simulation Synthesis Pnr(placement&routing) Signoff {STA,PV,FV,EMIR,VCLP}
- 3. Specifications The vendor or client provide the specifications like High performance Area Low power consumption Low cost
- 4. Architecture According to specifications we built blue print of chip All details on proccessors,memories&how they are connected How much block area is used &how much cost required and how much power consumed
- 5. Rtl coding Base on architecture we will write rtl code We build digital design of seqt ckts&comb ckts by using Hdl,vhdl,Verilog,system Verilog
- 6. Rtl simulation Functional verification is done in this process Aftr rtl design we apply test cases in verification stage Test cases are called behavioural simulations such as NC SIM,TOGGLE COVERAGE
- 7. Synthesis The conversion of rtl code into gatelevel netlist It is two types 1)logical aware 2)physical aware Logical aware :netlist,lib,sdc,upf Physical aware: all inputs but extra i/p is defp
- 8. Pnr (placement&routing) According to frontend (rtl) design team,which we consider as inputs to pnr,in manufacturing a realistic IC.
- 10. SYNTHESIS FLOW INPUTS Netlist file Lib file Sdc file Upf file Def file Lef file Tlu+ file Spef file Tf file Saif file Mmmc file(.view)
- 11. NETLIST(.V) In netlist we have connectivity information of macros, cells,io ports A list of electronic components in circuit
- 12. Lib (library file) Lib file contains library name,tech node, functionality Operating conditions-fast fast,slow slow, typical typical PVT condition-process voltage temperature. VTh-threshold voltage- hvt, lvt,svt,ulvt Pin info- pin name,pin direction,pg pin names, Timing –setup rise / fall hold rise/ fall Units- resistance,capacitance,area,power,voltage
- 13. Sdc (synopsys design constraints) Sdc contains clock info,timing info Timimg constraints #Timing interface #Timing exceptions #Design rule constraints Create_clk set_load set_false_path set_max_cap create_generated_clk set_driving_cell set_multicycle_path set_max_trans set_clk_latency set_input_delay set_halfcycle_path set_max_fanout set_clk_uncertainity set_output_delay Set_clk_transition
- 14. Upf(unified power format) if the block is working on multivoltage,multipower domain then we require upf file Upf consists of power info of complete design There are 2 types of power format Primary power ( core rings ,rails, stripes) Secondary power ( isolation cells,retention cells, level shifters) Syntax – create_power_domain_PD_ORCA_TOP create_power_domain_PD_RISC_CORE create_supply_net_vss_domain create_supply_net_vdd_domain create_supply_port_vss_domain
- 15. Def (design exchange format) Def file is represented of physical layout of IC in ASIC format Def file is strongly connected to lef file,both can display the physical design It is generated by pnr tool stage by stage It contains logical design data& physical design data logical-connectivity info Physical-placement location of components
- 16. Sanity checks 1. Netlist 2. Lib 3. Sdc
- 17. Netlist 1. Vdd should not tied to ground 2. Floating of I /p & o/p 3. Vdd&Vss shorts 4. No multi driven nets 5. Unloaded outputs 6. Combinational feedback
- 18. Lib In lib we will check inconsistency b/w logical lib & physical lib
- 19. Sdc 1. Unconstrained endpoints 2. I/p & o/p delay 3. Port io missing delay 4. Multi clk driven registers 5. No clk reaching flipflop 6. Linking related issues
- 20. Analyze In analyze stage it will read all required inputs,check the syntax errors for loaded inputs Here the tool read Verilog & check for any syntax errors like missing modules,unreserve references , black boxes #Analyze_format_Verilog
- 21. Elaborate At this stage converting technology dependent to getch independent During elaboration the tool ,if the design is hierarchy If hierarchy is unique the run will proceed ,otherwise run stops Elaborate_template.
- 22. Specify constraints AREA #POWER # TIMING Auto ungroup dynamic-clock gating multibit Boundary optimization static-power gating sizing Area recovery swapping Area optimization ungrouping path grouping
- 23. Optimize We will optimize the process for better performance
- 24. Compile It is used to check sematic errors from top of flow to bottom of flow
- 25. Insert Dft(design for testing) At this stage we will add logic to the design,to check functionality the block
- 26. Compile Ultra incrementals At this stage before it will check errors stage by stage In ultra incrementals stage its resume process from copile ultra incremental stage
- 30. Floor plan Objective : floorplan is nothing but partition of core area& die area In which there are 5 parameters 1. Aspect ratio : H/W 2. Utilization : macro area+std cell area+blockages/total core area#how much area we utlized 3. Die area :we are placing i/p ports o/p ports i/o ports by using IO file 4. Row site :macros are placing in between rows 5. Blockages : partial,hard,soft,
- 31. Inputs : All inputs ,IO file Outputs : Floordef pre - checks We should see no over laps of macros&ports Check proper offset of ports
- 32. Powerplan objective : Power plan is nothing but distributing of power for each&every cell of macros,std cells Steps : io pads , trunks, core rings ,stripes , rails, Inputs : all inputs +floorplan def Outputs : powerplan def Post checks : all cells should get power :fix any pg shorts&opens in design :check DRC’S
- 33. Pre –placement Tie cells –tie high , tie low Endcap cells- cells are placed at end of rows Decap cells- temporary capacitors between ground due to dynamic IR drop Spare cells- to modify& improve functionality of design , spare cells are extra cells Tap cells- they are used avoid latch-up problem in CMOS. filler cells- the Filler cells are non-functional cells used to continue the VDD and VSS rails. They are used to establish the continuity of the N-well and the implant layers on the standard cell rows. Filler cells have no logical functionality . They are used to fill empty space in the standard-cell rows to ensure that all power nets are connected.
- 34. Placement pre-checks Legality Congestion Check_mv design Opens&shorts Check terminals objective : *placement is nothing but placing std cells in design *it also determine routability in design
- 35. Steps Coarse placement Detailed placement Legalization HFNS(high fanout net synthesis) Scan chain reorder optimization
- 36. INPUTS : Powerplan def All inputs Scan def OUTPUTS : Placment def
- 37. Post -checks Congestion Utilization Legalization –no overlaps #check_legality Timing QOR Check_pg_connections Drc
- 38. Cts ( clock tree synthesis) Pre – checks Legality checks Pg connections Congestion Timing qor - #report_timing .#report_global_timing Timing drv,s – max_tran,max_cap,max_fanout OBJECTIVE : distribution clks for each&every seq cells
- 39. Inputs and Outputs INPUTS : Placement def file Cts spec file OUTPUTS : Cts def
- 40. Steps Clock tree initialization Synthesied cts Ccd optimization Gate by gate cts Clock cell relocation Drv fixing
- 41. Post –checks Skew balancing Mininimze insertion delay Drv Timing(setup&hold) Less congestion Utilization in limit
- 42. Routing Routing is a process of making physical connection between or among signal pins by following DRC rules
- 43. Types of routing Global routing Track assignment Detail routing Search & repair
- 44. Goals Minimize the total interconnect or wire length Complete the routing with in the area of design No DRC violations Meeting the timing No LVS errors
- 45. Pre checks
- 51. Post checks Timing must be clean Drv Drc’ No congestion No legality No lvs