Analysis and characterization of different high density on chip switched capacitor power converters in 130nm technology

UNIVERSITY OF TEXAS AT DALLAS
ERIK JONSSON SCHOOL OF ENGINEERING &
COMPUTER SCIENCE
EECT 6379 ENERGY HARVESTING, STORAGE
AND POWERING FOR MICROSYSTEMS
SPRING 2015
Project Report: Team 2D
Analysis and Characterization of Different
High Density On-Chip Switched Capacitor
Power Converters in 130nm Technology
- Prepared By
Aalay Kapadia Net ID: adk130330
Auto-Reconfigurable Switched-Capacitor DC-DC Power
Converter
Nishtha Sharma Net ID: nxs135730
Switched-Capacitor Power Converter with Closed-Loop
Interleaving Regulation
4/26/2015
In this project, initially we reviewed various design techniques for implementing high density On-chip
Switched-capacitor (SC) power converters and after analysis, we have worked on the implementation of the
best techniques to solve the important aspects of a power converter design : Power Density, Power
Consumption & Efficiency mainly focusing on the power density as per our project requirement.
Specifications Auto Reconfigurable Interleaving
Regulation
Technology 130nm 130nm
Vin 1.2 to 1.8V 1.2 to 1.8V
Vout 2-2.5V 2V
Power Efficiency 65% to 92% 61% to 82.5%
Switching Frequency 0.5MHz-1MHz 1MHz-15MHz
Load Current < 30mA 5mA
Area(mm2
) 0.01725 0.28
Power Density(Watt/mm2
) 0.43826087-1.33333333 0.021429-0.032143

ERIK JONSSON SCHOOL OF ENGINEERING & COMPUTER SCIENCE University Of Texas At Dallas 2
I. PROBLEM & SOLUTION
For switched capacitor power converter (SCPC) designs at
the power level below 100mW, if the capacitors can be
integrated on‐chip, then the entire system can achieve
monolithic implementation. This is very important for the
applications requiring small system form factors. On‐chip
capacitors can be implemented using high‐density capacitor
technologies such as deep trench capacitors in IBM SOI
processes. However, that will lead to high fabrication cost.
With standard CMOS process, from the perspective of circuit
designs (neither process, nor device), We are asked to suggest
the most effective techniques to achieve high density on‐chip
SCPC.
Switched capacitor is one of the DC-DC type converters.
Similar to the switch mode power converter, a SC converter
also consists of two major components, the power stage (also
known as the charge pump), along with a closed loop
feedback controller (and/or a feed-forward controller). The
charge pump is an array of capacitors, which act as energy
storage elements. The use of power switches and clock control
signals leads to appropriate switching actions that cause
charge storage on the pumping capacitors and then charge
transference to output load, with an ultimate goal to
maintain a desired voltage value. The major benefit of SC
power converters is their capability for monolithic integration
at low power levels, since they employ capacitors as energy
storage devices, instead of bulky, off-chip inductors. One
major drawback of traditional SC DC–DC converters is their
ability to provide only a single Conversion Gain (CG), which
is defined as the ratio of the output voltage to the input voltage
of the converter. If the output voltage moves from this desired
level, the efficiency of the SC converter reduces. If the
variation is large, the power loss becomes unacceptably high
due to charge redistribution. Hence, to accommodate a large
output voltage range and to be capable of powering
Dynamic Voltage Frequency Scaling (DVFS) based
applications, a SC power converter with a fixed CG does not
suffice. To overcome this drawback, state-of-the-art SCPC
designs involve the use of reconfigurable power stages to
supply variable output voltages. While such converters are
capable of delivering multiple voltage levels, it is done so
efficiently only at certain discrete levels, depending on the
topology of the reconfigurable charge pump and its
corresponding switching actions. Reconfigurable SC power
converters can be implemented using Series-Parallel switched
capacitor (SPSC) or Sequential switched capacitor (SQSC)
based on your application for which you are using. SPSC is a
reconfigurable SC power converter combined with
interleaving technique, which is popular among the most of
the designs.
To minimize the required capacitors and power switches in
SC power converters, multiple-output SC power regulators
can share capacitors and power switches in the power stage for
generating multiple regulated outputs and thus improving the
converter area efficiency.
As a design example, Fig. 1 shows the structure of an auto-
reconfigurable dual-output SC regulator, which consists of a
power stage for voltage conversion and a controller for output
regulation. In the power stage, there are 8 on-chip power
transistors, M11-M14 and M21-M24, 2 off-chip flying
capacitors Cf1, Cf2 and two output capacitors CL1 and CL2.
Proper operation sequence of power transistors and flying
capacitors can simultaneously produce two regulated output
voltages VOL and VOH in the proposed regulator. The
numbers of power transistors and off-chip flying capacitors
determine the total chip and board areas of the regulator. To
generate both 2x and 3x outputs, a total of 11 power
transistors and 3 flying capacitors are needed by using both
doubler and tripler together as shown in Fig. 1. The proposed
power stage can generate 2x (VOL) and 3x (VOH) outputs
simultaneously by reducing 3 on-chip power transistors and 1
off-chip flying capacitor compared with the conventional
approach, significantly saving both the chip and board areas.
Fig 1.Structure of auto-reconfigurable dual-output SC regulator.
In the controller shown in Fig. 1, the input sensing block
continuously detects the input voltage Vin. According to the
value of Vin, the power stage will be configured into the
conversion ratios 2x (for VOL), 3x (for VOH) or 2x (for
VOL), 2x (for VOH) in order to maintain high power
efficiency of the regulator under different input voltages. The
output sensing detector provides output voltages information
to a sub harmonic fixed on-time (SHFOT) control block that
regulates both outputs VOL and VOH. Hence, the control
scheme helps improve the light-load power efficiency of the
regulator and is suitable for low-power energy-harvesting
applications. As the load step has negligible impact on the
other output VOL, the proposed SHFOT control effectively
minimizes the cross-regulation between two different outputs.
In discrete-component realizations, minimizing the power-
stage component count and circuit complexity are the usual
cost constraints, whereas in IC realizations the required chip
area is important. Much more flexibility is available to the
designer in sizing components (switches and capacitors). We
designed the converter keeping that in mind. Although the
construction of capacitors has not been taken into account in
this paper, we have focused on using interleaving as an
approach to minimize the area of the device. We not only

focus on minimizing the area, but we also try to maximize the
output delivered as much as possible so that we get a high
power density.
In the next few sections, both Auto-reconfigurable and
Switched-Capacitor Power Converter and Switched-Capacitor
Power Converter with Closed-Loop Interleaving Regulation
are optimized for a high power density.
II. SYSTEM OVERVIEW, OPERATION & CONTROL
A. Auto-Reconfigurable Switched-Capacitor DC-DC Power
Converter
Fig. 2. Schematic of the proposed auto-reconfigurable 2x charge pump
Fig. 2 shows the structure of the proposed 2x/3x cross-
coupled SC-CP, which consists of a power stage realized by
power transistors Ml1-Ml7, Mr1-Mr7 and flying capacitors
Cl1-Cl2, Cr1-Cr2for voltage conversion,2x/3x adaptive
control circuitry to allow the proposed SC-CP automatically
performing the reconfiguration of voltage conversion ratios,
adaptive dead-time control circuitry (ADTCC) to boost the
power efficiency of the proposed SC-CP, and start-up
circuitry. Compared to the conventional 3x charge pump, no
extra power transistor or flying capacitor is added in the
proposed core 2x/3x charge pump as indicated in the
component-count comparison in Fig. 2. In fact, if any extra
power transistor is used, the size of all existing power
transistors should be increased in order to maintain the same
on resistance for the power efficiency consideration. Since the
whole circuit chip area is dominated by the area occupied by
power transistors, both extra power transistor(s) and other
enlarged power transistors would significantly increase the
chip area. As a result, the proposed 2x/3x SC-CP is an area-
efficient topology without using any extra power transistor.
The operational principle of the proposed SC-CP can be
best explained in two regions of Vin. When Vin< VR, the
proposed SC-CP is configured as a voltage tripler by the
adaptive control circuitry. The SC-CP operates in non-
overlapping clock phases φ1and φ2alternately. When φ1 =
VDD and φ2 = 0, switches Ml1, Ml3, Ml4, Ml6, Mr2, Mr5,
and Mr7 are on and other power switches are off. The voltage
across Cl1and Cl2 is charged to ~VDD, while the input supply
Vin stacks on the voltage stored in both Cr1and Cr2 in the
previous half-clock period to give the output voltage Vcp_out
≈3VDD. In the next half-clock cycle of φ1= 0 and φ2= VDD,
the operation of (Cl1, Cl2) and (Cr1, Cr2) is swapped. The
same output voltage (≈3VDD) can still be maintained. When
Vin > VR, the proposed SC-CP is configured as a voltage
doubler. Switches (Ml2, Mr2) and (Ml1, Ml4, Mr1, Mr4) are
always turned off and on, respectively, such that the voltage
on Cl1and Cr1is kept at VDD. The other eight power
transistors and capacitors Cl2and Cr2will operate alternately
in every half-clock period for charging and charge transfer
such that the output Vcp_out is maintained at ≈2VDD.
Fig. 3. Transistor level schematic of Power Stage
It should be noted that all transistors in the proposed SC-CP
are implemented using the standard single n-well 0.18-μm
CMOS. The substrate connections of all power transistors
shown in Fig. 2 ensure that no forward-biased p-n junction
will be turned on during different operating states.
Fig. 4. Two-Phase Non-Overlapping Clock Signals

B. Switched-Capacitor Power Converter with Closed-Loop
Interleaving Regulation:
a) Power stage
In order to minimize the area as well as get good efficiency as
an added benefit, we have chosen closed loop interleaved
charge pump design controlled by four phase complementary
clock signals as the solution design. With this configuration,
we get minimized area as well as a high efficiency out of the
power converter.
Since the first step in the design an interleaved switched
capacitor involves the design of the charge pump and so we
have described the operation of the device first. The design
consists of two parallel-connected cross-coupled voltage
doublers as shown in figure 1. The charge pump is controlled
by clock signals clki, where i = 1, 2, 3, 4, with a 90o phase
shift between each other. For example, clk1 and clk3 and used
for part 2 whereas clk2 and clk4 are used for part 1.
One of the major improvements of this topology is that the
gate control signals for each PMOS and NMOS power
transistors are generated internally. This avoids the need for
additional clock generators and voltage boosting circuits thus
saving a lot of area.
Fig. 5 A two-stage cross-coupled interleaved charge pump
Figure 6 shows all the four clock signals(clk1, clk2, clk3,
clk4) with a 90 degree phase shift between them. The detailed
operation of the device is as follows.
From figure 5 we notice that at any two instants, that two
clock signals are always high. This allows the pumping
capacitors to Vin whereas the remaining two are always
discharged to Vout. For a quarter time , both CLK1 and CLK4
are active, and CLK2 and CLK3 are low. This results in
voltage boost at node 1 and node 4 to 2Vin. These results in
turning ‘on’ of the transistor M1 and M7 and thus nodes 2 and
node 3 are charged to Vin. Thus the potential at node 1 and 4
are 2Vin and at 2 and 4 is Vin. Now the PMOS transistors M4
and M6 turned on to charge up the output voltage VO to
2VIN.
At this moment, there are indeed two nodes (1 and 4)
connected to the output, delivering the energy from the
pumping capacitors CP to the output. In the next quarter cycle,
CLK1 is still “1”, but CLK4 drops to “0” and CLK2 jumps up
to “1”. Accordingly, the nodes 1 and 2 will be connected to
2VIN, whereas the nodes 3 and 4 have the voltage potentials
of VIN. M4 and M8 will be turned on to charge up the output
voltage.
Fig. 6 Timing diagram of interleaving regulation
In figure 6, change in node voltages (V1, V2,V3,V4) along
with the complementary clock signals is depicted. Thus output
is charged to 2Vin for the entire clock cycle.
Although the case discussed above is ideal, in reality we
never reach a voltage of 2Vin at the output node. This happens
due to the turn on resistance of the power switches and charge
sharing between the output capacitor and the pumping
capacitor.
Due to the symmetrical structure of the circuit, similar
operations occur in other quarter cycles. The perpetual
presence of two high-voltage nodes connected to the output
lead to the improved reliability of energy sources at load
transient periods. 90° phase shift avoids the ripple peaks from
the two charging nodes occur at the same time, which
effectively reduces the peak-to-peak ripple voltage at the
output. Meanwhile, the current carried by each branch will be
half of the output current. This gives us the advantage of
reducing the sizes of the power switches thus reducing the
area of the power converter.
The output we get from this power stage is unregulated, so
we move onto the closed loop design for interleaved switched
capacitor power converter in the next section.
b) Closed loop design
In the previous section, we discussed the operation of a
cross-coupled interleaved charge pump. With the power stage,
we can’t control the duration of turn on time of the transistor.
In fact, the presence of parasitic capacitances also reduces the
power levels thus impacting the power density. With the
addition of a feedback controller to the interleaved charged
pump, we can increase the regulation of the output thus

reducing the output ripple thus increasing the power delivered
directly impacting the power density of the circuit.
The introduction of the closed loop control aids in achieving
the regulation at any precision voltage converter. The closed
loop control is implemented using the interleaved analog
PWM controller. In this circuit, the output voltage VO is
scaled down by using a voltage divider network. The scaled
voltage is then compared with the band gap reference voltage
at the input of the error amplifier. The error amplifier
amplifies the error with a finite gain, which determines the
resolution of the output ripple. The amplified error signal is
then compared with four 90° interleaving ramp signals at the
comparator array to produce the reset input for the
corresponding RS latch. The output signals from RS latch
determine the ending time of the converter’s duty ratio.
Fig. 7 Closed loop configuration of Interleaved switched capacitor power converter
During the startup, the output is relaxed with a zero voltage,
which leads to a large error signal expanding the clocks duty
ratios close to 100%. In that situation all four clocks will go
high at the same time inhibiting the turn “ON” of PMOS in the
power stage which happens to be the path for the output. In
order to limit the clocks duty ratios to the maximum turn on
time of 50% an AND array is employed at the final stage of
the control loop. In this case, all four cells in the converter will
be turned on to deliver the maximum power possible to the
output and charge up the output voltage within a short time.
III. PROJECT DESIGN/MODELING/ANALYSIS DETAILS
Converter
Fig. 8 Block level Diagram of schematic of Auto-Reconfigurable SCPC
In this section of the report, we discuss the design details of
our project. The SC power converter was designed with IBM
130nm technology. In the SC-CP shown in Fig. 3, power
transistors (Ml6, Mr6) and (Ml7, Mr7) are cross-coupled
connected and their states of switching are controlled by node
voltages at l5 and r5. Since node voltages of l5 and r5 are not
under the control of the non-overlapping clock signals and
both voltages will change at the same time during switching
transitions, there exist shoot-through currents that flow from V
cp_out to Vin due to simultaneous conduction of transistors
(Ml6, Ml7) and (Mr6, Mr7) during switching transitions in
both doubler and tripler configurations. Hence, the power
efficiencies of the SC-CP are degraded especially under light-
load condition.
Fig.9 Schematic of the 2x/3x adaptive control circuitry.
The ADTCC, that is realized by four additional
transistors (Mla1, Mla2, Mra1, Mra2) and two level shifters to
control the switching of power transistors Ml7and Mr7, is
shown in Fig. 3. For instance, when Ml6is turning on and Ml7
is turning off, transistor Mla1 is turned on and is directly
connecting between Vcp_out and the gate of Ml7. Dynamic
current through Mla1 helps turn off Ml7much faster than
turning on Ml6. On the other hand, when Ml6is turning off
and Ml7 is turning on (transistor Mla1 is off), Mla2 is turning

on simultaneously as turning off Ml6, because gate and
source of Mla2and Ml6 are connected opposite to each other.
Fig. 10 Adaptive Clock Booster Schematic
Since transistor Ml7 can only be turned on after turning on
Mla2 and the delay created by the on-resistance of Mla2, Ml7
is guaranteed to be turned on after turning off Ml6. The break-
before-make mechanism is thus established to minimize the
shoot-through current through Ml6 and Ml7during switching
transitions in both doubler and tripler configurations. Without
the loss of generality, both Mra1and Mra2 can ensure power
transistor Mr7 (1) to be turned on slower than turning off Mr6
and (2) to be turned off faster than turning on Mr6 As a result,
the proposed ADTCC can improve the efficiencies of the
proposed 2x/3x SC-CP, especially under light-load condition.
It should also be noted that the sizes of additional transistors
(Mla1/Mra1) and (Mla2/Mra2) are 233 and 20 times smaller
than that of Ml7/Mr7. The area occupied by additional
transistors is insignificant compared to the total chip area.
Fig. 11 Sensing Comparator Diagram Schematic
Fig. 9 shows the proposed 2x/3x adaptive control circuitry,
which consist of a two-phase non-overlapping clock generator,
an input sensing-comparator, a gate control generator, and an
adaptive clock booster. The input sensing comparator is used
to determine the configuration of the SC-CP under different
input voltages. The input voltage Vin is compared with the
reference voltage VR to generate an output state that will feed
into both the adaptive clock booster and the gate control
generator for properly controlling the SC-CP. The arbit stage
and hysteresis in the input sensing comparator can ensure that
the output voltage Vo2is always defined even if both DC input
voltages of the comparator are equal. In particular, Vo2is set
to VDD when Vin= VR. Therefore, the proposed SC-CP can
either be 3x or 2x configuration even when Vin is in the
vicinity of VR. Undefined output states of the comparator,
otherwise, would generate incorrect gate signals for power
transistors through the gate control generator and the adaptive
clock booster, resulting in malfunctioning of the SC-CP due to
simultaneous conduction of power transistors. Both gate
control generator and adaptive clock booster in Fig. 9 are used
to provide appropriate gate voltages for power transistors
Ml1– Ml7, Mrl– Mr7 in Fig. 3.
Fig. 12 Gate Control Generator Design Schematic
The gate control generator is realized by NAND gates and
chains of inverters as buffers to provide gate voltages of all
power transistors except Ml4and Mr4.Both gate voltages of
Ml4are Mr4 are generated by the adaptive clock booster
circuit. In particular, a local supply Vadapt is created to
adaptively switch to VDD or 2VDDby connecting Vadapt to
either node l4 or node r4 through two cross-coupled pMOS
transistors Mpc1and Mpc2as shown in Fig. 9. Voltage Vadapt
is further stabilized by a small-size on-chip poly-poly
capacitor Cpoly of 8 pF in our design. For example, when the
proposed SC-CP functions as a doubler, voltages at nodes l4
and r4 are either at 0 V or VDD. Both Mpc1and Mpc2 ensure
that voltage Vadapt is equal to VDD.
The SCPC with interleaving regulation was designed with
IBM 130nm technology. Interleaving greatly reduced the area
of our design by reducing the sizes of filtering components.
For the cross coupled charge pump, the sizes of the transistor
were kept constant with only one constraint i.e. Wp =2*Wn to
maintain the same turn on time for both PMOS and NMOS.
The pumping capacitor was optimized mainly for reduced area
but the benefit we got out of doing this was extremely low
output voltage ripple.

Fig. 13 Block diagram of Switched-Capacitor Power Converter with interleaving
regulation
For the feedback controller, ideal components were used
for comparator and error amplifier keeping our focus on area
and power rather than accuracy of output ripple voltage. The
buffer size was chosen so as to drive the pumping capacitors.
Figure 14 depicts the simulated interleaved clock signals and
the voltage potentials at node 1,2,3 and 4.
IV. KEY RESULTS
Converter
Fig. 16 Given Result Based Graph for 350nm Technology
TABLE I
Fig. 17 Graph Based On Proposed Results for 180nm Technology
Fig. 18 Given Result Based Graph for 350nm Technology
R Iout Vout vexp eff
1 100 0.018 1.8 2 0.9
2 1000 0.00195 2 2 0.975
3 10000 0.00018 1.8 2 0.9
4 100000 0.000019 1.9 2 0.95
5 1000000 0.0000018 1.8 2 0.9
At 500KHz Frequency and 1.2 V as Vin

TABLE II
Some of the key results are shown for calculating the input
voltage dependence and maximum current delivered to the
load which directly impacts the power delivered to the load.
In table III, efficiency is calculated for various input voltages.
TABLE III
The converter has 1.2V input and generates output at 2V
.When an ideal SC converter is unloaded, the DC voltage
conversion ratio M = VO/VDD assumes a value M = Mi,
which is uniquely determined by the converter topology. For
example, the basic cross coupled voltage doubler shown has
the ideal step-up conversion ratio Mi = VO/VDD = 2.
Fig. 21 Efficiency vs input voltage
As the input varying from 1.2 to 1.8V, the output voltage is
regulated at around 2 V, with a maximum load current of
3.0856 mA.
TABLE IV
Vin Vout Iout(mA)
1.2 1.994 3.072
1.3 1.999 3.078
1.4 2.003 3.083
1.5 2.005 3.081
1.6 2.001 3.071
1.7 2.003 3.084
1.8 2.006 3.079
Vin Iin Vout Iout pout Vout expected eff
1 1.2 0.0025 1.8 0.0042 0.00756 2 0.9
2 1.32 0.0055 2 0.006 0.012 2.2 0.909091
3 1.44 0.0093 2.2 0.0065 0.0143 2.4 0.916667
4 1.56 0.014 1.9 0.0076 0.01444 2.6 0.730769
5 1.68 0.02275 1.8 0.01 0.018 2.8 0.642857
6 1.8 0.02 2 0.0115 0.023 3 0.666667
At 10Kohm resistance and 1MHz switching frequency

Fig. 22 Output voltage vs Input voltage vs Output Current
V. PROJECT SUMMARY, HIGHLIGHTS AND INNOVATION
Two switched capacitor power converter with different
configurations are presented in this project to maximize the
power design. In design a) i.e. the Auto reconfigurable SCPC ,
the adaptive control circuitry is developed to automatically
change the conversion ratio of the proposed charge pump
under different input voltages due to coupling variations and
thus enable the DC/DC regulator to maintain high power
efficiencies. The adaptive dead-time control circuitry can
minimize the shoot-through current resulting from the
simultaneous conduction of power transistors during switching
transition and can thus greatly enhance power efficiencies of
the proposed SC-CP under different load currents. The
proposed auto-reconfigurable 2x SC-CP is suitable for high-
power demand transcutaneous power transmission through
inductive coupling in cochlear and retinal implants. The
summary is as below:
TABLE V: PERFORMANCE SUMMARY OF THE Given SC-CP
Fig. 23 A two-stage cross-coupled interleaved charge pump[2]
TABLE VI: PERFORMANCE SUMMARY OF design a
In design b) i.e. the SCPC with interleaving regulation,
the main focus was to maximize the power delivered keeping
the area as low as possible for the converter. The innovation in
the converter is that since the capacitor sizes for the five
capacitors were decreased by a factor of almost 100 each from
the original values proposed in [13], we propose that they can
be fabricated on-chip. The value of pumping capacitor is taken
as 20n Since the power converter’s output is well regulated
the output at 2 V with the input of 1.2V, they will serve their
purpose by providing the desired supply.
Specifications Auto Reconfigurable
Technology 130nm
Vin 1.2 to 1.8V
Vout 2-2.5V
Power Efficiency 65% to 92%
Switching Frequency 0.5MHz-1MHz
Load Current < 50mA
Area(mm2
) 0.01725
Power Density(Watt/mm2
) 0.43826087-1.33333

TABLE VII: PERFORMANCE SUMMARY of design b
Specifications Interleaving Regulation
Technology 130nm
Vin 1.2 to 1.8V
Vout 2V
Power Efficiency 61% to 82.5%
Switching Frequency 1MHz-15MHz
Load Current 5mA
Area(mm2
) 0.28
Power
Density(Watt/mm2
)
0.021429-0.032143
Cp 20nF
Cout 40nF
Output ripple 0.08mV
For the area calculation, since layout wasn’t available, Area
of the power converters was extracted from the layout XL
option present in schematic editor and the dimensions were
taken from edge to edge.
When the values of both the output and pumping capacitor
is chosen to be 1nF, the output voltage is well regulated with
an output ripple of 170mV.
In summary, we have successfully implemented two power
converters and optimized both of them for maximum power
density.
ACKNOWLEDGMENT
This work was done as part of coursework of course
EECT6379 under guidance of Prof. Dongsheng Brian Ma
(Ph.D.) at University Of Texas At Dallas. Any opinions,
findings and conclusions, or recommendations expressed in
this material are those of the authors and do not necessarily
reflect those of Prof. Dongsheng Brian Ma (Ph.D.) and
University Of Texas At Dallas.
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APPENDIX
A) Auto-Reconfigurable Switched-Capacitor DC-DC Power
Converter
Area calculation of using layout XL option present in cadence
schematic editor.
Area estimation using Layout XL.
Dimensions: 138.5921*124.4523 um^2
B) Switched-Capacitor Power Converter with Closed-
Loop Interleaving Regulation:
Area calculation of using layout XL option present in cadence
schematic editor.
Area estimation using Layout XL.
Dimensions: 369.270*771.680 um^2.

Analysis and characterization of different high density on chip switched capacitor power converters in 130nm technology

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Analysis and characterization of different high density on chip switched capacitor power converters in 130nm technology