Application of Solder Paste

APPLICATION OF SOLDER PASTE IN PCB CAVITIES*)

Markus Leitgeb, Christopher Michael Ryder
Austria Technologie & Systemtechnik AG
Leoben, Austria

ABSTRACT

INTRODUCTION

Two major drivers in the electronics industry are electrical
and mechanical miniaturization. Whereas lines and spaces
have been getting smaller over the years (current HDI
standard is 50/50µm), mechanical miniaturization has thus
far been mostly limited to decreasing layer-count and
material thickness.

The use of cavities in the PCB industry is nothing all too
new. Local depth reduction (through various methods and
technologies) has long been applied to achieve a number
of design and/or application linked results. With new
technologies available allowing for component terminals
in the cavity itself (pads, etc.), the challenge of soldering
these components is becoming a stronger focal point.

One further solution is local height reduction through the
introduction of recessed cavities on the PCB. These
cavities can be used assembling components and/or device
elements to reduce overall PCBA z-axis dimension.
The cavity forming method referred to in this paper allows
for unlimited flexibility in shape and depth of these
cavities, thereby enabling greater freedom in material
selection and PCB design rules. Solderable surfaces and
soldermask patterns can also be applied on the cavity
layer.
As much as this provides a solution for z-axis
miniaturization, the challenge of assembling components
with standard and even advanced surface mount
technologies remains a critical aspect of successful
implementation of these technologies.
This paper aims to demonstrate initial trials to address the
challenge of component assembly within recessed cavities
on the PCB using various stencil configurations. Two
major proponents of the trials presented here are AT&S
with its 2.5D® Technology and Christian Koenen GmbH,
a stencil manufacturer.
The ultimate target of these trials and this paper is not a
final and universal solution, but rather attempts to clarify
the initial challenge scope and explore existing or further
possible solutions.
KEYWORDS

Component placement itself is not the biggest challenge in
the assembly process. It is well known that the assembly
of the components can be easily altered by adjusting the zAxis in the placement programming. However, one
challenge remains largely open: “How do I get a solder
paste into the cavity in an effective and process-efficient
manner?”
Of course, there are well known methodologies in the
market like jet printing and nozzle dispensers, which can
fulfill these requirements, but there are as yet still
limitations in terms of throughput, application volumes,
etc… As stencil printing is still the most widely used and
currently the most cost effective solution in the market for
volume production of standard PCBAs, it would make
sense to have a cavity solution which is compatible with
standard stencil/paste SMT.
AT&S (PCB manufacturer) has started together with
Christian Koenen GmbH (stencil manufacturer) a project
to identify the any current limits of using stencil printing
for solder paste application in cavities of varying depths
on a single test vehicle.
The next logical step after this investigation would, of
course, be to identify any other applicable paste printing
methods and possible variations in terms of component
soldering and reliability performance when comparing to
standard (cavity-free) surface mounted components.

PCB, Cavities, Solder paste in cavity, Step stencil
*) Originally distributed at the International Conference on Soldering and Reliability”
Toronto, Ontario, Canada; May 4-6, 2011

1

TEST MATERIALS AND EQUIPMENT

test) (see figure 2). Minimum distance from the test
pattern to the cavity wall for the experiment was 2mm.

Test Vehicle
As there is no standard test vehicle for the testing of
solder paste printing in cavities available, an attempt was
made to create a vehicle based as much as possible on a
stencil printing manufacturer`s design. The vehicle
created contains a number of typical component
footprints: 0603, 0402, 0,5mm and 0,4mm fine pitch pads,
and µBGAs with 0,5 mm 0,3 mm pitch (see Figure 1).

Figure 2. Test board with cavity areas

Figure 1. Test pattern
The exact copper feature dimensions can be found in
Table 1 and 2 below.
Table 1. Copper features

Footprint
0603
0402
Fine Pitch 0,5mm
Fine Pitch 0,4mm
µBGA 0,5mm
µBGA 0,3mm

Pad Dimensions
x [mm]
y [mm] P [mm]
0,66
1,06
1,50
0,46
0,66
1,00
0,31
1,66
0,50
0,26
1,66
0,40
d = 0,33
0,50
d = 0,20
0,30

Figure 3. Schematic process flow of cavity formation.

Table 2. Stencil apertures
Footprint
0603
0402
Fine Pitch 0,5mm
Fine Pitch 0,4mm
µBGA 0,5mm
µBGA 0,3mm

The build for the 2,1mm thick PCB was a 12 layer multilayer with Panasonic R1650M material (halogenated
epoxy resin based prepreg). This stack up and production
method enables the removal of 5 layers at varying depths
on a single card. The specific depth is achieved by the
application of a paste on the release layer with subsequent
relamination of the entire board. A laser cutting process
then trims and cuts at the predetermined shape to separate
the relaminated layers from the release layer. The final
step is then “cap removal” and paste stripping (see Figure
3). What remains is the solder footprint pattern. Diverse
surface finishes and also application of solder mask may
be employed in the cavities, but for the sake of this
experiment solder mask was only used on the outer layer
(0µm cavity). Entek HT (Organic surface protection) was
used as a surface finish for all solderable surfaces.

Stencil Aperture
x [mm]
y [mm]
0,60
1,00
0,40
0,60
0,25
1,60
0,20
1,60
0,33
0,33
0,20
0,20

This footprint pattern was placed on the test vehicle on
recessed areas of 0µm (no cavity), 50µ, 250µm, 500µm
and 750µm (The 100µm cavity was not employed for this

The unused copper on all inner layers was “hatched”,
which means they were not full copper surfaces. This is
standard practice in PCB design to achieve warpage
control and enhance thermal reliability performance.
Fiducials for SMT registration and cavity printing were
located on outer layer to enable printing the solder paste
in a one step process. Therefore the only influence for
registration is the layer shift caused by the several
relamination steps. However, this shift is by any means
compatible with current HDI manufacturing standards.
Testing Material and Equipment


2

To distinguish whether solder paste type (ball size) plays a
role in cavity printing performance, two different types of
solder pastes were used for the printing trials:
•
•

Manufacturer A (Type 3)
Manufacturer B (Type 4)

Figure 5. Squeegee blade with moveable parts
The sloped edges of the step openings ensure that excess
paste is removed from the stencil during printing (see
Figure 6).

Both solder pastes are widely used lead-free pastes for
volume stencil printing process.
The solder paste printing system used in this trial is a two
part system consisting of a step stencil and a customized
squeegee. The stencil was a laser cut stainless steel stencil
glued in polyester mesh and tensioned in an aluminum
frame. The dimensions of the stencil were (736 x 736 x 40
mm³). Stencil base thickness was 1mm. Stencil thickness
in the print area was 80µm. The depth of the stencil is
adjusted for each individual cavity and is furthermore
recessed on the top side of the stencil to achieve a
consistent aspect ratio throughout the print (i.e. the stencil
thickness 80µm is constant for all areas despite cavity
depth) (see Figure 4).

Figure 6. Cross section of Step stencil with sloped edge
The printer used was an Ersa Versaprint. The parameters
employed are shown in Table 3.
Table 3. Printing parameters
Parameter
Speed F/B
Squeegee pressure F/B
Snap off speed
Snap off distance

Value
50/ 50
25/ 25
50,0
2,0

Unit
mm/s
N
mm/s
mm

A Koh Young KY-3020T tabletop full automatic system
was used for the inspection of the volume and printed
surface coverage of solder paste.
Figure 4. Overview Step Stencil on PCB
The customized steel squeegee is 150mm in length and is
designed with movable sections to account for variable
depth. Therefore the multi-depth top side contour of the
stencil is accounted for through the varying pressure of
the movable squeegee sections (Figure 5).

A Cyberscan CT300 was used for profiling the solder
paste and 3D image evaluation after printing.
TEST METHODOLGY
The first step in the trial methodology included the depth
inspection and verification of the cavity depths on the test
vehicle (nominal depths: 0µm, 50µm, 250µm, 500µm,
750µm). Measurements points were soldermask surface
on the outer layer (outermost point of solder stencil
contact) to copper surface in each cavity. Depth tolerance
should be understood as the accumulation of the single
layer thickness tolerances (i.e. +-10% for dielectric
thickness). All test vehicles were verified for as within
tolerance for the given depths.
The stencil and customized squeegee were subsequently
installed and registered. The squeegee must be aligned to
the specific cavities for which the movable parts are
designed. This was done manually using the alignment of
arrow markings on both stencil and squeegee (Figure 7).


3

Figure 7. Alignment marking on Squeegee and stencil
The type 3 solder paste was mixed accordingly and
applied to the step stencil surface. Using the print
parameters described above in Testing Material and
Equipment, several test prints were then carried out to
verify effectiveness and accuracy.
The test prints were first inspected manually with an
optical microscope to inspect general print status in terms
of accuracy and application. Considerations were made to
evaluate any obvious differences between the cavities, the
component footprints and/or solder paste types (type 3
and 4 were used, as mentioned above) (Figure 8).

Figure 9. 3D paste print verification with CT300 (750µm
cavity)
The first paste used for testing was the lead free type 3
from manufacturer A. Ten test vehicles were then printed.
Subsequently the 10 PCBs were analyzed for paste
volume and surface coverage (2D evaluation of print
coverage versus aperture opening) with the Koh Young.
The results will be discussed in the “evaluation” section of
this paper.
The next step after ultrasonic cleaning of the step stencil
was to print the type 4 solder paste onto 10 further test
vehicles. The test vehicles were subsequently analyzed in
the Koh Young AOI device. The complete results, as
stated above will be discussed at a later point.
Due to obvious and somewhat expected paste voids with
the type 3 solder paste (see Figure 10), it was decided to
proceed only with type 4 as it was deemed more suitable
for further analysis.

Figure 8. Alignment check with optical microscope
(750µm cavity)
During manual inspection some slight misregistration was
observed, whereupon the stencil was realigned to the PCB
test vehicle. New prints were carried out, inspected and
registration was verified.
The test prints were then measured with the solder paste
print AOI device (Koh Young) in order to assess transfer
efficiency (paste volume V) and surface coverage (SC)
measurement capability for varying focal points (i.e.
varying cavity depths). The device was able to
successfully scan the single test vehicle despite the depth
variations. The results were verified using the CT300
(Figure 9).

Figure 10. Comparison type 3 and 4 solder balls in fine
pitch area
A further 10 cards were paste printed with type 4.
Furthermore the element of stencil cleaning was added
with this run, whereas the stencil was cleaned with a
solution after every 2nd print. The cards were subsequently
analyzed with the AOI device.


4

To summarize, a total of 30 test vehicles were printed as
such:
•
•
•

Excluding the 0µm surface coverage values, a mean value
of 95,1% was found over all footprints and depths.

10 PCBs with type 3
10 PCBs with type 4
10 PCBs with type 4 (with stencil cleaning)

TEST EVALUATION
After AOI measurement and evaluation was carried out
the data was entered into Minitab and Excel to explore
interactions, deviations and trends.
The first trial with type 3 paste revealed the following
results. Broken down into component footprint, paste
volume analysis revealed a clear and reproducible trend.
The paste volume at 0µm (i.e. no cavity) was on average
113,9%. Highest value was 147,9% on the 0402 footprint
and lowest value was 57,9% on the 0,3mm µBGA.
The overall higher values on the 0µm footprints are linked
to the presence of solder mask and in particular the 25µm
delta between copper and solder mask height (Figure 11).
The exceptionally low value of 57,9% on the 0,3mm
µBGA can be traced to the presence of solder paste voids
due to the nature of the type 3 solder ball size (as
illustrated above in Figure 10). Otherwise a general trend
of decreasing paste volume was observed as cavity depth
increased (with few exceptions). Excluding the 0µm paste
volume values, a mean value of 62,9% was found over all
footprints and depths.

Figure 11. Type 3 – Paste Volume per footprint and
cavity depth
In terms surface coverage (SC) a similar trend was of
course noticeable (Figure 12). Highest value was for 0402
footprint with 116,7% at 0µm and lowest value was
0,3mm µBGA footprint with 57,1% at 750µm. Reasons
for this variation are similar to those described above.
Otherwise a general trend of decreasing surface coverage
was observed as cavity depth increased (with few
exceptions).

Figure 12. Type 3 – Surface coverage per footprint and
cavity depth
The second trial with type 4 paste revealed the following
results. Broken down into component footprint, paste
volume analysis revealed similar results with some
variation to those of the type 3 paste. Excluding the 0µm
paste volume values, a mean value of 93,7% was found
over all footprints and depths. Compared to the 62,9%
mean paste volume value found with the type 3 paste, a
clear indication of improved performance is recognizable
(Figure 13).

Figure 13. Type 4 – Paste Volume per footprint and
cavity depth
In terms of surface coverage a similar trend was
noticeable, whereas the deviation between type 3 and type
4 was not as pronounced. The mean value of 102,7% over
all footprints and depths (excluding the 0µm depth)
compared to the 95,1% from type 3 is indicative of the 2D
nature of the testing (Figure 14).


5

Figure 14. Type 4 – Surface coverage per footprint and
cavity depth

Figure 16. Type 4 / with cleaning – Surface coverage per
footprint and cavity

The third trial employed type 4 paste with manual stencil
cleaning after each second print. The following results
were found. The mean paste volume value for all
footprints on the 0µm depth was 89,4%. The mean paste
volume value for all remaining footprints and depths was
70,7%. Here we see a lower overall volume when
compared to the type 4 paste without cleaning results
(Figure 15). However, the standard deviation for the type
4 with cleaning is 4% lower than without cleaning
(respectively 10% and 14%). The greatest observable
difference in standard deviation was seen in 0,3mm
µBGA: without cleaning 35,9% and with cleaning 19,1%.

The interaction plots between the individual test elements
(paste type, footprint, cavity depth and cleaning y/n)
revealed some clear indications.

Figure 15. Type 4 / with cleaning – Paste Volume per
footprint and cavity depth

Figure 17. Interaction plot for paste volume

The data for surface coverage with type 4 and stencil
cleaning after every second print presented a more
homogenous pattern than the other trials, especially
considering the 0µm footprint performance with the
cavity depth performance (Figure 16). Similar to the
situation described above with paste volume, surface
coverage overall is less with the type 4 cleaning trials
compared to the type 4 without cleaning trials. However,
once again we see a lower standard deviation with the
type 4 with cleaning trials (with cleaning 6,9% and
without cleaning 10,7%).

First we will investigate the interaction plot for paste
volume (Figure 17). The interaction between paste and
component footprint demonstrates a slight overall
superiority of the type 4 paste versus type 3. However, the
performance indicators run relatively parallel (i.e. better
performance on larger component footprint compared to
smaller).

The interaction between paste type and cavity depth
demonstrates somewhat better overall performance with
the type 4 paste. However, performance in the cavities
regardless of depth can be viewed as consistent. The
visible difference on the 0µm cavity depth is, once again,
linked to the presence of solder mask and therefore a
higher contact plane for the stencil.
The interaction between footprint and cavity depth
demonstrates consistent patterns with exception of the
0,3mm µBGA. In general, the larger component footprints
fared better as did the smaller depths. The 0,3mm µBGA
showed a consistently low performance regardless of
cavity depths.


6

The interaction between paste and cleaning is moot as the
cleaning trials were carried out only with the type 4.
The interaction between component footprint and cleaning
provides conflicting results. The 0,3mm and 0,5mm pitch
BGAs as well as the 0603 demonstrated slightly improved
performance in terms of volume when cleaned, the
remaining footprints, however, demonstrate slightly less
volume when cleaned.
The plot for cavity depth and cleaning demonstrates the
largest interaction at 0µm cavity depth. Here we see the
largest reduction of volume on the type 4 with cleaning
compared to no cleaning. Otherwise, no major interaction
can be extrapolated.
Now we will examine the interaction plot for surface
coverage (Figure 18). The interactions for paste/ footprint,
paste/ cavity, footprint/ cavity and footprint/ cleaning can
be considered in line with the paste volume interaction
analysis described above.
The plot for cavity depth and cleaning revealed a
somewhat more pronounced interaction for the larger
cavity depths. These depths demonstrated an increased
surface coverage after cleaning.

coverage. The biggest variations in performance can be
accounted for with the solder mask height delta over
copper on the 0µm cavity depth and the 0,3mm µBGA.
Regarding the solder mask we would suggest this is a
common a phenomenon on standard non cavity PCBs. In
future trials, there would be the possibility of applying
solder mask in the cavities as well to aid in more direct
comparison.
The somewhat inferior performance of the 0,3mm µBGA,
we would also suggest, is demonstrative of general
limitations of the stencil printing method on this pitch and
not related necessarily to cavity depth.
It would appear after these initial trials that with some
further optimization in terms of both material and process
improvements could be made to increase transfer
efficiency and surface coverage. Such optimizations
would also have to consider the specific PCB design and
component footprint (design rules).
Considerations will be made on our part to examine the
manufacturing and reliability performance of the paste
printed cavity PCBs as a next step. Additional and/or
alternative printing and soldering processes and materials
may be drawn into the further trials.

Figure 18. Interaction plot for surface coverage
SUMMARY
The initial task at hand was to evaluate the feasibility and
effectiveness of using a standard method of paste printing
to print on to PCBs with varying cavity depths. The trials
employed, however, a non-standard stencil and squeegee
solution.
Despite the usage of non-standard materials (i.e.
stencil/squeegee system and multi-cavity depths PCB), the
printing process as such did not deviate from general
volume manufacturing practices.
In general, the trials demonstrated successful solder paste
printing results in terms of paste volume and surface

7

Application of Solder Paste

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