Article_IPC_EXPO_Dec_2003
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The document discusses the challenges of meeting tighter registration requirements for high layer count printed circuit boards (PCBs). As PCBs increase in density and complexity to accommodate growing performance needs, manufacturers must improve registration tolerances. This requires advances in materials, processes, and equipment. A registration capability model is presented and used to predict success rates given specific tolerance requirements. Meeting future demands will require improved process control, reduced variation, and continued technology development across the PCB industry.
Article_IPC_EXPO_Dec_2003
- 1. Meeting the Registration Challenges for High Layer Count PCB’s Brad Hammack Multek Doumen, China Abstract The packaging industry is “pulling” the Printed Circuit Board (PCB) technology level in the direction of semiconductor requirements. High density PCB’s are becoming commonplace in the network routers, automated test equipment, and server sectors. The need for high density (> 150 IO/Sq. cm) is becoming a common requirement. In order to fan out the high density packages, many layers are being added as finer lines, spacing and via diameters are approaching conventional manufacturing limits. These attributes are driving changes in base materials, imaging, etching, plating, soldermask, testing processes, and registration systems. This paper examines trends in PCB attributes and utilitizes a registration model and the Rayleigh distribution to predict capability for advanced registration requirements. High Density Drivers There are multiple drivers for the increasing need for more function in less space. Drivers are added functions for character data, voice data, and image data. Additional drivers include increased memory and hard disk data transfer rates, surface area shrinks, increased use of ultra-small high speed circuits, increased number of high density components for speed acceleration, shorter distance between components, and reduced propagation delay. The rapid pace of change in packaging that has occurred in order to accommodate higher performance requirements, has posed several challenges in both PCB manufacturing and assembly processes. The increased density has lead to higher layer counts, demanding improved registration tolerances in both manufacturing equipment and PCB processes. Trends in machine tool performance are referenced in the figure below. The trends are paralleled in the PCB fabrication processes. Year 1970s 1980s 1990s 2000s Velocity (ipm) 400 800 2,000 3,000 Acceleration (g's) 0.2 0.6 1.5 2.0 Spindle Speed(rpm) 6,000 15,000 20-40,000 110,000- 175,000 Accuracy ±0.001" ±0.0005" ±2µm <2µm Repeatability ±0.0005" ±0.0003" ±1µm <1µm Figure 1-- Machine Tool Performance Trends Source: By Charles Wang, Ph.D., and Bob Thomas (1970 – 1990 Data) PCB designs have experienced similar trends in line width and finished via diameter reduction. The reduction in line width is approaching “semiconductor” level dimensions. Available equipment and material sets are approaching conventional limits for volume production processes.
- 2. Figure 2: Line Width Reduction Figure 3: Via Size Reduction
- 3. While PCB photolithography and drilling processes have been utilized to demonstrate the trends over the past two decades, the packaging trend of pad attachment density continues to accelerate. This trend is a contributing factor for the addition of layers to PCB’s Figure 4: PCB Attachment Pad Density Registration Modeling As the number of layers increases in PCB’s, the registration systems have to be adapted to provide capability for more exacting tolerances. A simple registration capability model can be used to determine your current registration budget. The significant factors affecting registration are photo plotting, artwork dimensional stability, base material dimensional stability, post etch punch variation, drilling set up and hole location. Process Variable Std Dv Artwork Plotting 0.814 Artwork Front-Back 1.400 Post Etch Punch 0.383 Dimensional Stability 1.620 Inner Layer Std Dev 2.322 Inner layer +/- 3 s 6.967 Drill Set Up 0.500 Hole Location 0.530 Drill s 0.729 Drill +/- 3s 2.186 Overall 's' 2.434 Overall +/- 3s 7.302 Drill + (?) Capability (2 x Overall +/- 3s) 14.604 Figure 5: Registration Capability Model Source (Format): American Testing Corporation
- 4. Taking the capability model a step further, and utlilizing a weibull distribution (Rayleigh) in this case, one can predict the success rate for a given registration requirement. Assume that the drill diameter is .0098”, the pad is .0188”, and there is a one mil annular ring requirement. Using the overall standard deviation from Figure 5 (2.434) Figure 6: Drill + 9 And the cumulative distribution function F(x) = 1-e-(r*2/(2*Sigma2)) Solving for F(x) = 0.6443. Given a PWB with 10,000 holes requiring the registration above, 6443 holes would be in tolerance. Figure 7 shows the effect of dimensional variability (standard deviation) and the requirement in order to achieve 100% success. Overall Std Dev F(x) r2/2*sigma2 c=sqrt(2*sigma) 2.434 0.6443 1.0339 2.2064 2.20 0.7179 1.2655 2.0976 2.10 0.7506 1.3889 2.0494 2.00 0.7837 1.5313 2.0000 1.90 0.8167 1.6967 1.9494 1.80 0.8489 1.8904 1.8974 1.70 0.8798 2.1194 1.8439 1.60 0.9086 2.3926 1.7889 1.50 0.9342 2.7222 1.7321 1.40 0.9560 3.1250 1.6733 1.30 0.9733 3.6243 1.6125 1.20 0.9857 4.2535 1.5492 1.00 0.9978 6.1250 1.4142 0.90 0.9994 7.5617 1.3416 0.80 0.9999 9.5703 1.2649 0.70 0.9999 12.5000 1.1832 0.60 1.0000 17.0139 1.0954 Figure 7: Cumulative Distribution Function With .001" Annular Ring, Clearance per side = .0035" 0.0045" Accuracy radius = .0035" Pad Dia ==> .0188" Drill Dia 0.0098"
- 5. Size, pattern, and positional tolerances are projected to advance (Figure 8), as packaging drives these changes. Additional requirements for conductive-anodic-filament (CAF) resistance has increased the concern over registration capabilities. New base materials designed to withstand higher thermal processes, exhibit less Z-axis expansion, and pass IST and T288 testing, with improved dimensional stability are rapidly being commercialized. Figure 8: Manufacturing Tolerances Roadmap Source: Japan’s Institute of Electronics Packaging (Modified) Conclusion As semiconductor and PWB technologies converge, PWB fabricators, equipment manufacturers and material suppliers must work jointly to develop solutions for next generation products. The next generation designs will require tighter controls for front to back registration, drill hole true position, improved soldermask registration, and high speed electrical test equipment for fine pitch area testing. Future demand for products that have more functionality will continue at an accelerated pace. The use of conventional process technology will gradually yield more inefficacious results. Significant improvement in process control, variation reduction, and investment in process development will be a common focus among fabricators trying to maximize their return on technology investment. Current 2003 – 2004 Short Term 2005 – 2006 Long Term 2007 - 2014 Manufacturing Tolerences Positional Tolerences Inner Layer Pattern µm Outer Layer Pattern µm Hole Position Accuracy µm Soldermask Registration µm Size Tolerances Line Width (Inner Layer) µm Line Width (Outer Layer) µm Tooling Hole Diameter µm Bow and Twist ±25 ±25 ±50 ±50 10 10 50 0.7% ±12 ±12 ±20 ±20 5 5 50 0.5% ±8 ±8 ±10 ±20 3 3 30 0.3%
- 6. Size, pattern, and positional tolerances are projected to advance (Figure 8), as packaging drives these changes. Additional requirements for conductive-anodic-filament (CAF) resistance has increased the concern over registration capabilities. New base materials designed to withstand higher thermal processes, exhibit less Z-axis expansion, and pass IST and T288 testing, with improved dimensional stability are rapidly being commercialized. Figure 8: Manufacturing Tolerances Roadmap Source: Japan’s Institute of Electronics Packaging (Modified) Conclusion As semiconductor and PWB technologies converge, PWB fabricators, equipment manufacturers and material suppliers must work jointly to develop solutions for next generation products. The next generation designs will require tighter controls for front to back registration, drill hole true position, improved soldermask registration, and high speed electrical test equipment for fine pitch area testing. Future demand for products that have more functionality will continue at an accelerated pace. The use of conventional process technology will gradually yield more inefficacious results. Significant improvement in process control, variation reduction, and investment in process development will be a common focus among fabricators trying to maximize their return on technology investment. Current 2003 – 2004 Short Term 2005 – 2006 Long Term 2007 - 2014 Manufacturing Tolerences Positional Tolerences Inner Layer Pattern µm Outer Layer Pattern µm Hole Position Accuracy µm Soldermask Registration µm Size Tolerances Line Width (Inner Layer) µm Line Width (Outer Layer) µm Tooling Hole Diameter µm Bow and Twist ±25 ±25 ±50 ±50 10 10 50 0.7% ±12 ±12 ±20 ±20 5 5 50 0.5% ±8 ±8 ±10 ±20 3 3 30 0.3%