![The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1
r2 ARM has 37 registers, all 32-bits long
r3 A subset of these registers is accessible
r4 in each mode
r5
r6
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
Current mode Banked out registers
7
Program Status Registers
31 28 27 24 23 19 16 15 10 9 8 7 6 5 4 0
N Z C V Q de J U n d e f
GE[3:0] i cond_abc
IT n e d E A I F T mode
f s x c
§ Condition code flags § T Bit
§ N = Negative result from ALU § T = 0: Processor in ARM state
§ Z = Zero result from ALU § T = 1: Processor in Thumb state
§ C = ALU operation Carried out § Introduced in Architecture 4T
§ V = ALU operation oVerflowed § Mode bits
§ Sticky Overflow flag - Q flag § Specify the processor mode
§ Architecture 5TE and later only § New bits in V6
§ Indicates if saturation has occurred
§ GE[3:0] used by some SIMD
§ J bit instructions
§ Architecture 5TEJ and later only § E bit controls load/store endianness
§ J = 1: Processor in Jazelle state § A bit disables imprecise data aborts
§ Interrupt Disable bits § IT [abcde] IF THEN conditional
§ I = 1: Disables IRQ execution of Thumb2 instruction
§ F = 1: Disables FIQ groups
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Confidential
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![Introduction to
Instruction Sets
11
ARM Instruction Set
§ All instructions are 32 bits long / many execute in a single cycle
§ Instructions are conditionally executed
§ A load / store architecture
§ Example data processing instructions
SUB r0,r1,#5 r0 = r1 - 5
ADD r2,r3,r3,LSL #2 r2 = r3 + (r3 * 4)
IF EQ condition true r5 = r5 + r6
ADDEQ r5,r5,r6
§ Example branching instruction Branch forwards or backwards relative to
B <Label> current PC (+/- 32MB range)
§ Example memory access instructions Load word at address r1 into r0
LDR r0,[r1] IF NE condition true, store bottom byte
of r2 to address r3+r4
STRNEB r2,[r3,r4]
Store registers r4 to r8 and lr on
STMFD sp!,{r4-r8,lr} stack. Then update stack pointer
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Arm architecture overview
- 1. ARM Architecture Overview 1 Development of the ARM Architecture § Processor Architecture = Instruction Set + Programmer’s model 4T 5TE 6 7 ARM7TDMI ARM926EJ- S ARM1136JF -S Cortex-A8/R4/M3/M1 ARM922T ARM946E-S ARM1176JZF-S Thumb-2 ARM966E-S ARM11 MPCore Thumb Extensions: instruction set Improved SIMD Instructions ARM/Thumb v7A (applications) – NEON Unaligned data support Interworking v7R (real time) – HW Divide Extensions: DSP instructions V7M (microcontroller) – HW Thumb-2 (6T2) Extensions: Divide and Thumb-2 only TrustZone (6Z) Jazelle (5TEJ) Multicore (6K) § Note: Implementations of the same architecture can be very different § ARM7TDMI - architecture v4T. Von Neuman core with 3 stage pipeline § ARM920T - architecture v4T. Harvard core with 5 stage pipeline and MMU 2 Confidential 1
- 2. ARM Architecture profiles § Application profile (ARMv7-A à e.g. Cortex-A8) § Memory management support (MMU) § Highest performance at low power § Influenced by multi-tasking OS system requirements § TrustZone and Jazelle-RCT for a safe, extensible system § Real-time profile (ARMv7-R à e.g. Cortex-R4) § Protected memory (MPU) § Low latency and predictability ‘real-time’ needs § Evolutionary path for traditional embedded business § Microcontroller profile (ARMv7-M à e.g. Cortex-M3) § Lowest gate count entry point § Deterministic and predictable behavior a key priority § Deeply embedded use 3 Programmer’s Model 4 Confidential 2
- 3. Data Sizes and Instruction Sets § When used in relation to the ARM: § Halfword means 16 bits (two bytes) § Word means 32 bits (four bytes) § Doubleword means 64 bits (eight bytes) § Most ARMs implement two instruction sets § 32-bit ARM Instruction Set § 16-bit Thumb Instruction Set § Latest ARM cores introduce a new instruction set Thumb-2 § Provides a mixture of 32-bit and 16-bit instructions § Maintains code density with increased flexibility § Jazelle-DBX cores can also execute Java bytecode 5 Processor Modes § The ARM has seven basic operating modes: § Each mode has access to own stack and a different subset of registers § Some operations can only be carried out in a privileged mode Mode Description Supervisor Entered on reset and when a Software Interrupt (SVC) instruction (SWI) is executed Exception modes Entered when a high priority (fast) interrupt is FIQ raised Entered when a low priority (normal) interrupt IRQ is raised Privileged modes Abort Used to handle memory access violations Undef Used to handle undefined instructions Privileged mode using the same registers as System User mode Mode under which most Applications / OS Unprivileged User tasks run mode 6 Confidential 3
- 4. The ARM Register Set User mode IRQ FIQ Undef Abort SVC r0 r1 r2 ARM has 37 registers, all 32-bits long r3 A subset of these registers is accessible r4 in each mode r5 r6 r7 r8 r8 r9 r9 r10 r10 r11 r11 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr Current mode Banked out registers 7 Program Status Registers 31 28 27 24 23 19 16 15 10 9 8 7 6 5 4 0 N Z C V Q de J U n d e f GE[3:0] i cond_abc IT n e d E A I F T mode f s x c § Condition code flags § T Bit § N = Negative result from ALU § T = 0: Processor in ARM state § Z = Zero result from ALU § T = 1: Processor in Thumb state § C = ALU operation Carried out § Introduced in Architecture 4T § V = ALU operation oVerflowed § Mode bits § Sticky Overflow flag - Q flag § Specify the processor mode § Architecture 5TE and later only § New bits in V6 § Indicates if saturation has occurred § GE[3:0] used by some SIMD § J bit instructions § Architecture 5TEJ and later only § E bit controls load/store endianness § J = 1: Processor in Jazelle state § A bit disables imprecise data aborts § Interrupt Disable bits § IT [abcde] IF THEN conditional § I = 1: Disables IRQ execution of Thumb2 instruction § F = 1: Disables FIQ groups 8 Confidential 4
- 5. Data alignment § Prior to architecture v6 data accesses must be appropriately aligned for access size § Unaligned addresses will produce unexpected/undefined results Byte access Halfword access Word access (byte aligned) (halfword aligned) (word aligned) 3 2 1 0 2 0 0 7 6 5 4 6 4 4 b a 9 8 a 8 8 f e d c e c c § Unaligned data can be accessed using multiple aligned accesses combined with shift/mask operations 9 Exception Handling § When an exception occurs, the core: § Copies CPSR into SPSR_<mode> § Sets appropriate CPSR bits § Change to ARM state 0x1C FIQ IRQ § Change to exception mode 0x18 0x14 (Reserved) § Disable interrupts (if appropriate) 0x10 Data Abort § Stores the return address in LR_<mode> 0x0C Prefetch Abort § Sets PC to vector address 0x08 Software Interrupt 0x04 Undefined Instruction § To return, exception handler needs to: 0x00 Reset § Restore CPSR from SPSR_<mode> Vector Table § Restore PC from LR_<mode> Vector table can also be at 0xFFFF0000 on most cores § Must be done in ARM state in most cores, but... ...Thumb-2 capable cores can do this in Thumb state 10 Confidential 5
- 6. Introduction to Instruction Sets 11 ARM Instruction Set § All instructions are 32 bits long / many execute in a single cycle § Instructions are conditionally executed § A load / store architecture § Example data processing instructions SUB r0,r1,#5 r0 = r1 - 5 ADD r2,r3,r3,LSL #2 r2 = r3 + (r3 * 4) IF EQ condition true r5 = r5 + r6 ADDEQ r5,r5,r6 § Example branching instruction Branch forwards or backwards relative to B <Label> current PC (+/- 32MB range) § Example memory access instructions Load word at address r1 into r0 LDR r0,[r1] IF NE condition true, store bottom byte of r2 to address r3+r4 STRNEB r2,[r3,r4] Store registers r4 to r8 and lr on STMFD sp!,{r4-r8,lr} stack. Then update stack pointer 12 Confidential 6
- 7. Thumb Instruction Set § Thumb is a 16-bit instruction set § Optimized for code density from C code (~65% of ARM code size) § Improved performance from narrow memory § Subset of the functionality of the ARM instruction set § Thumb is not a “regular” instruction set! § Constraints are not generally consistent § Targeted at compiler generation, not hand coding 13 Thumb-2 Instruction Set § Thumb-2 is a major extension to the Thumb ISA § Adds 32-bit instructions to implement almost all of the ARM ISA functionality § Retains the complete 16-bit Thumb instruction set § Design objective: ARM performance with Thumb code density § No switching between ARM-Thumb states § Compiler automatically selects mix of 16 and 32 bit instructions 14 Confidential 7
- 8. Thumb 2 Performance / Density 100% ARM code Thumb-2 Performance Random mix ‘Profiled’ mix 100% Thumb code Code density 15 Processor Cores 16 Confidential 8
- 9. ARM7TDMI Processor § Architecture v4T § 3-stage pipeline § Single interface to memory 17 ARM926EJ-S Processor ARM926EJ-S § Architecture v5TE § 5-stage pipeline § Single-cycle 32x16 multiplier § Caches and TCMs § Memory management unit (MMU) § 2 AHB memory interfaces § Jazelle technology 18 Confidential 9
- 10. ARM1176JZ(F)-S Processor Core § TrustZone § 8-stage pipeline § Branch prediction § Four AXI memory ports § IEM (Intelligent Energy Management) § Integrated VFP coprocessor 19 ARM11 MPCore Processor § 1 – 4 MP11 processors MP11 MP11 MP11 MP11 § Cache coherency § Distributed interrupt controller 20 Confidential 10
- 11. ARM Cortex-M3 Processor § Architecture v7-M (Thumb-2 only) à Very different from previous ARM processors § No CPSR register § Vector table contains addresses, not instructions § Processor automatically saves/restores state in exceptions § Only 2 processor modes (Thread/Handler) § No Coprocessor 15 3-stage pipeline with static branch prediction § Atypical Implementation § Fixed memory map § Integrated interrupt controller § Serial-Wire Debug 21 ARM Cortex-A8 Processor § Architecture v7-A § 14 stage pipeline § NEON media processor 22 Confidential 11
- 12. The Instruction Pipeline 23 The Instruction Pipeline § The ARM7TDMI uses a 3-stage pipeline in order to increase the speed of the flow of instructions to the processor § Allows several operations to be performed simultaneously, rather than serially ARM Thumb PC PC FETCH Instruction fetched from memory PC - 4 PC-2 DECODE Decoding of registers used in instruction Register(s) read from Register Bank PC - 8 PC - 4 EXECUTE Shift and ALU operation Write register(s) back to Register Bank § The PC points to the instruction being fetched, not executed § Debug tools will hide this from you § This is now part of the ARM Architecture and applies to all processors 24 Confidential 12
- 13. Optimal Pipelining Cycle 1 2 3 4 5 6 7 8 9 Operation ADD F D E SUB F D E ORR F D E M AND F D E ORR F D E EOR F D E W F - Fetch D - Decode E - Execute § All operations here are on registers (single cycle execution) § In this example it takes 6 clock cycles to execute 6 instructions § Clock cycles per Instruction (CPI) = 1 25 Branch Pipeline Example Cycle 1 2 3 4 5 6 7 8 9 Address Operation 0x8000 BL 0x8FEC F D E EL EA 0x8004 SUB F D 0x8008 ORR F M 0x8FEC AND F D E 0x8FF0 ORR F D E 0x8FF4 EOR F D E W F - Fetch D - Decode E – Execute L – Linkret A - Adjust § Breaking the pipeline § Note that the core is executing in ARM state 26 Confidential 13
- 14. Cortex-A8 Integer Pipeline Branch Mispredict Penalty Replay Penalty F0 F1 F2 D0 D1 D2 D3 D4 E0 E1 E2 E3 E4 E5 DEC Queue Early RAM DEC SEQ Shift ALU SAT BP WB ALU AGU DEC Score Regfile Update TLB board MUL Queue & Issue Remap Early Logic Route MUL1 MUL2 ADD WB PIPE0 DEC Branch DEC Pred. Reg Pending File BP ALU Instruction Fetch Replay Shift ALU SAT Update WB Queue PIPE1 Instruction Decode LOAD AGU RAM + Format BP WB TLB Fwd Update STORE Instruction Execute / Load Store § Optimising code to make use of the processor pipeline is very difficult § Leave it to the compiler!! 27 Reference Slides 28 Confidential 14
- 15. Reference Material § ARM ARM (“Architecture Reference Manual”) § ARM DDI 0100E covers v5TE DSP extensions § Can be purchased from booksellers - ISBN 0-201-737191 (Addison-Wesley) § Available for download from ARM’s website § ARM v7-M ARM available for download from ARM’s website § Contact ARM if you need a different version (v6, v7-AR, etc.) § Steve Furber “ARM system-on-chip architecture” - 2nd edition § ISBN 0-201-67519-6 (Addison-Wesley) § Sloss, Symes & Wright – “ARM System Developer's Guide” § ISBN: 1-55860-874-5 (Morgan Kaufman) § RVCT Assembler Guide § Available for download from ARM’s website § Technical Reference Manuals for processor core being used § Available for download from ARM’s website 29 Naming Conventions § ARMx1z (e.g. ARM710T) indicates cache & full MMU § ARMx2z (e.g. ARM720T) indicates cache, MMU & Process ID support § ARMx3z (e.g. ARM1136J-S) indicates physically mapped caches and MMU § ARMx4z (e.g. ARM740T) indicates cache and MPU § ARMx5z (e.g. ARM1156T2-S) indicates cache, MPU and error correcting memory § ARMx6z (e.g. ARM966E-S) indicates write buffer but no caches § ARMx7z (e.g. ARM1176JZ-S) indicates AXI bus, & physically mapped caches and MMU § ARMxy6 (e.g. ARM946E-S) indicates TCMs 30 Confidential 15
- 16. Which architecture is my processor? Processor core Architecture § ARM7TDMI family v4T § ARM720T, ARM740T § ARM9TDMI family v4T § ARM920T,ARM922T,ARM940T § ARM9E family v5TE, v5TEJ § ARM946E-S, ARM966E-S, ARM926EJ -S § ARM10E family v5TE, v5TEJ § ARM1020E, ARM1022E, ARM1026EJ -S § ARM11 family v6 § ARM1136J(F)-S v6 § ARM1156T2(F)-S v6T2 § ARM1176JZ(F)-S v6Z § ARM11 MPCore v6 § Cortex family § ARM Cortex -A8 v7-A § ARM Cortex -R4(F) v7-R § ARM Cortex -M3 v7-M § ARM Cortex -M1 v6-M § For ARM processor naming conventions and features, please see the Appendix 31 ARMv4T Cores: 7TDMI 720T 740T 920T 940T SA1100 Architecture von Neumann von Neumann von Neumann Harvard Harvard Harvard 16K Instr + 4K Instr + 4K 16K Instr + 8K Unified 8K Unified Cache None 16K Data Data 16K Data 4 words/line 4 words/line 8 words/line 4 words/line 4 words/line Associativity N/A 4-way 4-way 64- way 64- way 32- way TCM No No No No No No Random Replacement N/A Random Random Random Round Robin Round Robin Write Write Through Write Through N/A Write Through Write Through Write Back Strategy Write Back Write Back 8 Words 8 Words 16 Words 8 Words 8 Words Write Buffer None 4 Addresses 4 Addresses 4 Addresses 4 Addresses 4 Addresses MMU/MPU None MMU MPU MMU MPU MMU Hi Vectors No Yes No Yes Yes Yes Streaming N/A Yes Yes Yes Yes Yes Standby No No No Yes Yes Yes Mode 32 Confidential 16
- 17. ARMv5 Cores: 926EJ-S 946E-S 966E-S 968E-S 1026EJ-S XScale Architecture Harvard Harvard Harvard Harvard Harvard Harvard 4-128K Instr 0-1024K Instr None None 0-128K Instr 32K Instr Cache 4-128K Data 0-1024K Data 0-128K Data 32K Data 8 words/line 8 words/line 8 words/line 8 words/line Associativity 4-way 4-way N/A N/A 4-way 32- way 0-1024K Instr 0-1024K Instr 0-64M Instr 0-64M Instr 0-1024K Instr TCM No 0-1024K Data 0-1024K Data 0-64M Data 0-64M Data 0-1024K Data Random Random Random Random Replacement N/A N/A Round Robin Round Robin Round Robin Round Robin Write Write Through Write Through Write Through Write Through Write Through N/A Strategy Write Back Write Back Write Back Write Back Write Back 16 Words 12 Words 12 Words 8 Words 16 Words 8 x 16 Bytes Write Buffer Data or Data or Data or Data or 4 Addresses Coalescing Address Address Address Address MMU MMU/MPU MMU MPU None None MMU or MPU With extensions Hi Vectors Yes Yes Yes Yes Yes Yes Streaming Yes Yes N/A N/A Yes Yes Standby Yes Yes Yes Yes Yes Yes Mode 33 ARMv6 Cores: 1136EJ(F)- 1156T2(F)- 1176JZ(F)- MPCore11 S S S Architecture Harvard Harvard Harvard Harvard 4-64K Instr 0-64K Instr 4-64K Instr 16-64K Instr Cache 4-64K Data 0-64K Data 4-64K Data 16-64K Data 8 words/line 8 words/line 8 words/line 8 words/line Associativity 4-way 4-way 4-way 4-way 0-64K Instr 0-256K Instr 0-64K Instr TCM None 0-64K Data 0-256K Data 0-64K Data Replacemen Random Random Random Random t Round Robin Round Robin Round Robin Round Robin Write Write Through Write Through Write Through Write Through Strategy Write Back Write Back Write Back Write Back MMU/MPU MMU MPU MMU MMU Hi Vectors Yes Yes Yes Yes Streaming Yes Yes N/A Yes Standby Yes Yes Yes Yes Mode Bus AHB/APB AXI AXI AXI VFP Support Yes Yes Yes Yes 34 Confidential 17
- 18. Cortex Cores: Cortex-M3 Cortex-M1 Cortex-R4 Cortex-A8 Architecture Harvard Harvard Harvard Harvard None None 4-64K Instr 16 or 32 Instr Cache 4-64K Data 16 or 32 Data 8 words/line 16 words/line Associativity N/A N/A 4-way 4-way 0-1M Instr 0-8M Instr TCM None None 0-1M Data 0-8M Data Replacemen N/A N/A Random Random t Write Write Through Write Through N/A N/A Strategy Write Back Write Back MPU MMU/MPU MPU None MMU (optional) Hi Vectors No No Yes Yes Streaming N/A N/A Yes Yes Standby Yes Yes Yes Yes Mode Bus AHB Lite/APB AHB Lite/APB AXI AXI VFP Support No No Yes Yes 35 TrustZone Computing § TrustZone adds a “parallel world” to allow trusted programs and data to be safely separated from the OS and applications § Introduced for ARM1176, standard for ARMv7-A Cores § Features: § New Secure Monitor Mode: gate -keeper for secure state § New S-bit in CP15 to indicate when the processor is running in a secured state § Security state exposed on external bus accesses to permit security- aware memory and peripherals § Ability to restrict debug to non- secure state 36 Confidential 18
- 19. NEON Media Processor Features § Single Instruction Multiple Data (SIMD) Media Processor § Targets audio and video codecs, image and speech processing, graphics, baseband processing, and general signal processing § 3 Processing pipelines: Integer/fixed point, single precision floating point, IEEE vector floating point § Efficient data handling § Best use of available memory bandwidth § Eliminates data arrangement overhead § Operates on separate register file § SIMD Framework excellent target for compilers 37 End 38 Confidential 19