ASIC DESIGN FLOW
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This document outlines the typical ASIC design flow process. It begins with specification where the features and functionalities of the ASIC are defined. This is followed by RTL coding to develop the logic functionality in a hardware description language. Simulation and synthesis then convert the RTL into a gate-level netlist. Pre-layout timing analysis checks for timing issues. Then automatic place and route lays out the design on the chip. Back annotation adds layout parasitic information. Post-layout timing analysis checks for real timing violations. Logic verification confirms correct functionality. The final tapeout step sends the design for fabrication if all checks pass.
ASIC DESIGN FLOW
- 1. ASIC DESIGN FLOW Submitted To:- Submitted By:- Manju K. Chattopadhyay Purvi Medawala 14MTES11
- 2. TABLE OF CONTENTS Introduction ASIC Design Flow Specification RTL Coding Test Bench & Simulation Synthesis Pre-layout Timing Analysis APR Back Annotation Post-layout Timing Analysis Logic Verification Tapeout
- 3. What is ASIC ? Application Specific Integrated Circuit Build by connecting existing circuit blocks in new ways High speed, Lesser area & power consumption, more time to market
- 5. SPECIFICATION Features and functionalities of ASIC are defined Chip planning is performed Architecture and microarchitecture are derived
- 6. RTL CODING Microarchitecture converted into synthesizable RTL code containing logic functionalities Graphical Tools like Summit Design’s or Mentor Graphics are used Sometimes code is written manually
- 8. TEST BENCH AND SIMULATION Test bench created to simulate RTL code using HDL simulators Cadence’s Verilog XL, Mentor Graphic’s Modelsim are used Finally logically correct RTL code obtained
- 9. SYNTHESIS RTL code converted into optimized logic gate level representation Synthesis tools like Synopsys’s Design Compiler & Cadence’s Ambit used “technology library” file & “constraints file” used
- 10. PRE-LAYOUT TIMING ANALYSIS synthesized database along with timing information from the synthesis process used to perform a Static Timing Analysis Tweaking (making small changes) has to be done to correct any timing issues
- 11. AUTOMATIC PLACE AND ROUTE (APR) Layout is produced synthesized database together with timing information from synthesis is used to place the logic gates Designs have timing critical path
- 12. BACK ANNOTATION process where extraction for RC parasitics are made from the layout. path delay is calculated from these RC parasitics Back annotation is the step that bridges synthesis and physical layout
- 13. POST-LAYOUT TIMING ANALYSIS allows real timing violations such as hold and setup to be detected net interconnect delay information is fed into the timing analysis and any setup violation is fixed
- 14. LOGIC VERIFICATION the final check to ensure the design is correct functionally after additional timing information from layout Design is re-simulated using test benches with timing information from layout If there are failures, fix it by moving back to step 2 or step 8
- 15. TAPEOUT When design passes logical verification, its ready for fabrication The tapeout design is in the form of GDSII file, which will be accepted by the foundry
- 16. REFRENCES Verilog Coding for Logic Synthesis, edited by Weng Fook Lee, John Wiley and Sons, Inc. CMOS Digital Integrated Circuits , Analysis and Design by Sung-Mo Kang & Yusuf Leblebici, TMH
- 18. THANK YOU !