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Unit VI
Digital Systems
 Binary arithmetic; Number base
conversion; Boolean algebra:
simplification of Boolean functions
using K-maps; Logic gates; Design of
basic combinational circuits: adders,
multiplexers, de-multiplexers
Vellore Institute of Technology, Chennai
Campus, Chennai. 444
Contents
 Introduction
 Number Systems and Binary Arithmetic
 Number conversion
 Whole numbers and fractional numbers
 Binary addition and subtraction
 2’s complement logic for subtraction
 Logic Gates
 Identities and Laws, Demorgan’s Theorems
 Combinational Logic
 Half adder and full adder
Vellore Institute of Technology, Chennai
Campus, Chennai. 445
Introduction
 Hardware consists of a few simple building blocks
 These are called logic gates
 AND, OR, NOT, …
 NAND, NOR, XOR, …
 Logic gates are built using transistors
 NOT gate can be implemented by a single transistor
 AND gate requires 3 transistors
 Transistors are the fundamental devices
 Pentium consists of 3 million transistors
 Compaq Alpha consists of 9 million transistors
 Now we can build chips with more than 100 million
transistors
Vellore Institute of Technology, Chennai
Campus, Chennai. 446
Number system
 Binary
 Octal
 Decimal
 Hexadecimal
Vellore Institute of Technology, Chennai
Campus, Chennai. 447
Number system – A comparison
 The binary number system, also called the base-2 number
system, is a method of representing numbers that counts by
using combinations of only two numerals: zero (0) and one (1).
 Computers use the binary number system to manipulate and
store all of their data including numbers, words, videos,
graphics, and music.
 Binary system is its simple.
 More difficult to convert from binary to decimal and from
decimal to binary.
 Hexadecimal number is more convenient and compact way to
represent binary numbers because it is very easy to convert
from binary to hexadecimal and vice versa.
Vellore Institute of Technology, Chennai
Campus, Chennai. 448
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer
Binary Subtraction
By 1’s complement arithmetic
 write down 1’s complement of the
subtrahend.
 add this with the minuend.
 If the result of addition has a carry over then
it is dropped and an 1 is added in the last bit.
 If there is no carry over, then 1’s
complement of the result of addition is
obtained to get the final result and it is
negative.
Vellore Institute of Technology, Chennai
Campus, Chennai. 455
Examples
1. Evaluate 110101 – 100101
1’s complement of 10011 is 011010.
Minuend - 1 1 0 1 0 1
1’s complement of subtrahend - 0 1 1 0 1 0
Carry over - 1 0 0 1 1 1 1
1
0 1 0 0 0 0
The required difference is 10000
Vellore Institute of Technology, Chennai
Campus, Chennai. 456
Contd…
2. Evaluate 101011 – 111001
1’s complement of 111001 is 000110.
Minuend - 1 0 1 0 1 1
1’s complement - 0 0 0 1 1 0
1 1 0 0 0 1
Hence the answer is the complement of the
difference – 1 1 1 0
Vellore Institute of Technology, Chennai
Campus, Chennai. 457
Subtraction by 2’s Complement
 At first, the 2’s complement of the
subtrahend is found.
 Then it is added to the minuend.
 If the final carry over of the sum is 1, it is
dropped and the rest of the bits is the
result and is positive.
 If there is no carry over, the two’s
complement of the sum will be the result
and it is negative.
Vellore Institute of Technology, Chennai
Campus, Chennai. 458
Examples
 Evaluate 110110 – 10110
The numbers of bits in the subtrahend is 5 while that of minuend is 6. We
make the number of bits in the subtrahend equal to that of minuend by taking
a `0’ in the sixth place of the subtrahend.
Now, 2’s complement of 010110 is (101001 + 1)
i.e.101010.
Add this with the minuend.
1 1 0 1 1 0 Minuend
1 0 1 0 1 0 2’s complement of subtrahend
1 1 0 0 0 0 0 Result of addition and carry over
After dropping the carry over we get the result of
subtraction to be 100000.
Vellore Institute of Technology, Chennai
Campus, Chennai. 459
Review Questions
 Evaluate:
 11001 – 10011
 1001 – 1101
 10100.01 – 11011.10
 https://www.math-only-math.com/subtraction-by-1s-
complement.html
 https://www.math-only-math.com/subtraction-by-2s-
complement.html
Vellore Institute of Technology, Chennai
Campus, Chennai. 460
Contd…
 Convert (11.10101)2 into decimal (2)
 Find the 9’s complement of 546700 (2)
 Evaluate (3250)10 – (72532)10 using 10’s
complement arithmetic. (3)
 Evaluate (565.67)8 – (234.34)8 using 2’s
complement arithmetic. (3)
Vellore Institute of Technology, Chennai
Campus, Chennai. 461
Contd…
 i. Convert (11.10101)2 into decimal (2)
 ii. Find the 2’s complement of (D46)16
(2)
 iii. Evaluate (150)10 – (232)10 using 1’s
complement binary arithmetic. (3)
 iv. Evaluate (55.67)8 – (24.34)8 using 2’s
complement binary arithmetic. (3)
Vellore Institute of Technology, Chennai
Campus, Chennai. 462
Logic Gates
Boolean Algebra
Map Specification
Combinational Circuits
Flip-Flops
Sequential Circuits
Memory Components
Integrated Circuits
Digital Logic Circuits
Vellore Institute of Technology, Chennai
Campus, Chennai. 463
Logic levels
 Transistor-Transistor Logic (TTL)
Vellore Institute of Technology, Chennai
Campus, Chennai. 464
Contd…
Vellore Institute of Technology, Chennai
Campus, Chennai. 465
TTL samples
Vellore Institute of Technology, Chennai
Campus, Chennai. 466
Logic Levels
 Complementary metal-oxide-semiconductor (CMOS)
Vellore Institute of Technology, Chennai
Campus, Chennai. 467
CMOS samples
Vellore Institute of Technology, Chennai
Campus, Chennai. 468
Digital Logic Circuits
 Basics
 Logic Gates
 Boolean Algebra, properties,
functions
 Canonical and standard forms
 K-Map
VIT University, Chennai Campus, Chennai. 469
Logic Gates
Digital Computers
- Imply that the computer deals with digital information, i.e., it deals
with the information that is represented by binary digits
- Why BINARY ? instead of Decimal or other number system ?
* Consider electronic signal
signal
range
0 1 2 3 4 5 6 7 8 9
0 0 1 2 3 4 5 6 7 8 9
1 1 2 3 4 5 6 7 8 9 10
2 2 3 4 5 6 7 8 9 1011
3 3 4 5 6 7 8 9 101112
4 4 5 6 7 8 9 10111213
5 5 6 7 8 9 1011121314
6 6 7 8 9 101112131415
7 7 8 9 10111213141516
8 8 9 1011121314151617
9 9 101112131415161718
0
1 7
6
5
4
3
2
1
0
binary octal
0 1
0 1
1 10
0
1
* Consider the calculation cost - Add
Vellore Institute of Technology, Chennai
Campus, Chennai. 470
Basic Logic Block - Gate
Types of Basic Logic Blocks
- Combinational Logic Block
Logic Blocks whose output logic value
depends only on the input logic values
- Sequential Logic Block
Logic Blocks whose output logic value
depends on the input values and the
state (stored information) of the blocks
Functions of Gates can be described by
- Truth Table
- Boolean Function
- Karnaugh Map
Gate
.
.
.
Binary
Digital
Input
Signal
Binary
Digital
Output
Signal
Vellore Institute of Technology, Chennai
Campus, Chennai. 471
Digital Gates - Principles
Switching Circuits
The abstract logic described previously can be implemented as an
actual circuit. Switches are left open for logic 0 and closed for logic 1.
Two variable AND circuit X.Y
Reason: The lamp (LED) in above picture will GLOW when the switches X
AND Y are both closed
VIT University, Chennai Campus, Chennai. 472
Contd…
Switching Circuits
The abstract logic described previously can be implemented as an
actual circuit. Switches are left open for logic 0 and closed for logic 1.
Two variable OR circuit X + Y
Reason: The lamp (LED) in above picture will GLOW when the switch X OR
Y is closed
VIT University, Chennai Campus, Chennai. 473
Contd…
Switching Circuits
The abstract logic described previously can be implemented as an
actual circuit. Switches are left open for logic 0 and closed for logic 1.
Four variable circuit U.V.(X + Y)
Reason: The lamp (LED) in above picture will GLOW when the switch X OR
Y is closed AND U AND V is closed
VIT University, Chennai Campus, Chennai. 474
Truth Table A truth table is a means for describing how a logic circuit's output
depends on the logic levels present at the circuit's inputs.
In the following twos-inputs logic circuit, the table lists all possible combinations
of logic levels present at inputs X and Y along with the corresponding output level F =
X.Y
X Y F = X.Y
0 0 0
0 1 0
1 0 0
1 1 1
F = X.Y means that the ? Mark indicates AND gate
Logic Gates
 A logic gate is an electronic circuit/device
 Makes the logical decisions.
 To arrive at this decisions, the most common logic
gates used are
 OR, AND, NOT, NAND, and NOR gates.
 The NAND and NOR gates are called universal gates.
 The exclusive-OR gate is another logic gate which
can be constructed using AND, OR and NOT gate.
Logic gates have
 one or more inputs
 only one output
 The output is active only for certain input
combinations.
 Logic gates are the building blocks of any digital
circuit.
 Logic gates are also called switches.
 With the availability of integrated circuits, switches
have been replaced by TTL (Transistor Transistor
Logic) circuits and CMOS circuits.
Inversion
A small circle on an input or an output indicates
inversion. See the NOT, NAND and NOR gates given
below for examples.
Gates and Truth Tables
AND OR NOT
F = (x y)
X Y F
0 0 0
0 1 0
1 0 0
1 1 1
F = (x + y)
X Y F
0 0 0
0 1 1
1 0 1
1 1 1
F = (x )’
X F
0 1
1 0
F = x y
x
y
x
y
x
F = x + y F = x ‘
Gates and Truth Tables
NAND
F = (x y)’
X Y F
0 0 1
0 1 1
1 0 1
1 1 0
F = (x + y)’
X Y F
0 0 1
0 1 0
1 0 0
1 1 0
F = (x y)’
x
y
x
y
F = (x + y)’
NOR
Gates and Truth Tables
XOR
F = xy’ + x’y
X Y F
0 0 0
0 1 1
1 0 1
1 1 0
F = xy + x’y’
X Y F
0 0 1
0 1 0
1 0 0
1 1 1
F = xy
x
y
x
y
F = xy
XNOR
Universal Gates
 Can be used for implementing any logic gate or
any combination of these basic gates
 NAND and NOR gates are universal gates
Exercises in Gates
Identify the gate, write the algebraic function and draw the truth table
Exercises in Gates
Identify the gate, write the algebraic function and draw the truth table
NOR XOR
Exercises in Gates
Identify the gate, write the algebraic function and draw the truth table
NOR
F = (x + y)’
XOR
F = (xy’+x’y)
Exercises in Gates
Identify the gate, write the algebraic function and draw the truth table
NOR
F = (x + y)’
X Y F
0 0 1
0 1 0
1 0 0
1 1 0
XOR
F = (xy’+x’y)
X Y F
0 0 0
0 1 1
1 0 1
1 1 0
Digital Gates
A
X X = (A + B)’
B
Name Symbol Function Truth Table
AND
A X = A • B
X or
B X = AB
0 0 0
0 1 0
1 0 0
1 1 1
0 0 0
0 1 1
1 0 1
1 1 1
OR
A
X X = A + B
B
I A X X = A’
0 1
1 0
Buffer A X X = A
A X
0 0
1 1
NAND
A
X X = (AB)’
B
0 0 1
0 1 1
1 0 1
1 1 0
NOR
0 0 1
0 1 0
1 0 0
1 1 0
XOR
Exclusive OR
A X = A  B
X or
B X = A’B + AB’
0 0 0
0 1 1
1 0 1
1 1 0
A X = (A  B)’
X or
B X = A’B’+ AB
0 0 1
0 1 0
1 0 0
1 1 1
XNOR
Exclusive NOR
or Equivalence
A B X
A B X
A X
A B X
A B X
A B X
A B X
Vellore Institute of Technology, Chennai
Campus, Chennai. 487
Universal Gates
To facilitate the conversion to NAND and NOR logic, we
have two new graphic symbols for these gates.
NAND Gate
NOR Gate
Realization of logic function using NAND gates
Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W
The above expression can be implemented with three AND gates in first
stage and one OR gate in second stage as shown in figure.
STEP 1
Realization of logic function using NAND gates
Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W
If bubbles are introduced at AND gates output and OR gates inputs (the
same for NOR gates), the above circuit becomes as shown in figure. .
STEP 2
Realization of logic function using NAND gates
Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W
Now replace OR gate with input bubble with the NAND gate. Now we
have circuit which is fully implemented with just NAND gates.
STEP 3
Exercises (Assignment)
Obtain the following logic functions using
i. AND, OR, NOT logic gates
ii. NAND gates
iii. NOR gates
1. x.y’.z + x.y’z’ + x’.y’.z
2. xy + yz + yz’
3. xy + yz + y’z
4. x.y + x’.z + y.z
5. x’y’z’ + x’y’z + x’yz + x’yz’ + xy’z’ + xy’z
Exercises contd…
6. x’y’z’ + x’y’z + xy’z
7. xy’ + x’y
8. (x+y+z)(xyz)’
9. xy’ + yz’ + zx’
10. (a’+b’).(a’+b).(a+b’)

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BEEE 102L LECTURE NOTES -Boolean , Gates,Multiplexer

  • 1. Unit VI Digital Systems  Binary arithmetic; Number base conversion; Boolean algebra: simplification of Boolean functions using K-maps; Logic gates; Design of basic combinational circuits: adders, multiplexers, de-multiplexers Vellore Institute of Technology, Chennai Campus, Chennai. 444
  • 2. Contents  Introduction  Number Systems and Binary Arithmetic  Number conversion  Whole numbers and fractional numbers  Binary addition and subtraction  2’s complement logic for subtraction  Logic Gates  Identities and Laws, Demorgan’s Theorems  Combinational Logic  Half adder and full adder Vellore Institute of Technology, Chennai Campus, Chennai. 445
  • 3. Introduction  Hardware consists of a few simple building blocks  These are called logic gates  AND, OR, NOT, …  NAND, NOR, XOR, …  Logic gates are built using transistors  NOT gate can be implemented by a single transistor  AND gate requires 3 transistors  Transistors are the fundamental devices  Pentium consists of 3 million transistors  Compaq Alpha consists of 9 million transistors  Now we can build chips with more than 100 million transistors Vellore Institute of Technology, Chennai Campus, Chennai. 446
  • 4. Number system  Binary  Octal  Decimal  Hexadecimal Vellore Institute of Technology, Chennai Campus, Chennai. 447
  • 5. Number system – A comparison  The binary number system, also called the base-2 number system, is a method of representing numbers that counts by using combinations of only two numerals: zero (0) and one (1).  Computers use the binary number system to manipulate and store all of their data including numbers, words, videos, graphics, and music.  Binary system is its simple.  More difficult to convert from binary to decimal and from decimal to binary.  Hexadecimal number is more convenient and compact way to represent binary numbers because it is very easy to convert from binary to hexadecimal and vice versa. Vellore Institute of Technology, Chennai Campus, Chennai. 448
  • 12. Binary Subtraction By 1’s complement arithmetic  write down 1’s complement of the subtrahend.  add this with the minuend.  If the result of addition has a carry over then it is dropped and an 1 is added in the last bit.  If there is no carry over, then 1’s complement of the result of addition is obtained to get the final result and it is negative. Vellore Institute of Technology, Chennai Campus, Chennai. 455
  • 13. Examples 1. Evaluate 110101 – 100101 1’s complement of 10011 is 011010. Minuend - 1 1 0 1 0 1 1’s complement of subtrahend - 0 1 1 0 1 0 Carry over - 1 0 0 1 1 1 1 1 0 1 0 0 0 0 The required difference is 10000 Vellore Institute of Technology, Chennai Campus, Chennai. 456
  • 14. Contd… 2. Evaluate 101011 – 111001 1’s complement of 111001 is 000110. Minuend - 1 0 1 0 1 1 1’s complement - 0 0 0 1 1 0 1 1 0 0 0 1 Hence the answer is the complement of the difference – 1 1 1 0 Vellore Institute of Technology, Chennai Campus, Chennai. 457
  • 15. Subtraction by 2’s Complement  At first, the 2’s complement of the subtrahend is found.  Then it is added to the minuend.  If the final carry over of the sum is 1, it is dropped and the rest of the bits is the result and is positive.  If there is no carry over, the two’s complement of the sum will be the result and it is negative. Vellore Institute of Technology, Chennai Campus, Chennai. 458
  • 16. Examples  Evaluate 110110 – 10110 The numbers of bits in the subtrahend is 5 while that of minuend is 6. We make the number of bits in the subtrahend equal to that of minuend by taking a `0’ in the sixth place of the subtrahend. Now, 2’s complement of 010110 is (101001 + 1) i.e.101010. Add this with the minuend. 1 1 0 1 1 0 Minuend 1 0 1 0 1 0 2’s complement of subtrahend 1 1 0 0 0 0 0 Result of addition and carry over After dropping the carry over we get the result of subtraction to be 100000. Vellore Institute of Technology, Chennai Campus, Chennai. 459
  • 17. Review Questions  Evaluate:  11001 – 10011  1001 – 1101  10100.01 – 11011.10  https://www.math-only-math.com/subtraction-by-1s- complement.html  https://www.math-only-math.com/subtraction-by-2s- complement.html Vellore Institute of Technology, Chennai Campus, Chennai. 460
  • 18. Contd…  Convert (11.10101)2 into decimal (2)  Find the 9’s complement of 546700 (2)  Evaluate (3250)10 – (72532)10 using 10’s complement arithmetic. (3)  Evaluate (565.67)8 – (234.34)8 using 2’s complement arithmetic. (3) Vellore Institute of Technology, Chennai Campus, Chennai. 461
  • 19. Contd…  i. Convert (11.10101)2 into decimal (2)  ii. Find the 2’s complement of (D46)16 (2)  iii. Evaluate (150)10 – (232)10 using 1’s complement binary arithmetic. (3)  iv. Evaluate (55.67)8 – (24.34)8 using 2’s complement binary arithmetic. (3) Vellore Institute of Technology, Chennai Campus, Chennai. 462
  • 20. Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Logic Circuits Vellore Institute of Technology, Chennai Campus, Chennai. 463
  • 21. Logic levels  Transistor-Transistor Logic (TTL) Vellore Institute of Technology, Chennai Campus, Chennai. 464
  • 22. Contd… Vellore Institute of Technology, Chennai Campus, Chennai. 465
  • 23. TTL samples Vellore Institute of Technology, Chennai Campus, Chennai. 466
  • 24. Logic Levels  Complementary metal-oxide-semiconductor (CMOS) Vellore Institute of Technology, Chennai Campus, Chennai. 467
  • 25. CMOS samples Vellore Institute of Technology, Chennai Campus, Chennai. 468
  • 26. Digital Logic Circuits  Basics  Logic Gates  Boolean Algebra, properties, functions  Canonical and standard forms  K-Map VIT University, Chennai Campus, Chennai. 469
  • 27. Logic Gates Digital Computers - Imply that the computer deals with digital information, i.e., it deals with the information that is represented by binary digits - Why BINARY ? instead of Decimal or other number system ? * Consider electronic signal signal range 0 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 8 9 1 1 2 3 4 5 6 7 8 9 10 2 2 3 4 5 6 7 8 9 1011 3 3 4 5 6 7 8 9 101112 4 4 5 6 7 8 9 10111213 5 5 6 7 8 9 1011121314 6 6 7 8 9 101112131415 7 7 8 9 10111213141516 8 8 9 1011121314151617 9 9 101112131415161718 0 1 7 6 5 4 3 2 1 0 binary octal 0 1 0 1 1 10 0 1 * Consider the calculation cost - Add Vellore Institute of Technology, Chennai Campus, Chennai. 470
  • 28. Basic Logic Block - Gate Types of Basic Logic Blocks - Combinational Logic Block Logic Blocks whose output logic value depends only on the input logic values - Sequential Logic Block Logic Blocks whose output logic value depends on the input values and the state (stored information) of the blocks Functions of Gates can be described by - Truth Table - Boolean Function - Karnaugh Map Gate . . . Binary Digital Input Signal Binary Digital Output Signal Vellore Institute of Technology, Chennai Campus, Chennai. 471
  • 29. Digital Gates - Principles Switching Circuits The abstract logic described previously can be implemented as an actual circuit. Switches are left open for logic 0 and closed for logic 1. Two variable AND circuit X.Y Reason: The lamp (LED) in above picture will GLOW when the switches X AND Y are both closed VIT University, Chennai Campus, Chennai. 472
  • 30. Contd… Switching Circuits The abstract logic described previously can be implemented as an actual circuit. Switches are left open for logic 0 and closed for logic 1. Two variable OR circuit X + Y Reason: The lamp (LED) in above picture will GLOW when the switch X OR Y is closed VIT University, Chennai Campus, Chennai. 473
  • 31. Contd… Switching Circuits The abstract logic described previously can be implemented as an actual circuit. Switches are left open for logic 0 and closed for logic 1. Four variable circuit U.V.(X + Y) Reason: The lamp (LED) in above picture will GLOW when the switch X OR Y is closed AND U AND V is closed VIT University, Chennai Campus, Chennai. 474
  • 32. Truth Table A truth table is a means for describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. In the following twos-inputs logic circuit, the table lists all possible combinations of logic levels present at inputs X and Y along with the corresponding output level F = X.Y X Y F = X.Y 0 0 0 0 1 0 1 0 0 1 1 1 F = X.Y means that the ? Mark indicates AND gate
  • 33. Logic Gates  A logic gate is an electronic circuit/device  Makes the logical decisions.  To arrive at this decisions, the most common logic gates used are  OR, AND, NOT, NAND, and NOR gates.  The NAND and NOR gates are called universal gates.  The exclusive-OR gate is another logic gate which can be constructed using AND, OR and NOT gate.
  • 34. Logic gates have  one or more inputs  only one output  The output is active only for certain input combinations.  Logic gates are the building blocks of any digital circuit.  Logic gates are also called switches.  With the availability of integrated circuits, switches have been replaced by TTL (Transistor Transistor Logic) circuits and CMOS circuits.
  • 35. Inversion A small circle on an input or an output indicates inversion. See the NOT, NAND and NOR gates given below for examples.
  • 36. Gates and Truth Tables AND OR NOT F = (x y) X Y F 0 0 0 0 1 0 1 0 0 1 1 1 F = (x + y) X Y F 0 0 0 0 1 1 1 0 1 1 1 1 F = (x )’ X F 0 1 1 0 F = x y x y x y x F = x + y F = x ‘
  • 37. Gates and Truth Tables NAND F = (x y)’ X Y F 0 0 1 0 1 1 1 0 1 1 1 0 F = (x + y)’ X Y F 0 0 1 0 1 0 1 0 0 1 1 0 F = (x y)’ x y x y F = (x + y)’ NOR
  • 38. Gates and Truth Tables XOR F = xy’ + x’y X Y F 0 0 0 0 1 1 1 0 1 1 1 0 F = xy + x’y’ X Y F 0 0 1 0 1 0 1 0 0 1 1 1 F = xy x y x y F = xy XNOR
  • 39. Universal Gates  Can be used for implementing any logic gate or any combination of these basic gates  NAND and NOR gates are universal gates
  • 40. Exercises in Gates Identify the gate, write the algebraic function and draw the truth table
  • 41. Exercises in Gates Identify the gate, write the algebraic function and draw the truth table NOR XOR
  • 42. Exercises in Gates Identify the gate, write the algebraic function and draw the truth table NOR F = (x + y)’ XOR F = (xy’+x’y)
  • 43. Exercises in Gates Identify the gate, write the algebraic function and draw the truth table NOR F = (x + y)’ X Y F 0 0 1 0 1 0 1 0 0 1 1 0 XOR F = (xy’+x’y) X Y F 0 0 0 0 1 1 1 0 1 1 1 0
  • 44. Digital Gates A X X = (A + B)’ B Name Symbol Function Truth Table AND A X = A • B X or B X = AB 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR A X X = A + B B I A X X = A’ 0 1 1 0 Buffer A X X = A A X 0 0 1 1 NAND A X X = (AB)’ B 0 0 1 0 1 1 1 0 1 1 1 0 NOR 0 0 1 0 1 0 1 0 0 1 1 0 XOR Exclusive OR A X = A  B X or B X = A’B + AB’ 0 0 0 0 1 1 1 0 1 1 1 0 A X = (A  B)’ X or B X = A’B’+ AB 0 0 1 0 1 0 1 0 0 1 1 1 XNOR Exclusive NOR or Equivalence A B X A B X A X A B X A B X A B X A B X Vellore Institute of Technology, Chennai Campus, Chennai. 487
  • 45. Universal Gates To facilitate the conversion to NAND and NOR logic, we have two new graphic symbols for these gates. NAND Gate NOR Gate
  • 46. Realization of logic function using NAND gates Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W The above expression can be implemented with three AND gates in first stage and one OR gate in second stage as shown in figure. STEP 1
  • 47. Realization of logic function using NAND gates Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W If bubbles are introduced at AND gates output and OR gates inputs (the same for NOR gates), the above circuit becomes as shown in figure. . STEP 2
  • 48. Realization of logic function using NAND gates Consider the following SOP expression : F = W.X.Y + X.Y.Z + Y.Z.W Now replace OR gate with input bubble with the NAND gate. Now we have circuit which is fully implemented with just NAND gates. STEP 3
  • 49. Exercises (Assignment) Obtain the following logic functions using i. AND, OR, NOT logic gates ii. NAND gates iii. NOR gates 1. x.y’.z + x.y’z’ + x’.y’.z 2. xy + yz + yz’ 3. xy + yz + y’z 4. x.y + x’.z + y.z 5. x’y’z’ + x’y’z + x’yz + x’yz’ + xy’z’ + xy’z
  • 50. Exercises contd… 6. x’y’z’ + x’y’z + xy’z 7. xy’ + x’y 8. (x+y+z)(xyz)’ 9. xy’ + yz’ + zx’ 10. (a’+b’).(a’+b).(a+b’)