CAD: introduction to floorplanning
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This document discusses floorplanning, which is an important first step in physical design. There are two main approaches to floorplanning: simulated annealing and analytical formulation. Popular representations of geometric relationships used in floorplanning are normalized Polish expression, B*-tree, and sequence pair. The goal of floorplanning is to optimize metrics like area and wire length. Slicing floorplans can be represented by binary trees, while non-slicing floorplans use constraint graphs.
CAD: introduction to floorplanning
- 2. Floorplanning is the first major step in physical design; it is particularly important because the resulting floorplan affects all the subsequent steps in physical design, such as placement and routing. Floorplanning provides early feedback that: evaluates architectural decisions, estimates chip areas, and estimates delay and congestion caused by wiring.
- 3. Two popular approaches to floorplanning are: simulated annealing: simulated annealing- based floorplanning relies on the representation of the geometric relationship among modules and analytical formulation: an analytical approach usually captures the absolute relationship directly.
- 4. The representation of geometric relationship is done using three popular floorplan representations: normalized Polish expression B*-tree Sequence Pair These representations are efficient, flexible, and effective in modeling geometric relationships (e.g., left, right, above, and below relationships) among modules for floorplan designs.
- 5. Let B = {b1, b2, ..., bm} be a set of m rectangular modules whose respective width, height, and area are denoted by wi, hi, and ai, 1<= i <= m. Each module is free to rotate. Let (xi , yi) denote the coordinate of the bottom-left corner of module bi such that no two modules overlap with each other. The goal of floorplanning is to optimize a predefined cost metric such as a combination of the area (i.e., the minimum bounding rectangle of F ) and wire length (i.e., the sum of all interconnection lengths) induced by a floorplan. For modern floorplan designs, other costs such as routability, power, and thermal might also need to be considered.
- 6. two categories for discussions: Slicing floorplans: A slicing floorplan can be obtained by repetitively cutting the floorplan horizontally or vertically Non-slicing floorplans: it is not so in this case.
- 7. We can use a binary tree to represent a slicing floorplan. A slicing tree is a binary tree with modules at the leaves and cut types at the internal nodes. There are two cut types, H and V. The H cut divides the floorplan horizontally. Similarly, the V cut divides the floorplan vertically. Slicing floorplan may correspond to more than one slicing tree, because the order of the cut-line selections may be different.
- 8. Slicing floorplan Non-slicing floorplan
- 10. We use a horizontal constraint graph ( HCG) and a vertical constraint graph ( VCG) to model a non-slicing floorplan. The horizontal constraint graph defines the horizontal relations of modules, and the vertical constraint graph defines the vertical ones. In a constraint graph, a node represents a module. If there is an edge from node A to node B in the HCG ( VCG), then module A is at the left (bottom) of module B.
- 12. Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed
- 13. Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed
- 15. The goal of floorplanning is to optimize a predefined cost function, such as the area of a resulting floorplan given by the minimum bounding rectangle of the floorplan region. The floorplan area directly correlates to the chip silicon cost. The larger the area, the higher the silicon cost. The space in the floorplan bounding rectangle uncovered by any module is called white space or dead space.
Editor's Notes
- #5: The analytical approach applies mathematical programming that is composed of an objective function and a set of constraints.